Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84440?usp=email )
Change subject: amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery
......................................................................
amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery
For A/B recovery, it is better, even though it is not mandatory, to
put BIOS level 2 table next to its PSP level2. So the relative
addresses of BIOS table are the same. So all the data in B could be a
copy of A.
Identical binary test on all non A/B recovery platform.
Booting test on Majolica with A/B recovery enabled.
Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 10 insertions(+), 10 deletions(-)
Approvals:
Maximilian Brune: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 42d13d8..0de0475 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1770,11 +1770,17 @@
/* Do 2nd PSP directory followed by 1st */
integrate_psp_firmwares(&ctx,
amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
+ if (cb_config.recovery_ab)
+ integrate_bios_firmwares(&ctx,
+ amd_bios_table, BHDL2_COOKIE, &cb_config);
+
if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) {
/* Create a copy of PSP Directory 2 in the backup slot B.
Related biosdir2_b copy will be created later. */
integrate_psp_firmwares(&ctx,
amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
+ integrate_bios_firmwares(&ctx,
+ amd_bios_table, BHDL2_COOKIE, &cb_config);
} else {
/*
* Either the platform is using only
@@ -1790,6 +1796,8 @@
integrate_psp_firmwares(&ctx,
amd_psp_fw_table, PSP_COOKIE, &cb_config);
integrate_psp_levels(&ctx, &cb_config);
+ if (cb_config.recovery_ab)
+ integrate_bios_levels(&ctx, &cb_config);
} else {
/* flat: PSP 1 cookie and no pointer to 2nd table */
integrate_psp_firmwares(&ctx,
@@ -1805,21 +1813,13 @@
add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config);
}
- if (have_bios_tables(amd_bios_table)) {
+ if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) {
if (cb_config.multi_level) {
/* Do 2nd level BIOS directory followed by 1st */
integrate_bios_firmwares(&ctx,
amd_bios_table, BHDL2_COOKIE, &cb_config);
- if (cb_config.recovery_ab) {
- if (ctx.pspdir2_b != NULL) {
- integrate_bios_firmwares(&ctx,
- amd_bios_table, BHDL2_COOKIE,
- &cb_config);
- }
- } else {
- integrate_bios_firmwares(&ctx,
+ integrate_bios_firmwares(&ctx,
amd_bios_table, BHD_COOKIE, &cb_config);
- }
integrate_bios_levels(&ctx, &cb_config);
} else {
/* flat: BHD1 cookie and no pointer to 2nd table */
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Change subject: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory
......................................................................
Patch Set 4: Code-Review+2
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Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/55739?usp=email )
Change subject: [HACK, NOTFORMERGE] include/cper: change alignment in cper_ia32x64_ctx_sz_bytype
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> https://lore.kernel.org/lkml/20250221111516.1468261-1-patrick.rudolph@9elem…. […]
meant to paste this link https://lore.kernel.org/lkml/20250221081242.1411553-1-patrick.rudolph@9elem… which fixes this for x86
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Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/55739?usp=email )
Change subject: [HACK, NOTFORMERGE] include/cper: change alignment in cper_ia32x64_ctx_sz_bytype
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
https://lore.kernel.org/lkml/20250221111516.1468261-1-patrick.rudolph@9elem… should make the linux kernel spec-compliant, so no need to make coreboot not-spec compliant to produce the output that the kernel expects
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Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/blobs/+/86534/comment/3d5cca3e_7138eaf9?usp=e… :
PS2, Line 9: includes
> `, which includes`
Done
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Hello Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/blobs/+/86534?usp=email
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
......................................................................
soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
Update dram.elf, which includes:
- Add EMI clock pre setting and post setting.
BRANCH=rauru
BUG=b:378592077
TEST=Build pass, Bootup pass.
Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M soc/mediatek/mt8196/dram.elf
M soc/mediatek/mt8196/dram.elf.md5
M soc/mediatek/mt8196/dram_release_notes.txt
3 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/34/86534/3
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Zhaoqing Jiu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86552?usp=email )
Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86552/comment/8320e759_33e78d21?us… :
PS2, Line 7: HW protect temperature
> Adjust thermal trip point parameters
Done
https://review.coreboot.org/c/coreboot/+/86552/comment/da9206d5_b7954a7b?us… :
PS2, Line 9: Adjust HW protect temperature so HW will trigger interrupt at expected
: trip point.
> Adjust thermal trip point parameters so the thermal can trigger the interrupt at the expected trip p […]
Done
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Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
......................................................................
Patch Set 2: Code-Review+2 Verified+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/blobs/+/86534/comment/5251cd17_605cf6f1?usp=e… :
PS2, Line 9: includes
`, which includes`
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Change subject: soc/mediatek/mt8196: Disable HWRot's clocks
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86553/comment/49b657b1_b787aaaf?us… :
PS2, Line 10: save power.
> do you have the number ?
Done
https://review.coreboot.org/c/coreboot/+/86553/comment/230b149a_0b352d61?us… :
PS2, Line 14: OK
> passed
Done
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