coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery
by Felix Held (Code Review) 21 Feb '25

21 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84440?usp=email ) Change subject: amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery ...................................................................... amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery For A/B recovery, it is better, even though it is not mandatory, to put BIOS level 2 table next to its PSP level2. So the relative addresses of BIOS table are the same. So all the data in B could be a copy of A. Identical binary test on all non A/B recovery platform. Booting test on Majolica with A/B recovery enabled. Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 10 insertions(+), 10 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 42d13d8..0de0475 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1770,11 +1770,17 @@ /* Do 2nd PSP directory followed by 1st */ integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + if (cb_config.recovery_ab) + integrate_bios_firmwares(&ctx, + amd_bios_table, BHDL2_COOKIE, &cb_config); + if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { /* Create a copy of PSP Directory 2 in the backup slot B. Related biosdir2_b copy will be created later. */ integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + integrate_bios_firmwares(&ctx, + amd_bios_table, BHDL2_COOKIE, &cb_config); } else { /* * Either the platform is using only @@ -1790,6 +1796,8 @@ integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); integrate_psp_levels(&ctx, &cb_config); + if (cb_config.recovery_ab) + integrate_bios_levels(&ctx, &cb_config); } else { /* flat: PSP 1 cookie and no pointer to 2nd table */ integrate_psp_firmwares(&ctx, @@ -1805,21 +1813,13 @@ add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config); } - if (have_bios_tables(amd_bios_table)) { + if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) { if (cb_config.multi_level) { /* Do 2nd level BIOS directory followed by 1st */ integrate_bios_firmwares(&ctx, amd_bios_table, BHDL2_COOKIE, &cb_config); - if (cb_config.recovery_ab) { - if (ctx.pspdir2_b != NULL) { - integrate_bios_firmwares(&ctx, - amd_bios_table, BHDL2_COOKIE, - &cb_config); - } - } else { - integrate_bios_firmwares(&ctx, + integrate_bios_firmwares(&ctx, amd_bios_table, BHD_COOKIE, &cb_config); - } integrate_bios_levels(&ctx, &cb_config); } else { /* flat: BHD1 cookie and no pointer to 2nd table */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6 Gerrit-Change-Number: 84440 Gerrit-PatchSet: 13 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory
by Krystian Hebel (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Filip Lewiński, Michał Żygowski. Krystian Hebel has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83734?usp=email ) Change subject: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5340165579174eb8ab26dfaae452896d6646c900 Gerrit-Change-Number: 83734 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 13:23:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[master]: [HACK, NOTFORMERGE] include/cper: change alignment in cper_ia32x64_ct...
by Felix Held (Code Review) 21 Feb '25

21 Feb '25

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/55739?usp=email ) Change subject: [HACK, NOTFORMERGE] include/cper: change alignment in cper_ia32x64_ctx_sz_bytype ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > https://lore.kernel.org/lkml/20250221111516.1468261-1-patrick.rudolph@9elem…. […] meant to paste this link https://lore.kernel.org/lkml/20250221081242.1411553-1-patrick.rudolph@9elem… which fixes this for x86 -- To view, visit https://review.coreboot.org/c/coreboot/+/55739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2501ea260d85710957358e831b9ab57f8556e6b Gerrit-Change-Number: 55739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 12:35:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[master]: [HACK, NOTFORMERGE] include/cper: change alignment in cper_ia32x64_ct...
by Felix Held (Code Review) 21 Feb '25

21 Feb '25

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/55739?usp=email ) Change subject: [HACK, NOTFORMERGE] include/cper: change alignment in cper_ia32x64_ctx_sz_bytype ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: https://lore.kernel.org/lkml/20250221111516.1468261-1-patrick.rudolph@9elem… should make the linux kernel spec-compliant, so no need to make coreboot not-spec compliant to produce the output that the kernel expects -- To view, visit https://review.coreboot.org/c/coreboot/+/55739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2501ea260d85710957358e831b9ab57f8556e6b Gerrit-Change-Number: 55739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 11:50:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in blobs[main]: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
by Jarried Lin (Code Review) 21 Feb '25

21 Feb '25

Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86534?usp=email ) Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/86534/comment/3d5cca3e_7138eaf9?usp=e… : PS2, Line 9: includes > `, which includes` Done -- To view, visit https://review.coreboot.org/c/blobs/+/86534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Gerrit-Change-Number: 86534 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 08:23:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
by Jarried Lin (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Jarried Lin. Hello Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/86534?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 ...................................................................... soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 Update dram.elf, which includes: - Add EMI clock pre setting and post setting. BRANCH=rauru BUG=b:378592077 TEST=Build pass, Bootup pass. Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/dram.elf M soc/mediatek/mt8196/dram.elf.md5 M soc/mediatek/mt8196/dram_release_notes.txt 3 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/34/86534/3 -- To view, visit https://review.coreboot.org/c/blobs/+/86534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Gerrit-Change-Number: 86534 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust thermal trip point parameters
by Zhaoqing Jiu (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Zhaoqing Jiu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86552?usp=email ) Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86552/comment/8320e759_33e78d21?us… : PS2, Line 7: HW protect temperature > Adjust thermal trip point parameters Done https://review.coreboot.org/c/coreboot/+/86552/comment/da9206d5_b7954a7b?us… : PS2, Line 9: Adjust HW protect temperature so HW will trigger interrupt at expected : trip point. > Adjust thermal trip point parameters so the thermal can trigger the interrupt at the expected trip p […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Gerrit-Change-Number: 86552 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 08:04:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust thermal trip point parameters
by Zhaoqing Jiu (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Zhaoqing Jiu has uploaded a new patch set (#3) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86552?usp=email ) Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters ...................................................................... soc/mediatek/mt8196: Adjust thermal trip point parameters Adjust thermal trip point parameters so the thermal can trigger the interrupt at the expected trip point. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f --- M src/soc/mediatek/mt8196/include/soc/thermal_internal.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/86552/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Gerrit-Change-Number: 86552 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
by Yu-Ping Wu (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86534?usp=email ) Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 ...................................................................... Patch Set 2: Code-Review+2 Verified+1 (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/86534/comment/5251cd17_605cf6f1?usp=e… : PS2, Line 9: includes `, which includes` -- To view, visit https://review.coreboot.org/c/blobs/+/86534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Gerrit-Change-Number: 86534 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 08:04:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Disable HWRot's clocks
by Jarried Lin (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86553?usp=email ) Change subject: soc/mediatek/mt8196: Disable HWRot's clocks ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86553/comment/49b657b1_b787aaaf?us… : PS2, Line 10: save power. > do you have the number ? Done https://review.coreboot.org/c/coreboot/+/86553/comment/230b149a_0b352d61?us… : PS2, Line 14: OK > passed Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a Gerrit-Change-Number: 86553 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 07:53:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit February 2025