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Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
......................................................................
Patch Set 4:
(4 comments)
Patchset:
PS3:
> how common is this code? i'd expect this to not only be correct for glinda; not sure though if this […]
I dont have information about other SoC.
Commit Message:
https://review.coreboot.org/c/coreboot/+/85640/comment/f363a6ab_9a04c362?us… :
PS3, Line 8:
> Sure. […]
Done
File src/soc/amd/glinda/cpu.c:
https://review.coreboot.org/c/coreboot/+/85640/comment/d296b8fb_425dde54?us… :
PS3, Line 43: fill_cpu_cache_info
> I guess you imply that: […]
Done
https://review.coreboot.org/c/coreboot/+/85640/comment/f050311a_6691a10e?us… :
PS3, Line 60: struct cpu_cache_info info_list
> Yes.
Done
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Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info
......................................................................
Patch Set 2:
(1 comment)
File src/arch/x86/include/arch/cpu.h:
https://review.coreboot.org/c/coreboot/+/85639/comment/a50585fe_4f746262?us… :
PS1, Line 280: uint8_t
> 'unique_id' sounds good to me; that's probably even a bit more descriptive. […]
Acknowledged
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85640?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
......................................................................
soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
Glinda SoC has separate caches for Classic and Dense cores, uniquely
identified using a cache ID computed from the core index.
Ensure `soc_fill_cpu_cache_info` computes the L3 cache size while
considering the cache ID, enabling accurate cache size calculation.
Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6
Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com>
---
M src/soc/amd/glinda/cpu.c
1 file changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/4
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Hello Angel Pons, Jérémy Compostella, build bot (Jenkins),
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Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info
......................................................................
arch/x86/cpu: Add element id to struct cpu_cache_info
Introduce a new variable, unique_id, in struct cpu_cache_info to track
the cache ID for SoCs with multiple CPU caches at the same level.
Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5
Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com>
---
M src/arch/x86/include/arch/cpu.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85639/2
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Hello Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, build bot (Jenkins),
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Change subject: arch/x86/cpu: Add helper function to compute cache
......................................................................
arch/x86/cpu: Add helper function to compute cache
Consider special requirements for computing cache size in certain SoCs,
such as `soc/amd/glinda`.
Use the helper function to implement SoC-specific logic for computing
cache size.
Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449
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---
M src/arch/x86/cpu_common.c
M src/arch/x86/include/arch/cpu.h
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Change subject: mb/google/trulo: Update GPIO wake pins
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/trulo/gpio.c:
https://review.coreboot.org/c/coreboot/+/86555/comment/f0115f4c_8ef5e4e0?us… :
PS2, Line 61: PAD_CFG_GPI_APIC
this is now getting register as IOAPIC and not like shared interrupt in existing implementation
```
PAD_CFG_GPI_IRQ_WAKE
```
As you have configured this PIN as IOAPIC then we don't need any additional GPE handling
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Change subject: mb/google/trulo: Update GPIO wake pins
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/trulo/gpio.c:
https://review.coreboot.org/c/coreboot/+/86555/comment/460fb570_9566948b?us… :
PS2, Line 245: PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
this should move into a separate CL as you are locking down the EC wake PIN
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Change subject: util/cbmem: Use uintN_t instead of uN int types
......................................................................
Patch Set 1: Code-Review+2
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Change subject: util/cbmem: Use uintN_t instead of uN int types
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Set Ready For Review
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