coreboot-gerrit February 2025

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Naresh Solanki (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Patrick Rudolph, Paul Menzel. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 4: (4 comments) Patchset: PS3: > how common is this code? i'd expect this to not only be correct for glinda; not sure though if this […] I dont have information about other SoC. Commit Message: https://review.coreboot.org/c/coreboot/+/85640/comment/f363a6ab_9a04c362?us… : PS3, Line 8: > Sure. […] Done File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/d296b8fb_425dde54?us… : PS3, Line 43: fill_cpu_cache_info > I guess you imply that: […] Done https://review.coreboot.org/c/coreboot/+/85640/comment/f050311a_6691a10e?us… : PS3, Line 60: struct cpu_cache_info info_list > Yes. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Feb 2025 21:32:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Naresh Solanki (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 2: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/85639/comment/a50585fe_4f746262?us… : PS1, Line 280: uint8_t > 'unique_id' sounds good to me; that's probably even a bit more descriptive. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Feb 2025 21:31:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Naresh Solanki (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Angel Pons, Jérémy Compostella, Naresh Solanki, Patrick Rudolph, Paul Menzel. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85640?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper Glinda SoC has separate caches for Classic and Dense cores, uniquely identified using a cache ID computed from the core index. Ensure `soc_fill_cpu_cache_info` computes the L3 cache size while considering the cache ID, enabling accurate cache size calculation. Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/glinda/cpu.c 1 file changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Naresh Solanki (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Angel Pons, Jérémy Compostella, Naresh Solanki. Hello Angel Pons, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85639?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... arch/x86/cpu: Add element id to struct cpu_cache_info Introduce a new variable, unique_id, in struct cpu_cache_info to track the cache ID for SoCs with multiple CPU caches at the same level. Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/arch/x86/include/arch/cpu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85639/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Naresh Solanki (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune. Hello Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85638?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... arch/x86/cpu: Add helper function to compute cache Consider special requirements for computing cache size in certain SoCs, such as `soc/amd/glinda`. Use the helper function to implement SoC-specific logic for computing cache size. Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85638/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Subrata Banik (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86555?usp=email ) Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/trulo/gpio.c: https://review.coreboot.org/c/coreboot/+/86555/comment/f0115f4c_8ef5e4e0?us… : PS2, Line 61: PAD_CFG_GPI_APIC this is now getting register as IOAPIC and not like shared interrupt in existing implementation ``` PAD_CFG_GPI_IRQ_WAKE ``` As you have configured this PIN as IOAPIC then we don't need any additional GPE handling -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Feb 2025 20:24:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Subrata Banik (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86555?usp=email ) Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/trulo/gpio.c: https://review.coreboot.org/c/coreboot/+/86555/comment/460fb570_9566948b?us… : PS2, Line 245: PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), this should move into a separate CL as you are locking down the EC wake PIN -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Feb 2025 20:22:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/cbmem: Use uintN_t instead of uN int types
by Felix Singer (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Elyes Haouas, Jakub "Kuba" Czapiga. Felix Singer has posted comments on this change by Jakub "Kuba" Czapiga. ( https://review.coreboot.org/c/coreboot/+/86556?usp=email ) Change subject: util/cbmem: Use uintN_t instead of uN int types ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a Gerrit-Change-Number: 86556 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 21 Feb 2025 17:17:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/cbmem: Use uintN_t instead of uN int types
by Jakub "Kuba" Czapiga (Code Review) 21 Feb '25

21 Feb '25

Jakub "Kuba" Czapiga has posted comments on this change by Jakub "Kuba" Czapiga. ( https://review.coreboot.org/c/coreboot/+/86556?usp=email ) Change subject: util/cbmem: Use uintN_t instead of uN int types ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a Gerrit-Change-Number: 86556 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Feb 2025 15:10:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Move common functions to gpio_eint_v2.c
by Matt DeVillier (Code Review) 21 Feb '25

21 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86541?usp=email ) Change subject: soc/mediatek/mt8196: Move common functions to gpio_eint_v2.c ...................................................................... soc/mediatek/mt8196: Move common functions to gpio_eint_v2.c Move gpio_get_eint_reg() and gpio_calc_eint_pos_bit() to common code to avoid redundant definitions for other platforms such as MT8189. BUG=b:379008996 BRANCH=none TEST=build passed. Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Change-Id: Id21f627a49f730f3a0db786a148f81806aeba287 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86541 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/gpio_eint_v2.c A src/soc/mediatek/common/include/soc/gpio_eint_v2.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/gpio_eint.c 4 files changed, 87 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/gpio_eint_v2.c b/src/soc/mediatek/common/gpio_eint_v2.c new file mode 100644 index 0000000..5e848fe --- /dev/null +++ b/src/soc/mediatek/common/gpio_eint_v2.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/gpio_eint_v2.h> + +void gpio_calc_eint_pos_bit(gpio_t gpio, u32 *pos, u32 *bit) +{ + uint32_t idx = gpio.id; + + *pos = 0; + *bit = 0; + + if (idx >= eint_data_len) + return; + + uint8_t index = eint_data[idx].index; + + *pos = index / MAX_EINT_REG_BITS; + *bit = index % MAX_EINT_REG_BITS; +} + +struct eint_regs *gpio_get_eint_reg(gpio_t gpio) +{ + uint32_t idx = gpio.id; + uintptr_t addr; + + if (idx >= eint_data_len) + return NULL; + + switch (eint_data[idx].instance) { + case EINT_E: + addr = EINT_E_BASE; + break; + case EINT_S: + addr = EINT_S_BASE; + break; + case EINT_W: + addr = EINT_W_BASE; + break; + case EINT_N: + addr = EINT_N_BASE; + break; + case EINT_C: + addr = EINT_C_BASE; + break; + default: + printk(BIOS_ERR, "%s: Failed to look up a valid EINT base for %d\n", + __func__, idx); + return NULL; + } + + return (void *)addr; +} diff --git a/src/soc/mediatek/common/include/soc/gpio_eint_v2.h b/src/soc/mediatek/common/include/soc/gpio_eint_v2.h new file mode 100644 index 0000000..6f4acc6 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/gpio_eint_v2.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_GPIO_EINT_V2_H__ +#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_GPIO_EINT_V2_H__ + +#include <stdint.h> + +enum { + EINT_INVALID = 0, + EINT_E, + EINT_S, + EINT_W, + EINT_N, + EINT_C, +}; + +struct eint_info { + uint8_t instance; + uint8_t index; +}; + +extern const struct eint_info eint_data[]; +extern const size_t eint_data_len; + +#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_GPIO_EINT_V2_H__ */ diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 85b670a..1793104 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -3,7 +3,8 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y) all-y += ../common/flash_controller.c -all-y += ../common/gpio.c ../common/gpio_op.c gpio.c gpio_eint.c +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c +all-y += ../common/gpio_eint_v2.c gpio_eint.c all-y += ../common/i2c.c i2c.c all-y += ../common/pll.c pll.c all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8196/gpio_eint.c b/src/soc/mediatek/mt8196/gpio_eint.c index f24860d..9263e9e 100644 --- a/src/soc/mediatek/mt8196/gpio_eint.c +++ b/src/soc/mediatek/mt8196/gpio_eint.c @@ -1,29 +1,14 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This file is created based on MT8196_EINT_Datasheet * Chapter number: 1 */ -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/gpio.h> +#include <commonlib/bsd/helpers.h> +#include <soc/gpio_eint_v2.h> -enum { - EINT_INVALID = 0, - EINT_E, - EINT_S, - EINT_W, - EINT_N, - EINT_C, -}; - -struct eint_info { - uint8_t instance; - uint8_t index; -}; - -static struct eint_info eint_data[] = { +const struct eint_info eint_data[] = { /* instance, index */ [0] = { EINT_W, 0 }, [1] = { EINT_W, 1 }, @@ -258,51 +243,4 @@ }; _Static_assert(ARRAY_SIZE(eint_data) == 293, "Incorrect eint_data size"); -void gpio_calc_eint_pos_bit(gpio_t gpio, u32 *pos, u32 *bit) -{ - uint32_t idx = gpio.id; - - *pos = 0; - *bit = 0; - - if (idx >= ARRAY_SIZE(eint_data)) - return; - - uint8_t index = eint_data[idx].index; - - *pos = index / MAX_EINT_REG_BITS; - *bit = index % MAX_EINT_REG_BITS; -} - -struct eint_regs *gpio_get_eint_reg(gpio_t gpio) -{ - uint32_t idx = gpio.id; - uintptr_t addr; - - if (idx >= ARRAY_SIZE(eint_data)) - return NULL; - - switch (eint_data[idx].instance) { - case EINT_E: - addr = EINT_E_BASE; - break; - case EINT_S: - addr = EINT_S_BASE; - break; - case EINT_W: - addr = EINT_W_BASE; - break; - case EINT_N: - addr = EINT_N_BASE; - break; - case EINT_C: - addr = EINT_C_BASE; - break; - default: - printk(BIOS_ERR, "%s: Failed to look up a valid EINT base for %d\n", - __func__, idx); - return NULL; - } - - return (void *)addr; -} +const size_t eint_data_len = ARRAY_SIZE(eint_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/86541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id21f627a49f730f3a0db786a148f81806aeba287 Gerrit-Change-Number: 86541 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit February 2025