coreboot-gerrit February 2025

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Alexander Couzens, Angel Pons, Felix Singer, Jan Philipp Groß, Paul Menzel. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 9: (5 comments) File src/mainboard/lenovo/m900/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74187/comment/778095cf_5b6b69be?us… : PS8, Line 42: # FSP Configuration > Remove comment, seems superfluous. Done File src/mainboard/lenovo/m900/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74187/comment/3365dc70_466ad06e?us… : PS8, Line 16: // global NVS and variables > Remove comment, seems superfluous. Done https://review.coreboot.org/c/coreboot/+/74187/comment/a72ea643_9e92881f?us… : PS8, Line 19: // CPU > Remove comment, seems superfluous. Done https://review.coreboot.org/c/coreboot/+/74187/comment/a4c93106_83d9071c?us… : PS8, Line 22: Scope (\_SB) { : > `Device (\_SB. […] Done File src/mainboard/lenovo/m900/ramstage.c: https://review.coreboot.org/c/coreboot/+/74187/comment/653b7a28_bebf27ac?us… : PS8, Line 8: /* Configure pads prior to SiliconInit() in case there's any : * dependencies during hardware initialization. */ : g > We usually don't configure GPIOs prior to FSP-S anymore, since various FSPs reconfigured them later […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 23 Feb 2025 06:05:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Alexander Couzens, Angel Pons, Felix Singer, Jan Philipp Groß, Nicholas Chin, Paul Menzel. Hello Alexander Couzens, Felix Singer, Jan Philipp Groß, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74187?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Code-Review+1 by Jan Philipp Groß, Verified+1 by build bot (Jenkins) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) The mainboard is marked IQ1X0MS, though it is also known as the MS-7988. The Small Form Factor version was used for this port, though the Mini Tower seems to use the exact same board. Other systems such as the ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre 700-25ISH appear to use the same PCB with different configurations of components. All the code in this port was originally copied from the Asrock H110M and then modified to match the actual configuration of the M900. The VBT was extracted using `intelvbttool -l -v data.vbt` while running version FWKTBFA of the vendor firmware. Working: - Boots to Linux with SeaBIOS 1.16.3 - Boots to Linux with EDK2 (MrChromebox uefipayload_202408) - Display Ports - VGA port - PCIe slots - Console over serial port - Front and rear USB 3.0 ports and internal USB2.0 headers - Front and rear audio jacks - Internal speaker - SATA ports 1-4 (5 and 6 are not populated on the M900) - Hardware monitoring via nct6683 kernel module - Gigabit Ethernet - S3 suspend/resume Unknown/untested: - M.2 E-key slot - Parallel port header - PS/2 Mouse/Keyboard via KB_MS1 header - TPM Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/lenovo/m900/Kconfig A src/mainboard/lenovo/m900/Kconfig.name A src/mainboard/lenovo/m900/Makefile.mk A src/mainboard/lenovo/m900/acpi/ec.asl A src/mainboard/lenovo/m900/acpi/superio.asl A src/mainboard/lenovo/m900/board_info.txt A src/mainboard/lenovo/m900/bootblock.c A src/mainboard/lenovo/m900/cmos.default A src/mainboard/lenovo/m900/cmos.layout A src/mainboard/lenovo/m900/data.vbt A src/mainboard/lenovo/m900/devicetree.cb A src/mainboard/lenovo/m900/dsdt.asl A src/mainboard/lenovo/m900/gma-mainboard.ads A src/mainboard/lenovo/m900/gpio.h A src/mainboard/lenovo/m900/hda_verb.c A src/mainboard/lenovo/m900/ramstage.c A src/mainboard/lenovo/m900/romstage.c 17 files changed, 731 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74187/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[S] Change in coreboot[main]: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage
by Name of user not set (Code Review) 22 Feb '25

22 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph. Hello Intel coreboot Reviewers, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86562?usp=email to look at the new patch set (#2). Change subject: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage ...................................................................... src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage Refactor stack guard code in romstage. It's just for improving readability. :) Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Signed-off-by: melongmelong <knw0507(a)naver.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 31 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86562/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Gerrit-Change-Number: 86562 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1005756 Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph

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[S] Change in coreboot[main]: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage.
by Name of user not set (Code Review) 22 Feb '25

22 Feb '25

Name of user not set #1005756 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86562?usp=email ) Change subject: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage. ...................................................................... src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage. Refactor stack guard code in romstage. It's just for improving readability. :) Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Signed-off-by: melongmelong <knw0507(a)naver.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 31 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86562/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 63a83ab..a2dec35 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -15,14 +15,14 @@ /* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 +#define NUM_STACK_GUARDS 64 +#define STACK_GUARD 0xdeadbeef -void __noreturn romstage_main(void) +static u32 *stack_guard_set(void) { int i; - const int num_guards = 64; - const u32 stack_guard = 0xdeadbeef; - u32 *stack_base; u32 size; + u32 *stack_base; const size_t stack_size = MAX(CONFIG_DCACHE_BSP_STACK_SIZE, DCACHE_RAM_ROMSTAGE_STACK_SIZE); @@ -34,8 +34,33 @@ printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n", size); + /* Set stack guard */ stack_base = (u32 *)(_ecar_stack - size); + for (i = 0; i < NUM_STACK_GUARDS; i++) + stack_base[i] = STACK_GUARD; + + return stack_base; +} + +static void stack_guard_check(u32 *stack_base) +{ + int i; + + if (stack_base == NULL) { + die("Cannot check stack guard because NULL stack base.\n"); + } + + /* Check the stack. */ + for (i = 0; i < NUM_STACK_GUARDS; i++) { + if (stack_base[i] == STACK_GUARD) + continue; + printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + } +} + +void __noreturn romstage_main(void) +{ /* Disable breakpoint since stack is intentionally corrupted */ stack_canary_breakpoint_remove(); @@ -51,8 +76,7 @@ * report the instruction pointer immediately, which can hint at which function * may be using too much stack. FSP might disable HW breakpoints, though. */ - for (i = 0; i < num_guards; i++) - stack_base[i] = stack_guard; + u32 *stack_base = stack_guard_set(); stack_canary_breakpoint_init(); @@ -73,12 +97,7 @@ mainboard_romstage_entry(); - /* Check the stack. */ - for (i = 0; i < num_guards; i++) { - if (stack_base[i] == stack_guard) - continue; - printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); - } + stack_guard_check(stack_base); if (CONFIG(SMM_TSEG)) smm_list_regions(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Gerrit-Change-Number: 86562 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1005756

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Felix Singer (Code Review) 22 Feb '25

22 Feb '25

Attention is currently required from: Alexander Couzens, Angel Pons, Nicholas Chin, Paul Menzel. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 8: Code-Review+1 (5 comments) File src/mainboard/lenovo/m900/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74187/comment/2acfd89e_e97c975b?us… : PS8, Line 42: # FSP Configuration Remove comment, seems superfluous. File src/mainboard/lenovo/m900/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74187/comment/495f8ee9_5cd9c7e1?us… : PS8, Line 16: // global NVS and variables Remove comment, seems superfluous. https://review.coreboot.org/c/coreboot/+/74187/comment/c2c4f63d_3b84ba98?us… : PS8, Line 19: // CPU Remove comment, seems superfluous. https://review.coreboot.org/c/coreboot/+/74187/comment/f3d95ba6_b25a0d95?us… : PS8, Line 22: Scope (\_SB) { : `Device (\_SB.PCI0)` File src/mainboard/lenovo/m900/ramstage.c: https://review.coreboot.org/c/coreboot/+/74187/comment/b76c639d_0cc710ae?us… : PS8, Line 8: /* Configure pads prior to SiliconInit() in case there's any : * dependencies during hardware initialization. */ : g We usually don't configure GPIOs prior to FSP-S anymore, since various FSPs reconfigured them later causing issues. Please have a look at clevo/cml-u/ramstage.c how it's done there. -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 8 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 23 Feb 2025 05:20:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table
by Subrata Banik (Code Review) 22 Feb '25

22 Feb '25

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Wonkyu Kim. Subrata Banik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/84872/comment/6d7dc02b_37f28d66?us… : PS8, Line 316: _V4 any reason why we skipped `_v3`? File src/soc/intel/common/block/include/intelblocks/cse_telemetry_v4.h: https://review.coreboot.org/c/coreboot/+/84872/comment/6a021a74_e1400324?us… : PS8, Line 41: SOC_INTEL_COMMON_CSE_TELEMETRY_V4_H nit ``` /* SOC_INTEL_COMMON_CSE_TELEMETRY_V4_H */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 23 Feb 2025 04:56:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: libpayload/drivers/usb/ehci: Remove "else" after a "break"
by Elyes Haouas (Code Review) 22 Feb '25

22 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86560?usp=email ) Change subject: libpayload/drivers/usb/ehci: Remove "else" after a "break" ...................................................................... libpayload/drivers/usb/ehci: Remove "else" after a "break" "else" is not useful after a "break". Change-Id: I0f511b8c4349ec64916b631c32d5db9487f24c9c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M payloads/libpayload/drivers/usb/ehci.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/86560/1 diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 822fdb1..991dc02 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -382,13 +382,13 @@ if (remaining <= 0) { cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE; break; - } else { - qtd_t *next = dma_memalign(64, sizeof(qtd_t)); - if (!next) - goto oom; - cur->next_qtd = virt_to_phys(next); - cur = next; } + + qtd_t *next = dma_memalign(64, sizeof(qtd_t)); + if (!next) + goto oom; + cur->next_qtd = virt_to_phys(next); + cur = next; } /* create QH */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f511b8c4349ec64916b631c32d5db9487f24c9c Gerrit-Change-Number: 86560 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: libpayload/drivers/usb/uhci: Remove "else" after "return"
by Elyes Haouas (Code Review) 22 Feb '25

22 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86559?usp=email ) Change subject: libpayload/drivers/usb/uhci: Remove "else" after "return" ...................................................................... libpayload/drivers/usb/uhci: Remove "else" after "return" "else" is not useful after a "return". Change-Id: I8950ad576a0252529258978935dc31ba53028b28 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M payloads/libpayload/drivers/usb/uhci.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86559/1 diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 7590ab3..1c6520f 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -429,12 +429,11 @@ virt_to_phys(td) & ~(FLISTP_QH | FLISTP_TERMINATE); td = wait_for_completed_qh(dev->controller, UHCI_INST(dev->controller)->qh_data); - if (td == 0) { + if (td == 0) return 0; - } else { - td_dump(td); - return 1; - } + + td_dump(td); + return 1; } /* finalize == 1: if data is of packet aligned size, add a zero length packet */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8950ad576a0252529258978935dc31ba53028b28 Gerrit-Change-Number: 86559 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: payloads: Get rid of whitespaces before tab
by Elyes Haouas (Code Review) 22 Feb '25

22 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86558?usp=email ) Change subject: payloads: Get rid of whitespaces before tab ...................................................................... payloads: Get rid of whitespaces before tab Change-Id: I4a20d844252870e97a5c07d77e882138f6a74f42 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M payloads/external/tint/generate_core.sh M payloads/external/tint/tintify_core.sh M payloads/libpayload/arch/arm/virtual.c M payloads/libpayload/crypto/sha1.c M payloads/libpayload/curses/curses.h M payloads/libpayload/curses/form/form.h M payloads/libpayload/curses/form/fty_generic.c M payloads/libpayload/curses/form/fty_regex.c M payloads/libpayload/curses/menu/m_global.c M payloads/libpayload/drivers/serial/ipq806x.c M payloads/libpayload/drivers/video/graphics.c M payloads/libpayload/include/arm/arch/cache.h M payloads/libpayload/include/queue.h M payloads/libpayload/libc/getopt_long.c M payloads/libpayload/libc/memory.c M payloads/libpayload/libc/printf.c M payloads/libpayload/libc/qsort.c M payloads/libpayload/libc/string.c 18 files changed, 67 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/86558/1 diff --git a/payloads/external/tint/generate_core.sh b/payloads/external/tint/generate_core.sh index 834906b..0aca41f 100755 --- a/payloads/external/tint/generate_core.sh +++ b/payloads/external/tint/generate_core.sh @@ -8,14 +8,14 @@ ############################################################################## # # USAGE: -# ./generate_core.sh <buildgcc> <corescript> prepare_before_patch +# ./generate_core.sh <buildgcc> <corescript> prepare_before_patch # where -# buildgcc - path to input buildgcc script -# corescript - path to output core part script -# prepare_before_patch - optional argument to insert prepare_${package} -# call into the unpack_and_patch function, e.g. -# for removing some files with rm command -# in order to reduce the size of patch file +# buildgcc - path to input buildgcc script +# corescript - path to output core part script +# prepare_before_patch - optional argument to insert prepare_${package} +# call into the unpack_and_patch function, e.g. +# for removing some files with rm command +# in order to reduce the size of patch file # ############################################################################## diff --git a/payloads/external/tint/tintify_core.sh b/payloads/external/tint/tintify_core.sh index 0cd6599..e1cecfa 100755 --- a/payloads/external/tint/tintify_core.sh +++ b/payloads/external/tint/tintify_core.sh @@ -8,8 +8,8 @@ ################################################################################ # # USAGE: -# ./tintify_core.sh <corescript> <tintified> \ -# <TINT_BASE_URL> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM> +# ./tintify_core.sh <corescript> <tintified> \ +# <TINT_BASE_URL> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM> # where # corescript - path to input core script # tintified - path to output tint script diff --git a/payloads/libpayload/arch/arm/virtual.c b/payloads/libpayload/arch/arm/virtual.c index cfc7af1..d720302 100644 --- a/payloads/libpayload/arch/arm/virtual.c +++ b/payloads/libpayload/arch/arm/virtual.c @@ -54,10 +54,10 @@ 0ULL << 54 | /* PN. 0:Not restricted */ \ 0ULL << 53 | /* PXN. 0:Not restricted */ \ 1 << 10 | /* AF. 1:Accessed. This is to prevent access \ - * fault when accessed for the first time */ \ + * fault when accessed for the first time */ \ 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \ 0 << 5 | /* NS. 0:Output address is in Secure space */ \ - 0 << 1 | /* block/table. 0:block entry */ \ + 0 << 1 | /* block/table. 0:block entry */ \ 1 << 0 /* validity. 1:valid */ \ ) #define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2)) diff --git a/payloads/libpayload/crypto/sha1.c b/payloads/libpayload/crypto/sha1.c index 5f54431..b2ef689 100644 --- a/payloads/libpayload/crypto/sha1.c +++ b/payloads/libpayload/crypto/sha1.c @@ -195,7 +195,7 @@ * @param data Pointer to the input data that shall be hashed. * @param len Length of the input data (in bytes). * @param buf Buffer which will hold the resulting hash (must be at - * least 20 bytes in size). + * least 20 bytes in size). * @return Pointer to the output buffer where the hash is stored. */ u8 *sha1(const u8 *data, size_t len, u8 *buf) diff --git a/payloads/libpayload/curses/curses.h b/payloads/libpayload/curses/curses.h index 96fa9ac..4919231 100644 --- a/payloads/libpayload/curses/curses.h +++ b/payloads/libpayload/curses/curses.h @@ -909,7 +909,7 @@ * These pseudo functions are always implemented as macros: */ -#define getyx(win,y,x) (y = getcury(win), x = getcurx(win)) +#define getyx(win,y,x) (y = getcury(win), x = getcurx(win)) #define getbegyx(win,y,x) (y = getbegy(win), x = getbegx(win)) #define getmaxyx(win,y,x) (y = getmaxy(win), x = getmaxx(win)) #define getparyx(win,y,x) (y = getpary(win), x = getparx(win)) @@ -950,8 +950,8 @@ #define getparx(win) ((win)?(win)->_parx:ERR) #define getpary(win) ((win)?(win)->_pary:ERR) -#define wstandout(win) (wattrset(win,A_STANDOUT)) -#define wstandend(win) (wattrset(win,A_NORMAL)) +#define wstandout(win) (wattrset(win,A_STANDOUT)) +#define wstandend(win) (wattrset(win,A_NORMAL)) #define wattron(win,at) wattr_on(win, NCURSES_CAST(attr_t, at), NULL) #define wattroff(win,at) wattr_off(win, NCURSES_CAST(attr_t, at), NULL) @@ -1272,7 +1272,7 @@ #define WACS_PLUS WACS_SSSS #define WACS_S1 NCURSES_WACS('o') /* scan line 1 */ -#define WACS_S9 NCURSES_WACS('s') /* scan line 9 */ +#define WACS_S9 NCURSES_WACS('s') /* scan line 9 */ #define WACS_DIAMOND NCURSES_WACS('`') /* diamond */ #define WACS_CKBOARD NCURSES_WACS('a') /* checker board */ #define WACS_DEGREE NCURSES_WACS('f') /* degree symbol */ diff --git a/payloads/libpayload/curses/form/form.h b/payloads/libpayload/curses/form/form.h index 2f55e42..584767a 100644 --- a/payloads/libpayload/curses/form/form.h +++ b/payloads/libpayload/curses/form/form.h @@ -111,7 +111,7 @@ *********/ typedef struct formnode { - unsigned short status; /* flags */ + unsigned short status; /* flags */ short rows; /* size in rows */ short cols; /* size in cols */ int currow; /* current row in field window */ @@ -148,7 +148,7 @@ struct typenode * right; /* ptr to operand for | */ void* (*makearg)(va_list *); /* make fieldtype arg */ - void* (*copyarg)(const void *); /* copy fieldtype arg */ + void* (*copyarg)(const void *); /* copy fieldtype arg */ void (*freearg)(void *); /* free fieldtype arg */ #if NCURSES_INTEROP_FUNCS @@ -315,7 +315,7 @@ void (* const free_arg)(void *)); extern NCURSES_EXPORT(int) set_fieldtype_choice (FIELDTYPE *, bool (* const next_choice)(FIELD *,const void *), - bool (* const prev_choice)(FIELD *,const void *)); + bool (* const prev_choice)(FIELD *,const void *)); /******************* * FIELD routines * diff --git a/payloads/libpayload/curses/form/fty_generic.c b/payloads/libpayload/curses/form/fty_generic.c index 439afcc..ff6e432 100644 --- a/payloads/libpayload/curses/form/fty_generic.c +++ b/payloads/libpayload/curses/form/fty_generic.c @@ -81,7 +81,7 @@ | Function : FIELDTYPE *_nc_generic_fieldtype( | bool (* const field_check)(FIELD *,const void *), | bool (* const char_check) (int, const void *), -| bool (*const next)(FORM*,FIELD*,const void*), +| bool (*const next)(FORM*,FIELD*,const void*), | bool (*const prev)(FORM*,FIELD*,const void*), | void (*freecallback)(void*)) | diff --git a/payloads/libpayload/curses/form/fty_regex.c b/payloads/libpayload/curses/form/fty_regex.c index 2c0a4ca..071cdc2 100644 --- a/payloads/libpayload/curses/form/fty_regex.c +++ b/payloads/libpayload/curses/form/fty_regex.c @@ -64,7 +64,7 @@ return 0; } -#define INIT register char *sp = RegEx_Init(instring); +#define INIT register char *sp = RegEx_Init(instring); #define GETC() (*sp++) #define PEEKC() (*sp) #define UNGETC(c) (--sp) diff --git a/payloads/libpayload/curses/menu/m_global.c b/payloads/libpayload/curses/menu/m_global.c index 4509996..f207cb6 100644 --- a/payloads/libpayload/curses/menu/m_global.c +++ b/payloads/libpayload/curses/menu/m_global.c @@ -69,7 +69,7 @@ (chtype)A_REVERSE, /* Attribute for selection */ (chtype)A_NORMAL, /* Attribute for nonselection */ (chtype)A_UNDERLINE, /* Attribute for inactive */ - ' ', /* Pad character */ + ' ', /* Pad character */ (Menu_Hook)0, /* Menu init */ (Menu_Hook)0, /* Menu term */ (Menu_Hook)0, /* Item init */ diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index e267d57..e62d6dc 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -34,7 +34,7 @@ #define IPQ_UART_DM_IMR(base) (((u8 *)(base)) + 0x14) #define IPQ_UART_DM_IPR(base) (((u8 *)(base)) + 0x18) #define IPQ_UART_DM_IRDA(base) (((u8 *)(base)) + 0x38) -#define IPQ_UART_DM_MISR(base) (((u8 *)(base)) + 0x10) +#define IPQ_UART_DM_MISR(base) (((u8 *)(base)) + 0x10) #define IPQ_UART_DM_MR1(base) (((u8 *)(base)) + 0x00) #define IPQ_UART_DM_MR2(base) (((u8 *)(base)) + 0x04) #define IPQ_UART_DM_NO_CHARS_FOR_TX(base) (((u8 *)(base)) + 0x040) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 632a283..9032803 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -190,8 +190,8 @@ /* * Transform a vector: - * x' = x * a_x + offset_x - * y' = y * a_y + offset_y + * x' = x * a_x + offset_x + * y' = y * a_y + offset_y */ static int transform_vector(struct vector *out, const struct vector *in, diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index b4e292e..db98e770 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -46,8 +46,8 @@ #define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ #define SCTLR_Z (1 << 11) /* Branch prediction enable */ #define SCTLR_I (1 << 12) /* Instruction cache enable */ -#define SCTLR_V (1 << 13) /* Low/high exception vectors */ -#define SCTLR_RR (1 << 14) /* Round Robin select */ +#define SCTLR_V (1 << 13) /* Low/high exception vectors */ +#define SCTLR_RR (1 << 14) /* Round Robin select */ /* Bits 16:15 are reserved */ #define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ /* Bit 18 is reserved */ diff --git a/payloads/libpayload/include/queue.h b/payloads/libpayload/include/queue.h index c9ac701..70a0307 100644 --- a/payloads/libpayload/include/queue.h +++ b/payloads/libpayload/include/queue.h @@ -393,7 +393,7 @@ if (((elm)->field.sqx_next = XSIMPLEQ_XOR(head, \ (elm)->field.sqx_next)->field.sqx_next) \ == XSIMPLEQ_XOR(head, NULL)) \ - (head)->sqx_last = \ + (head)->sqx_last = \ XSIMPLEQ_XOR(head, &(elm)->field.sqx_next); \ } while (0) @@ -563,7 +563,7 @@ #define CIRCLEQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ for ((var) = CIRCLEQ_LAST(head, headname); \ - (var) != CIRCLEQ_END(head) && \ + (var) != CIRCLEQ_END(head) && \ ((tvar) = CIRCLEQ_PREV(var, headname, field), 1); \ (var) = (tvar)) diff --git a/payloads/libpayload/libc/getopt_long.c b/payloads/libpayload/libc/getopt_long.c index c0303cf..41495e7 100644 --- a/payloads/libpayload/libc/getopt_long.c +++ b/payloads/libpayload/libc/getopt_long.c @@ -81,7 +81,7 @@ /* return values */ #define BADCH (int)'?' #define BADARG ((*options == ':') ? (int)':' : (int)'?') -#define INORDER (int)1 +#define INORDER (int)1 #define EMSG (char*)"" diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c index fff295e..78163c3 100644 --- a/payloads/libpayload/libc/memory.c +++ b/payloads/libpayload/libc/memory.c @@ -120,8 +120,8 @@ * @param s2 Pointer to the second area to compare. * @param n Size of the first area in bytes (both must have the same length). * @return If n is 0, return zero. Otherwise, return a value less than, equal - * to, or greater than zero if s1 is found less than, equal to, or - * greater than s2 respectively. + * to, or greater than zero if s1 is found less than, equal to, or + * greater than s2 respectively. */ static int default_memcmp(const void *s1, const void *s2, size_t n) diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c index 3edf166..0c85a2a 100644 --- a/payloads/libpayload/libc/printf.c +++ b/payloads/libpayload/libc/printf.c @@ -364,26 +364,26 @@ * Print string formatted according to the fmt parameter and variadic arguments. * Each formatting directive must have the following form: * - * \% [ FLAGS ] [ WIDTH ] [ .PRECISION ] [ TYPE ] CONVERSION + * \% [ FLAGS ] [ WIDTH ] [ .PRECISION ] [ TYPE ] CONVERSION * * FLAGS:@n - * - "#" Force to print prefix.For \%o conversion, the prefix is 0, for + * - "#" Force to print prefix.For \%o conversion, the prefix is 0, for * \%x and \%X prefixes are 0x and 0X and for conversion \%b the * prefix is 0b. * - * - "-" Align to left. + * - "-" Align to left. * - * - "+" Print positive sign just as negative. + * - "+" Print positive sign just as negative. * - * - " " If the printed number is positive and "+" flag is not set, + * - " " If the printed number is positive and "+" flag is not set, * print space in place of sign. * - * - "0" Print 0 as padding instead of spaces. Zeroes are placed between + * - "0" Print 0 as padding instead of spaces. Zeroes are placed between * sign and the rest of the number. This flag is ignored if "-" * flag is specified. * * WIDTH:@n - * - Specify the minimal width of a printed argument. If it is bigger, + * - Specify the minimal width of a printed argument. If it is bigger, * width is ignored. If width is specified with a "*" character instead of * number, width is taken from parameter list. And integer parameter is * expected before parameter for processed conversion specification. If @@ -391,7 +391,7 @@ * set. * * PRECISION:@n - * - Value precision. For numbers it specifies minimum valid numbers. + * - Value precision. For numbers it specifies minimum valid numbers. * Smaller numbers are printed with leading zeroes. Bigger numbers are not * affected. Strings with more than precision characters are cut off. Just * as with width, an "*" can be used used instead of a number. An integer @@ -400,37 +400,37 @@ * second one for precision. * * TYPE:@n - * - "hh" Signed or unsigned char.@n - * - "h" Signed or unsigned short.@n - * - "" Signed or unsigned int (default value).@n - * - "l" Signed or unsigned long int.@n - * - "ll" Signed or unsigned long long int.@n + * - "hh" Signed or unsigned char.@n + * - "h" Signed or unsigned short.@n + * - "" Signed or unsigned int (default value).@n + * - "l" Signed or unsigned long int.@n + * - "ll" Signed or unsigned long long int.@n * * * CONVERSION:@n - * - % Print percentile character itself. + * - % Print percentile character itself. * - * - c Print single character. + * - c Print single character. * - * - s Print zero terminated string. If a NULL value is passed as + * - s Print zero terminated string. If a NULL value is passed as * value, "(NULL)" is printed instead. * - * - P, p Print value of a pointer. Void * value is expected and it is + * - P, p Print value of a pointer. Void * value is expected and it is * printed in hexadecimal notation with prefix (as with \%#X / \%#x * for 32-bit or \%#X / \%#x for 64-bit long pointers). * - * - b Print value as unsigned binary number. Prefix is not printed by + * - b Print value as unsigned binary number. Prefix is not printed by * default. (Nonstandard extension.) * - * - o Print value as unsigned octal number. Prefix is not printed by + * - o Print value as unsigned octal number. Prefix is not printed by * default. * - * - d, i Print signed decimal number. There is no difference between d + * - d, i Print signed decimal number. There is no difference between d * and i conversion. * - * - u Print unsigned decimal number. + * - u Print unsigned decimal number. * - * - X, x Print hexadecimal number with upper- or lower-case. Prefix is + * - X, x Print hexadecimal number with upper- or lower-case. Prefix is * not printed by default. * * All other characters from fmt except the formatting directives are printed in @@ -465,7 +465,7 @@ if (i > j) { if ((retval = printf_putnchars(&fmt[j], (size_t) (i - j), ps)) < 0) - return retval; + return retval; counter += retval; } @@ -569,7 +569,7 @@ case 's': if ((retval = print_string(va_arg(ap, char *), width, precision, flags, ps)) < 0) - return retval; + return retval; counter += retval; j = i + 1; goto next_char; @@ -676,7 +676,7 @@ if (i > j) { if ((retval = printf_putnchars(&fmt[j], (u64) (i - j), ps)) < 0) - return retval; + return retval; counter += retval; } diff --git a/payloads/libpayload/libc/qsort.c b/payloads/libpayload/libc/qsort.c index aad2aa3..2fd62ff 100644 --- a/payloads/libpayload/libc/qsort.c +++ b/payloads/libpayload/libc/qsort.c @@ -39,11 +39,11 @@ /* * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function". */ -#define swapcode(TYPE, parmi, parmj, n) { \ - size_t i = (n) / sizeof (TYPE); \ - TYPE *pi = (TYPE *) (parmi); \ - TYPE *pj = (TYPE *) (parmj); \ - do { \ +#define swapcode(TYPE, parmi, parmj, n) { \ + size_t i = (n) / sizeof (TYPE); \ + TYPE *pi = (TYPE *) (parmi); \ + TYPE *pj = (TYPE *) (parmj); \ + do { \ TYPE t = *pi; \ *pi++ = *pj; \ *pj++ = t; \ @@ -70,7 +70,7 @@ } else \ swapfunc(a, b, es, swaptype) -#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) +#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) static __inline char * med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *)) diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index a1b7d4d..98aeff1 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -41,8 +41,8 @@ * @param s1 The first string. * @param s2 The second string. * @return Returns a value less than zero, if s1 is shorter than s2. Returns - * zero, if s1 equals s2. Returns a value greater than zero, if - * s1 is longer than s2. + * zero, if s1 equals s2. Returns a value greater than zero, if + * s1 is longer than s2. */ int strcasecmp(const char *s1, const char *s2) { @@ -84,8 +84,8 @@ * @param s1 The first string. * @param s2 The second string. * @return Returns a value less than zero, if s1 is shorter than s2. Returns - * zero, if s1 equals s2. Returns a value greater than zero, if - * s1 is longer than s2. + * zero, if s1 equals s2. Returns a value greater than zero, if + * s1 is longer than s2. */ int strcmp(const char *s1, const char *s2) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a20d844252870e97a5c07d77e882138f6a74f42 Gerrit-Change-Number: 86558 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[master]: cbfstool: Import minimal set of files from flashmap
by Elyes Haouas (Code Review) 22 Feb '25

22 Feb '25

Attention is currently required from: Sol Boucher. Elyes Haouas has posted comments on this change by Sol Boucher. ( https://review.coreboot.org/c/coreboot/+/9940?usp=email ) Change subject: cbfstool: Import minimal set of files from flashmap ...................................................................... Patch Set 6: (1 comment) File util/cbfstool/flashmap/fmap.c: https://review.coreboot.org/c/coreboot/+/9940/comment/9486bff2_ec911203?usp… : PS6, Line 669: memcpy(&buf[total_size - fmap_size(fmap) + 1], : fmap, : fmap_size(fmap) + 1); it gives: ‘memcpy’ forming offset 56 is out of the bounds [0, 56] [-Warray-bounds=] 593 | memcpy(&buf[total_size - fmap_size(fmap) + 1], | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 594 | fmap, | ~~~~~ 595 | fmap_size(fmap) + 1); | ~~~~~~~~~~~~~~~~~~~~ -- To view, visit https://review.coreboot.org/c/coreboot/+/9940?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida33f81509abc1cf2e532435adbbf31919d96bd8 Gerrit-Change-Number: 9940 Gerrit-PatchSet: 6 Gerrit-Owner: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Sol Boucher <solb(a)chromium.org> Gerrit-Comment-Date: Sat, 22 Feb 2025 16:04:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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