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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
......................................................................
Patch Set 21:
(1 comment)
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85454/comment/a4a5d1ad_8950f7c4?us… :
PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> Combining the comment from a similar discussion here:
> https://review.coreboot.org/c/coreboot/+/86452/comment/84dc3ced_2fc8ae13/
>
> I acknowledge there are 2 problems which are coming in the way of common code:
> 1) UPD name changes during each generation of SoCs
> 2) New UPD requirement for ESOL in the future.
>
> Those problems can be addressed through one or more of the following:
> 1) fill_base_esol_fsp_params() that are common/base to all SoCs. We can provide the default implementation in the common code. We can communicate to Intel and ask them to not change the name for these UPDs. If the UPD names change even after that, then we can provide an override to fill_base_esol_fsp_params() in the SoC specific way.
> 2) Add soc_fill_additional_esol_fsp_params() to support new UPDs. The default implementation does nothing, but the SoC specific UPDs can be filled by the concerned code. Again we can do this when we have to cross that bridge.
> 3) Versioning scheme as suggested earlier by Julius.
>
> Even if the suggested improvements does not stand the test of time, they will definitely reduce code and logic duplication
There are at least two angles to this request to create common code using eSOL:
1. Julius wants to leverage the code between MTL and PTL because the number of UPDs is the same in both eSOL implementations. Also, the names look the same at this point.
2. Karthik wants to avoid using #if/#endif guards in each SoC code base that implements an override for platform_display_early_shutdown_notification. Instead, he suggests using common code like ux_inform_user_of_poweroff_operation, which takes an FSP UPD pointer and updates the required UPDs. Currently, the SoC override might exist in each SoC and circle back to the #1 angle.
There are few reasons why we can't implement a common layer:
In the IA common code model, we intentionally avoided making common code based on FSP-UPD because the FSP team never guaranteed to use the same UPD names across multiple SOC generations.
- UPD names can change
- New UPDs may be added
- UPDs can be divided based on SoC IP block, like `VgaInit`, which is now part of `m_cfg->VgaInit`, can be implemented in FSP as a nested data structure like `m_cfg->PreMemDisplay->VgaInit`.
this idea of implementing common code based on the UPD variable names:
- The common block might need more overrides or #if/#endif guards to handle different SoC variations.
- Creating a folder structure as suggested by Julius could solve the problem, but it wouldn't be any better than the existing proposal, where each SoC layer has its dedicated `platform_display_early_shutdown_notification` API implementation.
- We might end up with multiple versions of the common block (e.g., `fsp_esol_2024`, `fsp_esol_2025`, `fsp_esol_2026`, etc.) as it evolves each year, which would require us to move unnecessary folders into the common block.
- The volatile SoC block was never designed to be moved into IA common code.
- If the guideline is to implement common code based on UPD name commonality, there are many better candidates than just eSOL.
Overall, I believe that trying to common things based on UPD variable names is not a good idea, and I would strongly oppose it.
As suggested by Jeremy, there are ample code blocks that exist into each SoC block which can be revisited to make it common. I would like to emphasize that need rather using common code for eSOL.
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Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM
......................................................................
Patch Set 2:
(2 comments)
File src/soc/mediatek/mt8196/thermal_sram.c:
https://review.coreboot.org/c/coreboot/+/86551/comment/7c8b6d40_e0922721?us… :
PS2, Line 71: int
uint32_t
https://review.coreboot.org/c/coreboot/+/86551/comment/497c7f80_158f7feb?us… :
PS2, Line 71: int
unint32_t ?
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Change subject: soc/mediatek/mt8196: Disable HWRot's clocks
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86553/comment/669dcb1b_eef307a1?us… :
PS3, Line 9: are
is
https://review.coreboot.org/c/coreboot/+/86553/comment/4fc2d2d7_492b76f7?us… :
PS3, Line 10: This is a Vcore sub-block item that decreases SOC power
: consumption from 120mW to 90mW.
This patch is a subitem of Vcore power consumption improvement. The whole work improves SoC power consumption from 120mW to 90mW in suspend.
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(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
......................................................................
soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
Update dram.elf, which includes:
- Add EMI clock pre setting and post setting.
BRANCH=rauru
BUG=b:378592077
TEST=Build pass, Bootup pass.
Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M soc/mediatek/mt8196/dram.elf
M soc/mediatek/mt8196/dram.elf.md5
M soc/mediatek/mt8196/dram_release_notes.txt
3 files changed, 9 insertions(+), 1 deletion(-)
Approvals:
Yu-Ping Wu: Verified; Looks good to me, approved
Yidi Lin: Looks good to me, approved
diff --git a/soc/mediatek/mt8196/dram.elf b/soc/mediatek/mt8196/dram.elf
index a39b8f9..cd3dc83 100644
--- a/soc/mediatek/mt8196/dram.elf
+++ b/soc/mediatek/mt8196/dram.elf
Binary files differ
diff --git a/soc/mediatek/mt8196/dram.elf.md5 b/soc/mediatek/mt8196/dram.elf.md5
index c62a77b..aa78653 100644
--- a/soc/mediatek/mt8196/dram.elf.md5
+++ b/soc/mediatek/mt8196/dram.elf.md5
@@ -1 +1 @@
-eb5a6b2b584df19a461297b35ca69b1a *dram.elf
+ee9a89634430162b3d10e1a16f191bc7 *dram.elf
diff --git a/soc/mediatek/mt8196/dram_release_notes.txt b/soc/mediatek/mt8196/dram_release_notes.txt
index 9cb9afb..ec16e64 100644
--- a/soc/mediatek/mt8196/dram_release_notes.txt
+++ b/soc/mediatek/mt8196/dram_release_notes.txt
@@ -12,3 +12,11 @@
- CL:*7518650 mt8196: SLC: Port SLC driver
- CL:*7842174 mtk-dramk/mt8196: Sync to MediaTek's preloader version 20241121
+
+# 16174.34.0
+
+1. An official build from ChromeOS version 16174.34.0.
+
+2. Included changes:
+
+- CL:*8030082 mt8196: EMI: Add EMI clock pre setting and post setting
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Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> This is not limited to THC wake, for those wake sources that uses GpioInt in its ACPI _CRS will need […]
another reference link for pinctrl-intel.c:
https://codebrowser.dev/linux/linux/drivers/pinctrl/intel/pinctrl-intel.c.h…
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Change subject: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 8:
(1 comment)
This change is ready for review.
Patchset:
PS5:
> I created a partner bug for this b:376218080
Added v4 header
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Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> It seems that this is only used by [[https://review.coreboot.org/c/coreboot/+/85200]]. […]
This is not limited to THC wake, for those wake sources that uses GpioInt in its ACPI _CRS will need to use this macro. Please reference:
https://github.com/torvalds/linux/blob/master/drivers/pinctrl/intel/pinctrl…
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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
......................................................................
Patch Set 21:
(1 comment)
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85454/comment/2816c04a_60f07500?us… :
PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> > Why not try Jérémy's solution for now and use it for as many generations as it works in? "common" […]
Combining the comment from a similar discussion here:
https://review.coreboot.org/c/coreboot/+/86452/comment/84dc3ced_2fc8ae13/
I acknowledge there are 2 problems which are coming in the way of common code:
1) UPD name changes during each generation of SoCs
2) New UPD requirement for ESOL in the future.
Those problems can be addressed through one or more of the following:
1) fill_base_esol_fsp_params() that are common/base to all SoCs. We can provide the default implementation in the common code. We can communicate to Intel and ask them to not change the name for these UPDs. If the UPD names change even after that, then we can provide an override to fill_base_esol_fsp_params() in the SoC specific way.
2) Add soc_fill_additional_esol_fsp_params() to support new UPDs. The default implementation does nothing, but the SoC specific UPDs can be filled by the concerned code. Again we can do this when we have to cross that bridge.
3) Versioning scheme as suggested earlier by Julius.
Even if the suggested improvements does not stand the test of time, they will definitely reduce code and logic duplication.
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