coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/a4a5d1ad_8950f7c4?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > Combining the comment from a similar discussion here: > https://review.coreboot.org/c/coreboot/+/86452/comment/84dc3ced_2fc8ae13/ > > I acknowledge there are 2 problems which are coming in the way of common code: > 1) UPD name changes during each generation of SoCs > 2) New UPD requirement for ESOL in the future. > > Those problems can be addressed through one or more of the following: > 1) fill_base_esol_fsp_params() that are common/base to all SoCs. We can provide the default implementation in the common code. We can communicate to Intel and ask them to not change the name for these UPDs. If the UPD names change even after that, then we can provide an override to fill_base_esol_fsp_params() in the SoC specific way. > 2) Add soc_fill_additional_esol_fsp_params() to support new UPDs. The default implementation does nothing, but the SoC specific UPDs can be filled by the concerned code. Again we can do this when we have to cross that bridge. > 3) Versioning scheme as suggested earlier by Julius. > > Even if the suggested improvements does not stand the test of time, they will definitely reduce code and logic duplication There are at least two angles to this request to create common code using eSOL: 1. Julius wants to leverage the code between MTL and PTL because the number of UPDs is the same in both eSOL implementations. Also, the names look the same at this point. 2. Karthik wants to avoid using #if/#endif guards in each SoC code base that implements an override for platform_display_early_shutdown_notification. Instead, he suggests using common code like ux_inform_user_of_poweroff_operation, which takes an FSP UPD pointer and updates the required UPDs. Currently, the SoC override might exist in each SoC and circle back to the #1 angle. There are few reasons why we can't implement a common layer: In the IA common code model, we intentionally avoided making common code based on FSP-UPD because the FSP team never guaranteed to use the same UPD names across multiple SOC generations. - UPD names can change - New UPDs may be added - UPDs can be divided based on SoC IP block, like `VgaInit`, which is now part of `m_cfg->VgaInit`, can be implemented in FSP as a nested data structure like `m_cfg->PreMemDisplay->VgaInit`. this idea of implementing common code based on the UPD variable names: - The common block might need more overrides or #if/#endif guards to handle different SoC variations. - Creating a folder structure as suggested by Julius could solve the problem, but it wouldn't be any better than the existing proposal, where each SoC layer has its dedicated `platform_display_early_shutdown_notification` API implementation. - We might end up with multiple versions of the common block (e.g., `fsp_esol_2024`, `fsp_esol_2025`, `fsp_esol_2026`, etc.) as it evolves each year, which would require us to move unnecessary folders into the common block. - The volatile SoC block was never designed to be moved into IA common code. - If the guideline is to implement common code based on UPD name commonality, there are many better candidates than just eSOL. Overall, I believe that trying to common things based on UPD variable names is not a good idea, and I would strongly oppose it. As suggested by Jeremy, there are ample code blocks that exist into each SoC block which can be revisited to make it common. I would like to emphasize that need rather using common code for eSOL. -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 04:18:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Save HW protect temperature to SRAM
by Yidi Lin (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86551?usp=email ) Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ...................................................................... Patch Set 2: (2 comments) File src/soc/mediatek/mt8196/thermal_sram.c: https://review.coreboot.org/c/coreboot/+/86551/comment/7c8b6d40_e0922721?us… : PS2, Line 71: int uint32_t https://review.coreboot.org/c/coreboot/+/86551/comment/497c7f80_158f7feb?us… : PS2, Line 71: int unint32_t ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 Gerrit-Change-Number: 86551 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 01:14:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Disable HWRot's clocks
by Yidi Lin (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86553?usp=email ) Change subject: soc/mediatek/mt8196: Disable HWRot's clocks ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86553/comment/669dcb1b_eef307a1?us… : PS3, Line 9: are is https://review.coreboot.org/c/coreboot/+/86553/comment/4fc2d2d7_492b76f7?us… : PS3, Line 10: This is a Vcore sub-block item that decreases SOC power : consumption from 120mW to 90mW. This patch is a subitem of Vcore power consumption improvement. The whole work improves SoC power consumption from 120mW to 90mW in suspend. -- To view, visit https://review.coreboot.org/c/coreboot/+/86553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a Gerrit-Change-Number: 86553 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 01:10:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust thermal trip point parameters
by Yidi Lin (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu, Zhaoqing Jiu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86552?usp=email ) Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Gerrit-Change-Number: 86552 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 00:58:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Yidi Lin (Code Review) 21 Feb '25

21 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB. BUG=b:379008996 BRANCH=none TEST=booted successfully Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86538 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8189/gpio.c 1 file changed, 37 insertions(+), 5 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8189/gpio.c b/src/soc/mediatek/mt8189/gpio.c index 27179c3..dde8d14 100644 --- a/src/soc/mediatek/mt8189/gpio.c +++ b/src/soc/mediatek/mt8189/gpio.c @@ -8,6 +8,26 @@ #include <device/mmio.h> #include <gpio.h> +#define SPI_NOR_GPIO_BASE 150 + +enum { + SPI_NOR_CK = 0, + SPI_NOR_CS = 1, + SPI_NOR_IO0 = 2, + SPI_NOR_IO1 = 3, + SPI_NOR_IO2 = 4, + SPI_NOR_IO3 = 5, +}; + +static const struct gpio_drv_info bootblock_gpio_driving_info[] = { + [SPI_NOR_CK] = { 0x10, 12, 3, }, + [SPI_NOR_CS] = { 0x10, 27, 3, }, + [SPI_NOR_IO0] = { 0x10, 15, 3, }, + [SPI_NOR_IO1] = { 0x10, 18, 3, }, + [SPI_NOR_IO2] = { 0x10, 21, 3, }, + [SPI_NOR_IO3] = { 0x10, 24, 3, }, +}; + static const struct gpio_drv_info gpio_driving_info[] = { [0] = { 0x10, 15, 3, }, [1] = { 0x10, 9, 3, }, @@ -261,14 +281,26 @@ const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) { - if (raw_id >= ARRAY_SIZE(gpio_driving_info)) - return NULL; - return &gpio_driving_info[raw_id]; + if (ENV_BOOTBLOCK) { + uint32_t id = raw_id - SPI_NOR_GPIO_BASE; + + if (id >= ARRAY_SIZE(bootblock_gpio_driving_info)) + return NULL; + return &bootblock_gpio_driving_info[id]; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_info)) + return NULL; + return &gpio_driving_info[raw_id]; + } } const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) { - if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + if (ENV_BOOTBLOCK) { return NULL; - return &gpio_driving_adv_info[raw_id]; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + return NULL; + return &gpio_driving_adv_info[raw_id]; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
by Yidi Lin (Code Review) 21 Feb '25

21 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/blobs/+/86534?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 ...................................................................... soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 Update dram.elf, which includes: - Add EMI clock pre setting and post setting. BRANCH=rauru BUG=b:378592077 TEST=Build pass, Bootup pass. Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/dram.elf M soc/mediatek/mt8196/dram.elf.md5 M soc/mediatek/mt8196/dram_release_notes.txt 3 files changed, 9 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Verified; Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/soc/mediatek/mt8196/dram.elf b/soc/mediatek/mt8196/dram.elf index a39b8f9..cd3dc83 100644 --- a/soc/mediatek/mt8196/dram.elf +++ b/soc/mediatek/mt8196/dram.elf Binary files differ diff --git a/soc/mediatek/mt8196/dram.elf.md5 b/soc/mediatek/mt8196/dram.elf.md5 index c62a77b..aa78653 100644 --- a/soc/mediatek/mt8196/dram.elf.md5 +++ b/soc/mediatek/mt8196/dram.elf.md5 @@ -1 +1 @@ -eb5a6b2b584df19a461297b35ca69b1a *dram.elf +ee9a89634430162b3d10e1a16f191bc7 *dram.elf diff --git a/soc/mediatek/mt8196/dram_release_notes.txt b/soc/mediatek/mt8196/dram_release_notes.txt index 9cb9afb..ec16e64 100644 --- a/soc/mediatek/mt8196/dram_release_notes.txt +++ b/soc/mediatek/mt8196/dram_release_notes.txt @@ -12,3 +12,11 @@ - CL:*7518650 mt8196: SLC: Port SLC driver - CL:*7842174 mtk-dramk/mt8196: Sync to MediaTek's preloader version 20241121 + +# 16174.34.0 + +1. An official build from ChromeOS version 16174.34.0. + +2. Included changes: + +- CL:*8030082 mt8196: EMI: Add EMI clock pre setting and post setting -- To view, visit https://review.coreboot.org/c/blobs/+/86534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Gerrit-Change-Number: 86534 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Cliff Huang (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > This is not limited to THC wake, for those wake sources that uses GpioInt in its ACPI _CRS will need […] another reference link for pinctrl-intel.c: https://codebrowser.dev/linux/linux/drivers/pinctrl/intel/pinctrl-intel.c.h… -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 00:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table
by Bora Guvendik (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 8: (1 comment) This change is ready for review. Patchset: PS5: > I created a partner bug for this b:376218080 Added v4 header -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 00:06:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Cliff Huang (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > It seems that this is only used by [[https://review.coreboot.org/c/coreboot/+/85200]]. […] This is not limited to THC wake, for those wake sources that uses GpioInt in its ACPI _CRS will need to use this macro. Please reference: https://github.com/torvalds/linux/blob/master/drivers/pinctrl/intel/pinctrl… -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sat, 22 Feb 2025 00:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Karthik Ramasubramanian (Code Review) 21 Feb '25

21 Feb '25

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