coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: chromeos/Kconfig: BMP_LOGO only if using FSP
by Paz Zcharya (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Subrata Banik. Hello Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86563?usp=email to look at the new patch set (#2). Change subject: chromeos/Kconfig: BMP_LOGO only if using FSP ...................................................................... chromeos/Kconfig: BMP_LOGO only if using FSP Currently, CHROMEOS_FW_SPLASH_SCREEN selects BMP_LOGO and HAVE_CUSTOME_BMP_LOGO, which are both defined in src/drivers/intel/fsp2_0/Kconfig. Since they are intel-/fsp2_0- specific, change the selection to be conditional on the use of PLATFORM_USES_FSP2_0. BUG=b:398621376 TEST=Compile Google/Rex and Google/Rauru Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Signed-off-by: Paz Zcharya <pazz(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/86563/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Gerrit-Change-Number: 86563 Gerrit-PatchSet: 2 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: chromeos/Kconfig: BMP_LOGO only if using FSP
by Paz Zcharya (Code Review) 23 Feb '25

23 Feb '25

Paz Zcharya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86563?usp=email ) Change subject: chromeos/Kconfig: BMP_LOGO only if using FSP ...................................................................... chromeos/Kconfig: BMP_LOGO only if using FSP Currently, CHROMEOS_FW_SPLASH_SCREEN selects BMP_LOGO and HAVE_CUSTOME_BMP_LOGO, which are both defined in src/drivers/intel/fsp2_0/Kconfig. Since they are intel/fsp2_0 specific, change the selection to be conditional on the use of PLATFORM_USES_FSP2_0. BUG=b:398621376 TEST=Compile Google/Rex and Google/Rauru Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Signed-off-by: Paz Zcharya <pazz(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/86563/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 60f48fe..934ea9b 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -82,8 +82,8 @@ config CHROMEOS_FW_SPLASH_SCREEN bool "Display Splash Screen in firmware" default n - select BMP_LOGO - select HAVE_CUSTOM_BMP_LOGO + select BMP_LOGO if PLATFORM_USES_FSP2_0 + select HAVE_CUSTOM_BMP_LOGO if PLATFORM_USES_FSP2_0 help Select this option to display the manufacturer's logo or custom image (OEM splash screen) early in the boot process. -- To view, visit https://review.coreboot.org/c/coreboot/+/86563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Gerrit-Change-Number: 86563 Gerrit-PatchSet: 1 Gerrit-Owner: Paz Zcharya <pazz(a)google.com>

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[XS] Change in coreboot[main]: opensbi is a burden!
by Elyes Haouas (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85732?usp=email to look at the new patch set (#14). Change subject: opensbi is a burden! ...................................................................... opensbi is a burden! Update opensbi submodule to upstream master Updating from commit id 5019fd124b4c: 2022-09-01 16:53:28 +0530 - (include: sbi: Reduce includes in sbi_pmu.h) to commit id 1ad199124479: 2025-01-24 17:51:57 +0530 - (lib: sbi: fwft: Return SBI_ERR_DENIED_LOCKED when setting a locked feature) This brings in 755 new commits. Change-Id: Ic050c7b8dc2e202ee3b7fe07c749181c0845f0e7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/opensbi 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85732/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/85732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic050c7b8dc2e202ee3b7fe07c749181c0845f0e7 Gerrit-Change-Number: 85732 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h>
by Elyes Haouas (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82315?usp=email ) Change subject: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> ...................................................................... Patch Set 12: (1 comment) Patchset: PS11: > Is this change reproducible? TEST=Built purism/librem_bdw (Librem 13 v1) with BUILD_TIMELESS=1, no change in output ROM. -- To view, visit https://review.coreboot.org/c/coreboot/+/82315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Gerrit-Change-Number: 82315 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Feb 2025 15:21:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h>
by Elyes Haouas (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Elyes Haouas, Intel coreboot Reviewers. Hello Eric Lai, Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82315?usp=email to look at the new patch set (#12). Change subject: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> ...................................................................... intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> Use already defined macros in <spd.h> and <dram/ddr3.h>. TEST=Built purism/librem_bdw (Librem 13 v1) with BUILD_TIMELESS=1, no change in output ROM. Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/spd.c 1 file changed, 13 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/82315/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/82315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Gerrit-Change-Number: 82315 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage
by Paul Menzel (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Name of user not set #1005756, Patrick Rudolph. Paul Menzel has posted comments on this change by Name of user not set #1005756. ( https://review.coreboot.org/c/coreboot/+/86562?usp=email ) Change subject: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86562/comment/fb185b5d_e956cdde?us… : PS2, Line 7: src/cpu/intel/car/romstage.c I suggest: cpu/intel/car/romstage https://review.coreboot.org/c/coreboot/+/86562/comment/794148bb_b0fad66f?us… : PS2, Line 9: Refactor stack guard code in romstage. Madybe more specific: Factor out stack_guard_set() and …() for improving readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/86562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Gerrit-Change-Number: 86562 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1005756 Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Name of user not set #1005756 Gerrit-Comment-Date: Sun, 23 Feb 2025 13:26:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h>
by Angel Pons (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Elyes Haouas, Intel coreboot Reviewers. Angel Pons has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82315?usp=email ) Change subject: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: Is this change reproducible? -- To view, visit https://review.coreboot.org/c/coreboot/+/82315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Gerrit-Change-Number: 82315 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 23 Feb 2025 11:31:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Angel Pons (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Nicholas Chin. Angel Pons has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 10: (3 comments) File src/mainboard/lenovo/m900/cmos.layout: https://review.coreboot.org/c/coreboot/+/74187/comment/67b29e4d_32db5a32?us… : PS10, Line 21: 400 1 e 2 hyper_threading Doesn't have a default File src/mainboard/lenovo/m900/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74187/comment/6a34ac9a_3006f5fb?us… : PS10, Line 42: register "PrimaryDisplay" = "Display_PEG" Out of curiosity, why? https://review.coreboot.org/c/coreboot/+/74187/comment/113e4607_5438e6f8?us… : PS10, Line 122: register "gen1_dec" = "0x00fc0201" : register "gen2_dec" = "0x003c0a01" : register "gen3_dec" = "0x00040069" : register "gen4_dec" = "0x000c0081" Do we know what these decode ranges are used for? -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Feb 2025 10:00:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Felix Singer (Code Review) 23 Feb '25

23 Feb '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) The mainboard is marked IQ1X0MS, though it is also known as the MS-7988. The Small Form Factor version was used for this port, though the Mini Tower seems to use the exact same board. Other systems such as the ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre 700-25ISH appear to use the same PCB with different configurations of components. All the code in this port was originally copied from the Asrock H110M and then modified to match the actual configuration of the M900. The VBT was extracted using `intelvbttool -l -v data.vbt` while running version FWKTBFA of the vendor firmware. Working: - Boots to Linux with SeaBIOS 1.16.3 - Boots to Linux with EDK2 (MrChromebox uefipayload_202408) - Display Ports - VGA port - PCIe slots - Console over serial port - Front and rear USB 3.0 ports and internal USB2.0 headers - Front and rear audio jacks - Internal speaker - SATA ports 1-4 (5 and 6 are not populated on the M900) - Hardware monitoring via nct6683 kernel module - Gigabit Ethernet - S3 suspend/resume Unknown/untested: - M.2 E-key slot - Parallel port header - PS/2 Mouse/Keyboard via KB_MS1 header - TPM Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74187 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- A src/mainboard/lenovo/m900/Kconfig A src/mainboard/lenovo/m900/Kconfig.name A src/mainboard/lenovo/m900/Makefile.mk A src/mainboard/lenovo/m900/acpi/ec.asl A src/mainboard/lenovo/m900/acpi/superio.asl A src/mainboard/lenovo/m900/board_info.txt A src/mainboard/lenovo/m900/bootblock.c A src/mainboard/lenovo/m900/cmos.default A src/mainboard/lenovo/m900/cmos.layout A src/mainboard/lenovo/m900/data.vbt A src/mainboard/lenovo/m900/devicetree.cb A src/mainboard/lenovo/m900/dsdt.asl A src/mainboard/lenovo/m900/gma-mainboard.ads A src/mainboard/lenovo/m900/gpio.h A src/mainboard/lenovo/m900/hda_verb.c A src/mainboard/lenovo/m900/ramstage.c A src/mainboard/lenovo/m900/romstage.c 17 files changed, 731 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/lenovo/m900/Kconfig b/src/mainboard/lenovo/m900/Kconfig new file mode 100644 index 0000000..882f313 --- /dev/null +++ b/src/mainboard/lenovo/m900/Kconfig @@ -0,0 +1,36 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LENOVO_M900 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + # Actual chip is NCT6685 + select SUPERIO_NUVOTON_NCT6687D + +config DIMM_SPD_SIZE + default 512 # DDR4 + +config DISABLE_HECI1_AT_PRE_BOOT + default y + +config MAINBOARD_DIR + default "lenovo/m900" + +config MAINBOARD_PART_NUMBER + default "M900" + +endif diff --git a/src/mainboard/lenovo/m900/Kconfig.name b/src/mainboard/lenovo/m900/Kconfig.name new file mode 100644 index 0000000..9248140 --- /dev/null +++ b/src/mainboard/lenovo/m900/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_M900 + bool "ThinkCentre M900" diff --git a/src/mainboard/lenovo/m900/Makefile.mk b/src/mainboard/lenovo/m900/Makefile.mk new file mode 100644 index 0000000..ef44a4c --- /dev/null +++ b/src/mainboard/lenovo/m900/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/m900/acpi/ec.asl b/src/mainboard/lenovo/m900/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/m900/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/m900/acpi/superio.asl b/src/mainboard/lenovo/m900/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/m900/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/m900/board_info.txt b/src/mainboard/lenovo/m900/board_info.txt new file mode 100644 index 0000000..a19aea3 --- /dev/null +++ b/src/mainboard/lenovo/m900/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/lenovo/m900/bootblock.c b/src/mainboard/lenovo/m900/bootblock.c new file mode 100644 index 0000000..8afe6b3 --- /dev/null +++ b/src/mainboard/lenovo/m900/bootblock.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +/* Change to NCT6687D_SP1 to use COM2 header */ +#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP2) +#define POWER_DEV PNP_DEV(0x2e, NCT6687D_SLEEP_PWR) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* + * Replicate non-default vendor settings (mostly multi-function pin + * selection settings) in the global LDN. It seems like some bits are + * set to non-default values before coreboot configures them; possibly + * by the MCU firmware. Comments provided for notable settings. + */ + pnp_write_config(GLOBAL_DEV, 0x13, 0x0c); + /* Pins 121, 122 as TACHPWM */ + pnp_write_config(GLOBAL_DEV, 0x15, 0xf0); + /* Pin 125 as TACHPWM */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x07); + pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x08); + /* Pins 95, 98, 124 as TACHPWM */ + pnp_write_config(GLOBAL_DEV, 0x1e, 0xfc); + /* Pins 126, 127 as TACHPWM */ + pnp_write_config(GLOBAL_DEV, 0x1f, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x22, 0xbc); + pnp_write_config(GLOBAL_DEV, 0x23, 0xdf); + /* Route pins 29-36 to COM A (COM2 header) */ + pnp_write_config(GLOBAL_DEV, 0x24, 0x61); + pnp_write_config(GLOBAL_DEV, 0x25, 0xff); + /* Route pins to parallel port */ + pnp_write_config(GLOBAL_DEV, 0x27, 0xbe); + pnp_write_config(GLOBAL_DEV, 0x29, 0xfd); + /* Route pins 7-13 to COM B (Back panel COM1) */ + pnp_write_config(GLOBAL_DEV, 0x2a, 0xcf); + + /* Configure pin for PECI */ + pnp_set_logical_device(POWER_DEV); + pnp_write_config(POWER_DEV, 0xf3, 0x0c); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Back panel COM1 */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/lenovo/m900/cmos.default b/src/mainboard/lenovo/m900/cmos.default new file mode 100644 index 0000000..f3330e5 --- /dev/null +++ b/src/mainboard/lenovo/m900/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/lenovo/m900/cmos.layout b/src/mainboard/lenovo/m900/cmos.layout new file mode 100644 index 0000000..2c67e5a --- /dev/null +++ b/src/mainboard/lenovo/m900/cmos.layout @@ -0,0 +1,57 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +# Used by vboot +416 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/m900/data.vbt b/src/mainboard/lenovo/m900/data.vbt new file mode 100644 index 0000000..37bfddf --- /dev/null +++ b/src/mainboard/lenovo/m900/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb new file mode 100644 index 0000000..4f96ac1 --- /dev/null +++ b/src/mainboard/lenovo/m900/devicetree.cb @@ -0,0 +1,188 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_G" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # PL2 override 91W + register "power_limits_config" = "{ + .tdp_pl2_override = 91, + }" + + device domain 0 on + subsystemid 0x17aa 0x30bc inherit + + device ref peg0 on + smbios_slot_desc "SlotTypePciExpressGen3" "SlotLengthOther" + "PCIE16X_1" "SlotDataBusWidth16X" + end + device ref igpu on + register "PrimaryDisplay" = "Display_PEG" + end + device ref sa_thermal on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* Rear port 5 */ + [1] = USB2_PORT_MID(OC0), /* Rear port 6 */ + [2] = USB2_PORT_EMPTY, /* BMC slot not populated */ + [3] = USB2_PORT_MID(OC_SKIP), /* M.2 */ + [4] = USB2_PORT_MID(OC4), /* Front port 1 */ + [5] = USB2_PORT_MID(OC4), /* Front port 2 */ + [6] = USB2_PORT_MID(OC2), /* Rear port 3 */ + [7] = USB2_PORT_MID(OC3), /* Rear port 4 */ + [8] = USB2_PORT_MID(OC5), /* FUSB_1 Header */ + [9] = USB2_PORT_MID(OC5), /* FUSB_1 Header */ + [10] = USB2_PORT_MID(6), /* FUSB_2 Header */ + [11] = USB2_PORT_MID(6), /* FUSB_2 Header */ + [12] = USB2_PORT_MID(OC1), /* Rear port 7 */ + [13] = USB2_PORT_MID(OC1), /* Rear port 8 */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* Rear port 5 */ + [1] = USB3_PORT_DEFAULT(OC0), /* Rear port 6 */ + [2] = USB3_PORT_DEFAULT(OC2), /* Rear port 3 */ + [3] = USB3_PORT_DEFAULT(OC3), /* Rear port 4 */ + [4] = USB3_PORT_DEFAULT(OC4), /* Front port 1 */ + [5] = USB3_PORT_DEFAULT(OC4), /* Front port 2 */ + [6] = USB3_PORT_DEFAULT(OC1), /* Rear port 7 */ + [7] = USB3_PORT_DEFAULT(OC1), /* Rear port 8 */ + [8] = USB3_PORT_EMPTY, /* HSIO used for PCIe */ + [9] = USB3_PORT_EMPTY, /* HSIO used for PCIe */ + }" + end + device ref thermal on end + device ref heci1 on end + device ref sata on + register "SataSalpSupport" = "true" + register "SataPortsEnable" = "{ + [0] = true, + [1] = true, + [2] = true, + [3] = true, + }" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "true" + register "PcieRpClkReqSupport[4]" = "false" + register "PcieRpAdvancedErrorReporting[4]" = "true" + register "PcieRpLtrEnable[4]" = "true" + register "PcieRpClkSrcNumber[4]" = "1" + register "PcieRpHotPlug[4]" = "true" + + smbios_slot_desc "SlotTypePciExpressGen3" "SlotLengthOther" + "PCIE1X_1" "SlotDataBusWidth1X" + end + device ref pcie_rp7 on # M.2 E-key + register "PcieRpEnable[6]" = "true" + register "PcieRpClkReqSupport[6]" = "true" + register "PcieRpClkReqNumber[6]" = "4" + register "PcieRpAdvancedErrorReporting[6]" = "true" + register "PcieRpLtrEnable[6]" = "true" + register "PcieRpClkSrcNumber[6]" = "7" + register "PcieRpHotPlug[6]" = "true" + + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M_2" "SlotDataBusWidth1X" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "true" + register "PcieRpClkReqSupport[8]" = "false" + register "PcieRpAdvancedErrorReporting[8]" = "true" + register "PcieRpLtrEnable[8]" = "true" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpHotPlug[8]" = "true" + + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" + "PCIE4X_1" "SlotDataBusWidth4X" + end + device ref lpc_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x00040069" + register "gen4_dec" = "0x000c0081" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Actually a NCT6685D, but the 6687D seems similar enough + chip superio/nuvoton/nct6687d + device pnp 2e.1 on # Parallel port + io 0x60 = 0x278 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 - optional module + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO0-7 + device pnp 2e.8 off end # P80 UART + device pnp 2e.9 off end # GPIO8-9, GPIO1-8 AF + device pnp 2e.a on # ACPI + io 0x60 = 0xa10 + irq 0xe7 = 0x0f + irq 0xe8 = 0xe0 + irq 0xec = 0x00 + irq 0xee = 0xff + end + device pnp 2e.b on # EC + io 0x60 = 0xa20 + end + device pnp 2e.c off end # RTC + device pnp 2e.d off end # Deep Sleep + device pnp 2e.e on # TACH/PWM assignment + # Pin 122 TACHIN0, Pin 121 PWMOUT0 (CPU Fan) + irq 0xe1 = 0x80 + # Pin 98 TACHIN2, Pin 95 PWMOUT2 (AUX1 Fan) + irq 0xe2 = 0xa2 + # Pin 125 TACHIN3, Pin 124 PWMOUT3 (AUX2 Fan) + irq 0xe3 = 0xb3 + irq 0xe4 = 0x10 # Pin 126 PWMOUT1 (SYS Fan) + irq 0xe5 = 0x09 # Pin 127 TACHIN1 (SYS Fan) + end + device pnp 2e.f off end # Function register + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref hda on + register "PchHdaVcType" = "Vc1" + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/lenovo/m900/dsdt.asl b/src/mainboard/lenovo/m900/dsdt.asl new file mode 100644 index 0000000..dda17a5 --- /dev/null +++ b/src/mainboard/lenovo/m900/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/m900/gma-mainboard.ads b/src/mainboard/lenovo/m900/gma-mainboard.ads new file mode 100644 index 0000000..dd45ad4 --- /dev/null +++ b/src/mainboard/lenovo/m900/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- mainboard VGA port + DP2, -- DP++ port 1 + DP3, -- DP++ port 2 + HDMI2, -- DP++ port 1 + HDMI3, -- DP++ port 2 + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/m900/gpio.h b/src/mainboard/lenovo/m900/gpio.h new file mode 100644 index 0000000..d9146ce --- /dev/null +++ b/src/mainboard/lenovo/m900/gpio.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, DEEP), + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + PAD_CFG_GPO(GPP_A18, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_A19, 0, UP_20K, DEEP), + PAD_CFG_GPO(GPP_A20, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, PLTRST), + PAD_CFG_GPO(GPP_B1, 0, PLTRST), + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_B3, 0, PLTRST), + PAD_CFG_GPO(GPP_B4, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B6, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B9, 0, PLTRST), + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_B11, 0, PLTRST), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_GPO(GPP_B15, 0, PLTRST), + PAD_CFG_GPO(GPP_B16, 0, PLTRST), + PAD_CFG_GPO(GPP_B17, 0, PLTRST), + PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_B19, 0, PLTRST), + PAD_CFG_GPI_DUAL_ROUTE(GPP_B20, NONE, PLTRST, OFF, NONE, NMI, SMI), + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_C9, 0, PLTRST), + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + PAD_CFG_GPO(GPP_C16, 0, PLTRST), + PAD_CFG_GPO(GPP_C17, 0, PLTRST), + PAD_CFG_GPO(GPP_C18, 0, PLTRST), + PAD_CFG_GPO(GPP_C19, 0, PLTRST), + PAD_CFG_GPO(GPP_C20, 0, PLTRST), + PAD_CFG_GPO(GPP_C21, 0, PLTRST), + PAD_CFG_GPO(GPP_C22, 0, PLTRST), + PAD_CFG_GPO(GPP_C23, 0, PLTRST), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 0, PLTRST), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D4, 1, RSMRST), + PAD_CFG_GPO(GPP_D5, 0, RSMRST), + PAD_CFG_GPO(GPP_D6, 0, RSMRST), + PAD_CFG_GPO(GPP_D7, 0, RSMRST), + PAD_CFG_GPO(GPP_D8, 0, RSMRST), + PAD_CFG_GPO(GPP_D9, 0, RSMRST), + PAD_CFG_GPO(GPP_D10, 0, RSMRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D16, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_D19, 0, PLTRST), + PAD_CFG_GPO(GPP_D20, 0, PLTRST), + PAD_CFG_GPO(GPP_D21, 0, PLTRST), + PAD_CFG_GPO(GPP_D22, 0, PLTRST), + PAD_CFG_GPO(GPP_D23, 0, PLTRST), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_TERM_GPO(GPP_E0, 0, UP_20K, PLTRST), + PAD_CFG_TERM_GPO(GPP_E1, 0, UP_20K, PLTRST), + PAD_CFG_TERM_GPO(GPP_E2, 0, UP_20K, PLTRST), + PAD_CFG_GPO(GPP_E3, 0, PLTRST), + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + PAD_CFG_GPO(GPP_E5, 0, PLTRST), + PAD_CFG_GPO(GPP_E6, 0, PLTRST), + PAD_CFG_GPO(GPP_E7, 0, PLTRST), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPO(GPP_F0, 0, PLTRST), + PAD_CFG_NF(GPP_F1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_F3, 0, PLTRST), + PAD_CFG_GPO(GPP_F4, 0, PLTRST), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_F7, 0, DEEP), + PAD_CFG_GPO(GPP_F8, 0, PLTRST), + PAD_CFG_GPO(GPP_F9, 0, PLTRST), + PAD_CFG_NF(GPP_F10, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F11, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F13, NONE, PLTRST, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_F19, 0, PLTRST), + PAD_CFG_GPO(GPP_F20, 0, PLTRST), + PAD_CFG_GPO(GPP_F21, 0, PLTRST), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 0, PLTRST), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_G3, 0, PLTRST), + PAD_CFG_GPO(GPP_G4, 0, PLTRST), + PAD_CFG_GPO(GPP_G5, 0, PLTRST), + PAD_CFG_GPO(GPP_G6, 0, PLTRST), + PAD_CFG_GPO(GPP_G7, 0, PLTRST), + PAD_CFG_GPO(GPP_G8, 0, PLTRST), + PAD_CFG_GPO(GPP_G9, 0, PLTRST), + PAD_CFG_GPO(GPP_G10, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_G18, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_G19, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPO(GPP_G20, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_G22, 0, PLTRST), + PAD_CFG_GPO(GPP_G23, 0, PLTRST), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, PLTRST), + PAD_CFG_GPO(GPP_H1, 0, RSMRST), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_H3, 0, PLTRST), + PAD_CFG_GPO(GPP_H4, 0, PLTRST), + PAD_CFG_GPO(GPP_H5, 0, PLTRST), + PAD_CFG_GPO(GPP_H6, 0, PLTRST), + PAD_CFG_GPO(GPP_H7, 0, PLTRST), + PAD_CFG_GPO(GPP_H8, 0, PLTRST), + PAD_CFG_GPO(GPP_H9, 0, PLTRST), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_CFG_GPO(GPP_H13, 0, PLTRST), + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + PAD_CFG_GPO(GPP_H16, 0, PLTRST), + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + PAD_CFG_GPO(GPP_H18, 1, PLTRST), + PAD_CFG_GPO(GPP_H19, 0, PLTRST), + PAD_CFG_GPO(GPP_H20, 0, PLTRST), + PAD_CFG_GPO(GPP_H21, 0, PLTRST), + PAD_CFG_GPO(GPP_H22, 0, PLTRST), + PAD_CFG_GPO(GPP_H23, 0, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + PAD_CFG_NF(GPD0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + PAD_CFG_NF(GPD2, DN_20K, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 0, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD9, 0, PWROK), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_GPI_DUAL_ROUTE(GPP_I3, NONE, PLTRST, OFF, NONE, SMI, NMI), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_I5, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, DN_20K, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/lenovo/m900/hda_verb.c b/src/mainboard/lenovo/m900/hda_verb.c new file mode 100644 index 0000000..e400a59e --- /dev/null +++ b/src/mainboard/lenovo/m900/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek ALC662 rev3 */ + 0x17aa30bc, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa30bc), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x15, 0x99130110), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4047c62b), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x58560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/m900/ramstage.c b/src/mainboard/lenovo/m900/ramstage.c new file mode 100644 index 0000000..4ae8415 --- /dev/null +++ b/src/mainboard/lenovo/m900/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include "gpio.h" + +static void init_mainboard(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/lenovo/m900/romstage.c b/src/mainboard/lenovo/m900/romstage.c new file mode 100644 index 0000000..1a94d61 --- /dev/null +++ b/src/mainboard/lenovo/m900/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <stdint.h> +#include <string.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const u16 rcomp_resistors[3] = {121, 75, 100}; + + const u16 rcomp_targets[5] = {50, 26, 20, 20, 26}; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = {0x50, 0x51, 0x52, 0x53}, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Felix Singer (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Alexander Couzens, Angel Pons, Jan Philipp Groß, Nicholas Chin, Paul Menzel. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 23 Feb 2025 07:07:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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