coreboot-gerrit February 2025

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[S] Change in coreboot[main]: refactor: Consolidate bmp_logo_filename() logic
by Paz Zcharya (Code Review) 23 Feb '25

23 Feb '25

Paz Zcharya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86566?usp=email ) Change subject: refactor: Consolidate bmp_logo_filename() logic ...................................................................... refactor: Consolidate bmp_logo_filename() logic Function bmp_logo_filename() is intended to be the sole method for selecting which logo will be displayed. Currently, however, this logic is distributed across two locations: bmp_load_logo() and bmp_logo_filename(). Consolidate all logo selection logic into bmp_logo_filename() exclusively. Furthermore, the inclusion of <fsp/api.h> is specific to the FSP environment and compromises cross-compatibility. Therefore, add conditional compilation directives to ensure that this header is only included when appropriate. Change-Id: Ifd91af411aff6ccd6f5974a0b6c849794b9a2794 Signed-off-by: Paz Zcharya <pazz(a)google.com> --- M src/lib/bmp_logo.c M src/vendorcode/google/chromeos/splash.c 2 files changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/86566/1 diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c index 5a5adaa..26fbe5b 100644 --- a/src/lib/bmp_logo.c +++ b/src/lib/bmp_logo.c @@ -4,7 +4,6 @@ #include <bootsplash.h> #include <cbfs.h> #include <cbmem.h> -#include <fsp/api.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -20,7 +19,7 @@ void *bmp_load_logo(size_t *logo_size) { void *logo_buffer; - const char *logo_name; + const char *logo_name = bmp_logo_filename(); /* CBMEM is locked for S3 resume path. */ if (acpi_is_wakeup_s3()) @@ -34,11 +33,6 @@ if (!logo_buffer) return NULL; - if (platform_is_low_battery_shutdown_needed()) - logo_name = "low_battery.bmp"; - else - logo_name = bmp_logo_filename(); - *logo_size = cbfs_load(logo_name, logo_buffer, 1 * MiB); if (*logo_size == 0) return NULL; diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c index f63f526..6da6bba 100644 --- a/src/vendorcode/google/chromeos/splash.c +++ b/src/vendorcode/google/chromeos/splash.c @@ -3,8 +3,16 @@ #include <bootsplash.h> #include <vendorcode/google/chromeos/chromeos.h> +#if CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR) +#include <fsp/api.h> +#endif + const char *bmp_logo_filename(void) { +#if CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR) + if (platform_is_low_battery_shutdown_needed()) + return "low_battery.bmp"; +#endif if (chromeos_device_branded_plus_hard()) return "cb_plus_logo.bmp"; else if (chromeos_device_branded_plus_soft()) -- To view, visit https://review.coreboot.org/c/coreboot/+/86566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd91af411aff6ccd6f5974a0b6c849794b9a2794 Gerrit-Change-Number: 86566 Gerrit-PatchSet: 1 Gerrit-Owner: Paz Zcharya <pazz(a)google.com>

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl: Disconnect WLAN Sleep GPIO
by Matt DeVillier (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86564?usp=email ) Change subject: mb/starlabs/byte_adl: Disconnect WLAN Sleep GPIO ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b3421f1ab676599ffec6b2f46429ce937704e40 Gerrit-Change-Number: 86564 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 23 Feb 2025 21:04:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/byte_adl: Reconfigure the vGPIO's for CNVi BT
by Matt DeVillier (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86565?usp=email ) Change subject: mb/starlabs/byte_adl: Reconfigure the vGPIO's for CNVi BT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d6007e40b2edbadeb5611f6cd67df0c1e6ee8a6 Gerrit-Change-Number: 86565 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 23 Feb 2025 21:04:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl: Disconnect WLAN Sleep GPIO
by Sean Rhodes (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86564?usp=email ) Change subject: mb/starlabs/byte_adl: Disconnect WLAN Sleep GPIO ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b3421f1ab676599ffec6b2f46429ce937704e40 Gerrit-Change-Number: 86564 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Feb 2025 20:53:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/byte_adl: Reconfigure the vGPIO's for CNVi BT
by Sean Rhodes (Code Review) 23 Feb '25

23 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86565?usp=email ) Change subject: mb/starlabs/byte_adl: Reconfigure the vGPIO's for CNVi BT ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d6007e40b2edbadeb5611f6cd67df0c1e6ee8a6 Gerrit-Change-Number: 86565 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Feb 2025 20:53:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h>
by Angel Pons (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Elyes Haouas, Intel coreboot Reviewers. Angel Pons has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82315?usp=email ) Change subject: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Gerrit-Change-Number: 82315 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 23 Feb 2025 20:44:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Drop unused symbols
by Angel Pons (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Elyes Haouas, Intel coreboot Reviewers, Jon Murphy. Angel Pons has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81976?usp=email ) Change subject: soc/intel/common/block/cse: Drop unused symbols ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0639f03baf4edcf5f01d6673137dfbab1f2d4a25 Gerrit-Change-Number: 81976 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 23 Feb 2025 20:39:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type
by Matt DeVillier (Code Review) 23 Feb '25

23 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86540?usp=email ) Change subject: mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type ...................................................................... mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type Use fw_config to probe WIFI Type. BUG=b:389391653 TEST=emerge-nissa coreboot Change-Id: Iaefda61e4929d48f02ce7190e9e45d70b32b75e3 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86540 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/dirks/overridetree.cb 1 file changed, 34 insertions(+), 5 deletions(-) Approvals: Eric Lai: Looks good to me, approved Ivy Jian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb index a953b4c..8b7bc43 100644 --- a/src/mainboard/google/brya/variants/dirks/overridetree.cb +++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb @@ -1,3 +1,15 @@ +fw_config + field WIFI_SAR_ID 0 0 + option ID_0 0 + option ID_1 1 + end + field WIFI_TYPE 1 2 + option WIFI_ALL 0 + option WIFI_CNVI 1 + option WIFI_PCIE 2 + end +end + chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" @@ -184,7 +196,10 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "enable_cnvi_ddr_rfim" = "true" - device generic 0 on end + device generic 0 on + probe WIFI_TYPE WIFI_CNVI + probe WIFI_TYPE WIFI_ALL + end end end device ref i2c3 on @@ -209,6 +224,8 @@ end device ref pcie_rp11 on # Enable wlan PCIe 11 using clk 2 + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 2, .clk_req = 2, @@ -218,13 +235,19 @@ register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" use usb2_port8 as bluetooth_companion - device pci 00.0 on end + device pci 00.0 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end end chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" register "srcclk_pin" = "2" - device generic 0 on end + device generic 0 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end end end device ref emmc on end @@ -315,14 +338,20 @@ register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI_TYPE WIFI_PCIE + probe WIFI_TYPE WIFI_ALL + end end chip drivers/usb/acpi register "desc" = ""CNVI Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port10 on end + device ref usb2_port10 on + probe WIFI_TYPE WIFI_CNVI + probe WIFI_TYPE WIFI_ALL + end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1"" -- To view, visit https://review.coreboot.org/c/coreboot/+/86540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaefda61e4929d48f02ce7190e9e45d70b32b75e3 Gerrit-Change-Number: 86540 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/cbmem: Use uintN_t instead of uN int types
by Matt DeVillier (Code Review) 23 Feb '25

23 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86556?usp=email ) Change subject: util/cbmem: Use uintN_t instead of uN int types ...................................................................... util/cbmem: Use uintN_t instead of uN int types Replace all occurrences of u8, u16, u32 and u64 with their respective alternatives of uint8_t. There is no need to unnecessarily compress code by using standard types aliases. BUG=b:391874512 TEST=Compile cbmem Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a Signed-off-by: Jakub Czapiga <czapiga(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/cbmem/cbmem.c 1 file changed, 15 insertions(+), 20 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 15b6770..bdb6794 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -35,13 +35,8 @@ #include <x86intrin.h> #endif -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; - /* Return < 0 on error, 0 on success. */ -static int parse_cbtable(u64 address, size_t table_size); +static int parse_cbtable(uint64_t address, size_t table_size); struct mapping { void *virt; @@ -178,8 +173,8 @@ */ static void *aligned_memcpy(void *dest, const void *src, size_t n) { - u8 *d = dest; - const volatile u8 *s = src; /* volatile to prevent optimization */ + uint8_t *d = dest; + const volatile uint8_t *s = src; /* volatile to prevent optimization */ while ((uintptr_t)s & (sizeof(size_t) - 1)) { if (n-- == 0) @@ -353,7 +348,7 @@ } /* Return < 0 on error, 0 on success. */ -static int parse_cbtable(u64 address, size_t table_size) +static int parse_cbtable(uint64_t address, size_t table_size) { const void *buf; struct mapping header_mapping; @@ -441,7 +436,7 @@ char freqs[100]; int size; char *endp; - u64 rv; + uint64_t rv; const char* freq_file = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq"; @@ -509,7 +504,7 @@ debug("Timestamp tick frequency: %ld MHz\n", tick_freq_mhz); } -static u64 arch_convert_raw_ts_entry(u64 ts) +static uint64_t arch_convert_raw_ts_entry(uint64_t ts) { return ts / tick_freq_mhz; } @@ -518,14 +513,14 @@ * Print an integer in 'normalized' form - with commas separating every three * decimal orders. */ -static void print_norm(u64 v) +static void print_norm(uint64_t v) { if (v >= 1000) { /* print the higher order sections first */ print_norm(v / 1000); - printf(",%3.3u", (u32)(v % 1000)); + printf(",%3.3u", (uint32_t)(v % 1000)); } else { - printf("%u", (u32)(v % 1000)); + printf("%u", (uint32_t)(v % 1000)); } } @@ -1096,9 +1091,9 @@ } struct cbmem_console { - u32 size; - u32 cursor; - u8 body[]; + uint32_t size; + uint32_t cursor; + uint8_t body[]; } __attribute__ ((__packed__)); #define CBMC_CURSOR_MASK ((1 << 28) - 1) @@ -1828,7 +1823,7 @@ int i; size_t size_to_read = addr_cells * 4 + size_cells * 4; - u8 *dtbuffer = alloca(size_to_read); + uint8_t *dtbuffer = alloca(size_to_read); if (read(fd, dtbuffer, size_to_read) < 0) { perror(reg); return 1; @@ -1836,13 +1831,13 @@ close(fd); /* No variable-length byte swap function anywhere in C... how sad. */ - u64 baseaddr = 0; + uint64_t baseaddr = 0; for (i = 0; i < addr_cells * 4; i++) { baseaddr <<= 8; baseaddr |= *dtbuffer; dtbuffer++; } - u64 cb_table_size = 0; + uint64_t cb_table_size = 0; for (i = 0; i < size_cells * 4; i++) { cb_table_size <<= 8; cb_table_size |= *dtbuffer; -- To view, visit https://review.coreboot.org/c/coreboot/+/86556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a Gerrit-Change-Number: 86556 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT
by Sean Rhodes (Code Review) 23 Feb '25

23 Feb '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86387?usp=email ) Change subject: mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT ...................................................................... mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT It seems FSP will only automatically configure the vGPIO's for CNVi Bluetooth if USB 2 Port 7 is used. On this board, USB 2 Port 9 is used, so manually confgiure the vGPIO's related to CNVi for USB Bluetooth instead of UART. Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86387 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 1 file changed, 21 insertions(+), 11 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index f7a9737..8a0b804 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -449,26 +449,36 @@ /* R7: Not Connected */ PAD_NC(GPP_R7, NONE), - /* BT_EN */ + /* CNV_BTEN */ PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP), - - /* CNVi BT UART0 */ + /* CNV_BT_HOST_WAKEB */ + PAD_NC(GPP_VGPIO_4, NONE), + /* CNV_BT_IF_SELECT */ + PAD_CFG_GPO(GPP_VGPIO_5, 1, DEEP), + /* vCNV_BT_UART_TXD */ PAD_NC(GPP_VGPIO_6, NONE), + /* vCNV_BT_UART_RXD */ PAD_NC(GPP_VGPIO_7, NONE), + /* vCNV_BT_UART_CTS_B */ PAD_NC(GPP_VGPIO_8, NONE), + /* vCNV_BT_UART_RTS_B */ PAD_NC(GPP_VGPIO_9, NONE), - - /* CNVi UART0 */ + /* vUART0_TXD */ PAD_NC(GPP_VGPIO_18, NONE), + /* vUART0_RXD */ PAD_NC(GPP_VGPIO_19, NONE), + /* vUART0_CTS_B */ PAD_NC(GPP_VGPIO_20, NONE), + /* vUART0_RTS_B */ PAD_NC(GPP_VGPIO_21, NONE), - - /* BT I2S */ - PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), - PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), - PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), - PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* BT_I2S_BCLK */ + PAD_NC(GPP_VGPIO_30, NONE), + /* BT_I2S_SYNC */ + PAD_NC(GPP_VGPIO_31, NONE), + /* BT_I2S_SDO */ + PAD_NC(GPP_VGPIO_32, NONE), + /* BT_I2S_SDI */ + PAD_NC(GPP_VGPIO_33, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/86387?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c Gerrit-Change-Number: 86387 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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