coreboot-gerrit February 2025

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[M] Change in coreboot[main]: util/cbfstool: Optionally place new components as high as possible
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Chen, Gang C, Jincheng Li. Hello Chen, Gang C, Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86569?usp=email to review the following change. Change subject: util/cbfstool: Optionally place new components as high as possible ...................................................................... util/cbfstool: Optionally place new components as high as possible cbfstool by default places new components as low as possible. Add option -z to place them as high as possible. This useful to put files into cached region when only the highest portion close to 4G boundary is cached. Change-Id: Ida3131694f3e8883424351a68bba6a8da612ae09 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c M util/cbfstool/common.h 4 files changed, 45 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/86569/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3d768b0..cdcf8fa 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1948,21 +1948,24 @@ } static size_t absolute_align(const struct cbfs_image *image, size_t val, - size_t align) + size_t align, bool up) { const size_t region_offset = buffer_offset(&image->buffer); /* To perform alignment on absolute address, take the region offset */ /* of the image into account. */ - return align_up(val + region_offset, align) - region_offset; + size_t aligned = up ? align_up(val + region_offset, align) : + align_down(val + region_offset, align); + return aligned - region_offset; } int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, - size_t page_size, size_t align, size_t metadata_size) + size_t page_size, size_t align, size_t metadata_size, + bool close_to_top) { struct cbfs_file *entry; size_t need_len; - size_t addr, addr_next, addr2, addr3, offset; + size_t addr, addr_next, addr2, addr3, offset, offset2; /* Default values: allow fitting anywhere in ROM. */ if (!page_size) @@ -2007,6 +2010,7 @@ * For stage targets, the address is also used to re-link stage before * being added into CBFS. */ + offset = (uint32_t)-1; for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { @@ -2021,7 +2025,20 @@ if (addr_next - addr < need_len) continue; - offset = absolute_align(image, addr + metadata_size, align); + if (close_to_top) { + offset2 = absolute_align(image, addr_next - size, align, false); + if (is_in_same_page(offset2, size, page_size) && + is_in_range(addr, addr_next, metadata_size, offset2, size)) { + offset = offset2; + } + /* + * By now, extra page alignment is not needed. + * TODO: add page alignment based on needs. + */ + continue; + } + + offset = absolute_align(image, addr + metadata_size, align, true); if (is_in_same_page(offset, size, page_size) && is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1).\n"); @@ -2029,7 +2046,7 @@ } addr2 = align_up(addr, page_size); - offset = absolute_align(image, addr2, align); + offset = absolute_align(image, addr2, align, true); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2).\n"); return offset; @@ -2039,11 +2056,15 @@ * definitely provide the space for header. */ assert(page_size >= metadata_size); addr3 = addr2 + page_size; - offset = absolute_align(image, addr3, align); + offset = absolute_align(image, addr3, align, true); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3).\n"); return offset; } } + + if (close_to_top && (offset != (uint32_t)-1)) + return offset; + return -1; } diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 85ba023..8f00d8a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -118,7 +118,8 @@ * "align" specifies starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, - size_t page_size, size_t align, size_t metadata_size); + size_t page_size, size_t align, size_t metadata_size, + bool close_to_top); /* Callback function used by cbfs_legacy_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 9acfd26..bde61b5 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -108,6 +108,7 @@ */ uint32_t ext_win_base; uint32_t ext_win_size; + bool close_to_top; } param = { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, @@ -116,6 +117,7 @@ .headeroffset = HEADER_OFFSET_UNKNOWN, .region_name = SECTION_NAME_PRIMARY_CBFS, .u64val = -1, + .close_to_top = false, }; /* @@ -612,7 +614,7 @@ metadata_size += cbfs_file_attr_hash_size(param.hash); int32_t address = cbfs_locate_entry(&image, data_size, param.pagesize, - param.alignment, metadata_size); + param.alignment, metadata_size, param.close_to_top); if (address < 0) { ERROR("'%s'(%u + %zu) can't fit in CBFS for page-size %#x, align %#x.\n", @@ -1801,12 +1803,12 @@ } static const struct command commands[] = { - {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gh?", cbfs_add, true, true}, + {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gzh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:p:vA:gh?", cbfs_add_flat_binary, true, true}, {"add-payload", "H:r:f:n:c:b:a:C:I:p:vA:gh?", cbfs_add_payload, true, true}, - {"add-stage", "a:H:r:f:n:t:c:b:P:QS:p:yvA:gh?", cbfs_add_stage, + {"add-stage", "a:H:r:f:n:t:c:b:P:QS:p:yvA:gzh?", cbfs_add_stage, true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?j:", cbfs_add_master_header, true, true}, @@ -2304,6 +2306,9 @@ case 'U': param.unprocessed = true; break; + case 'z': + param.close_to_top = true; + break; case LONGOPT_IBB: param.ibb = true; break; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 88d5238..50e4ceb 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -30,6 +30,13 @@ return value; } +static inline uint32_t align_down(uint32_t value, uint32_t align) +{ + if (value % align) + value -= (value % align); + return value; +} + /* Buffer and file I/O */ struct buffer { char *name; -- To view, visit https://review.coreboot.org/c/coreboot/+/86569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3131694f3e8883424351a68bba6a8da612ae09 Gerrit-Change-Number: 86569 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[XS] Change in coreboot[main]: util/cbfstool: Handle unaligned component adding by do_cbfs_locate
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Jincheng Li. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86568?usp=email to review the following change. Change subject: util/cbfstool: Handle unaligned component adding by do_cbfs_locate ...................................................................... util/cbfstool: Handle unaligned component adding by do_cbfs_locate Unaligned component adding was originally handled by cbfs_add_entry. do_cbfs_locate is also able to handle unaligned component adding when alignment is not assigned, where cbfs_locate_entry will find en eligible entry assuming alignment = 1 (unaligned). Change-Id: Ifbf9017170833d7786eb95922554ddc86d2a5f8b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M util/cbfstool/cbfstool.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/86568/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 783c7d9..9acfd26 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -879,8 +879,10 @@ * do_cbfs_locate(). In this case, it needs to ensure that the location found can fit * the CBFS file in its final form (after any compression and conversion). * - * 3. If --align was passed and the offset is still undecided at this point, + * 3. If the offset is still undecided at this point, * do_cbfs_locate() is called to find an appropriately aligned location. + * if alignment is not assigned, do_cbfs_locate/cbfs_locate_entry will assume + * alignment = 1 (unaligned). * * 4. If |offset| is still 0 at the end, cbfs_add_entry() will find the first available * location that fits. @@ -968,7 +970,7 @@ } /* This needs to run after convert() to take compression into account. */ - if (!offset && param.alignment) + if (!offset) if (do_cbfs_locate(&offset, buffer_size(&buffer))) goto error; -- To view, visit https://review.coreboot.org/c/coreboot/+/86568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbf9017170833d7786eb95922554ddc86d2a5f8b Gerrit-Change-Number: 86568 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[S] Change in coreboot[main]: util/cbfstool: Add missing \n in debug messages
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86567?usp=email ) Change subject: util/cbfstool: Add missing \n in debug messages ...................................................................... util/cbfstool: Add missing \n in debug messages Find all potential missings by below script and apply manual check and fixes. grep -nE "(DEBUG|ERROR)\(\".+[^\\n]\"" util/cbfstool/ -r Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/fit.c 2 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/86567/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index e935357..3d768b0 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -636,7 +636,7 @@ if (header_offset % align) header_offset -= header_offset % align; if (header_offset < addr) { - ERROR("No space to hold cbfs_file header."); + ERROR("No space to hold cbfs_file header.\n"); return -1; } @@ -783,10 +783,10 @@ // Test for complicated cases if (content_offset > 0) { if (addr_next < content_offset) { - DEBUG("Not for specified offset yet"); + DEBUG("Not for specified offset yet.\n"); continue; } else if (addr > content_offset) { - DEBUG("Exceed specified content_offset."); + DEBUG("Exceed specified content_offset.\n"); break; } else if (addr + header_size > content_offset) { ERROR("Not enough space for header.\n"); @@ -1879,7 +1879,7 @@ } while (next != NULL); uint32_t header_size = be32toh(header->offset) + size; if (header_size > CBFS_METADATA_MAX_SIZE) { - DEBUG("exceeding allocated space for cbfs_file headers"); + DEBUG("exceeding allocated space for cbfs_file headers.\n"); return NULL; } /* attr points to the last valid attribute now. @@ -2024,14 +2024,14 @@ offset = absolute_align(image, addr + metadata_size, align); if (is_in_same_page(offset, size, page_size) && is_in_range(addr, addr_next, metadata_size, offset, size)) { - DEBUG("cbfs_locate_entry: FIT (PAGE1)."); + DEBUG("cbfs_locate_entry: FIT (PAGE1).\n"); return offset; } addr2 = align_up(addr, page_size); offset = absolute_align(image, addr2, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { - DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); + DEBUG("cbfs_locate_entry: OVERLAP (PAGE2).\n"); return offset; } @@ -2041,7 +2041,7 @@ addr3 = addr2 + page_size; offset = absolute_align(image, addr3, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { - DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); + DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3).\n"); return offset; } } diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index d4e48f1..ca60720 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -719,12 +719,12 @@ struct fit_entry *entry; if (!fit) { - ERROR("Internal error."); + ERROR("Internal error.\n"); return 1; } if (fit_free_space(fit, max_fit_entries) < 1) { - ERROR("No space left in FIT."); + ERROR("No space left in FIT.\n"); return 1; } @@ -781,12 +781,12 @@ const size_t idx) { if (!fit) { - ERROR("Internal error."); + ERROR("Internal error.\n"); return 1; } if (idx >= fit_table_entries(fit)) { - ERROR("Index out of range."); + ERROR("Index out of range.\n"); return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/86567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8 Gerrit-Change-Number: 86567 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
by Subrata Banik (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, hualin wei. Subrata Banik has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86554?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/86554/comment/90425d8f_da5e67eb?us… : PS2, Line 456: DECLARE_WEAK_CROS_GPIOS why ? the definition of `cros_gpios` is exactly same between this file and newly introduced https://review.coreboot.org/c/coreboot/+/86554/2/src/mainboard/google/brya/… -- To view, visit https://review.coreboot.org/c/coreboot/+/86554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255 Gerrit-Change-Number: 86554 Gerrit-PatchSet: 2 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 02:15:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: chromeos/Kconfig: BMP_LOGO only if using FSP
by Paz Zcharya (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Subrata Banik. Paz Zcharya has posted comments on this change by Paz Zcharya. ( https://review.coreboot.org/c/coreboot/+/86563?usp=email ) Change subject: chromeos/Kconfig: BMP_LOGO only if using FSP ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86563/comment/a75ffa39_e1845776?us… : PS2, Line 11: intel- > intel remove the `-`? File src/vendorcode/google/chromeos/Kconfig: https://review.coreboot.org/c/coreboot/+/86563/comment/56217051_9bc525fb?us… : PS2, Line 84: default n > how about adding a `depends on PLATFORM_USES_FSP2_0` But if I make that change, wouldn't it prevent the code from functioning correctly on non-FSP systems? -- To view, visit https://review.coreboot.org/c/coreboot/+/86563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Gerrit-Change-Number: 86563 Gerrit-PatchSet: 2 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 02:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Name of user not set #1005756, Patrick Rudolph. Shuo Liu has posted comments on this change by Name of user not set #1005756. ( https://review.coreboot.org/c/coreboot/+/86562?usp=email ) Change subject: src/cpu/intel/car/romstage.c: Refactor stack guard code in romstage ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Gerrit-Change-Number: 86562 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1005756 Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Name of user not set #1005756 Gerrit-Comment-Date: Mon, 24 Feb 2025 02:14:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Drop unused symbols
by Subrata Banik (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Elyes Haouas, Intel coreboot Reviewers, Jon Murphy. Subrata Banik has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81976?usp=email ) Change subject: soc/intel/common/block/cse: Drop unused symbols ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0639f03baf4edcf5f01d6673137dfbab1f2d4a25 Gerrit-Change-Number: 81976 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 24 Feb 2025 02:10:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: chromeos/Kconfig: BMP_LOGO only if using FSP
by Subrata Banik (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Paz Zcharya. Subrata Banik has posted comments on this change by Paz Zcharya. ( https://review.coreboot.org/c/coreboot/+/86563?usp=email ) Change subject: chromeos/Kconfig: BMP_LOGO only if using FSP ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86563/comment/2c19cfbb_100692ff?us… : PS2, Line 11: intel- intel File src/vendorcode/google/chromeos/Kconfig: https://review.coreboot.org/c/coreboot/+/86563/comment/f6298a91_80c1600d?us… : PS2, Line 84: default n how about adding a `depends on PLATFORM_USES_FSP2_0` -- To view, visit https://review.coreboot.org/c/coreboot/+/86563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Gerrit-Change-Number: 86563 Gerrit-PatchSet: 2 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 02:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts
by Brian Hsu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Brian Hsu has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/86535?usp=email ) Change subject: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Dear all, If no concern, please kindly help to submit the CL. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/86535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Gerrit-Change-Number: 86535 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 02:04:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
by hualin wei (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Qinghong Zeng. hualin wei has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86554?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP ...................................................................... Patch Set 2: (1 comment) This change is ready for review. File src/mainboard/google/brya/variants/pujjoniru/gpio.c: https://review.coreboot.org/c/coreboot/+/86554/comment/d3b1db08_85636753?us… : PS1, Line 212: DECLARE_CROS_GPIOS(cros_gpios); > `adding a line without newline at end of file` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/86554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255 Gerrit-Change-Number: 86554 Gerrit-PatchSet: 2 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 00:56:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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