coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable to...
by Tongtong Pan (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Matt DeVillier, Pranava Y N, Subrata Banik, Weimin Wu. Tongtong Pan has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/86542?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable touchpad ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/felino/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86542/comment/8142e2ef_5ed8f0d8?us… : PS1, Line 237: register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)" > needs tabs vs spaces here and 3 lines below Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135 Gerrit-Change-Number: 86542 Gerrit-PatchSet: 2 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 06:13:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[XS] Change in coreboot[main]: soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn
by Subrata Banik (Code Review) 24 Feb '25

24 Feb '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86578?usp=email ) Change subject: soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn ...................................................................... soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn In the low battery poweroff scenario, the platform should halt after issuing the poweroff command. This ensures that no further code execution occurs, preventing potential issues. Additionally, the do_low_battery_poweroff() function is marked with __noreturn to indicate that it does not return. This is appropriate because the platform will either power off or halt. TEST=Able to compile google/fatcat. Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/reset.c M src/soc/intel/common/reset.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/86578/1 diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 3fefa57..307be57 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -32,4 +32,5 @@ } poweroff(); + halt(); } diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index 8331853..71fe05d 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -30,6 +30,6 @@ * * Call this function to power off the platform if the battery level is critically low. */ -void do_low_battery_poweroff(void); +__noreturn void do_low_battery_poweroff(void); #endif /* _INTEL_COMMON_RESET_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c Gerrit-Change-Number: 86578 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable to...
by Tongtong Pan (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tongtong Pan, Weimin Wu. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86542?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Weimin Wu, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable touchpad ...................................................................... mb/google/fatcat/var/felino: Modify the overridetree.cb for enable touchpad Modify the overridetree.cb configuration and gpio.c to enable touchpad. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/felino/gpio.c M src/mainboard/google/fatcat/variants/felino/overridetree.cb 2 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/86542/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135 Gerrit-Change-Number: 86542 Gerrit-PatchSet: 2 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Yidi Lin (Code Review) 24 Feb '25

24 Feb '25

Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86538/comment/62f6b520_8aa4c888?us… : PS4, Line 9: In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB. > I guess the issue might be caused by me directly modifying in the Gerrit editor... […] Don't use online editor again. -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 06:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Vince Liu <vince-wl.liu(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

1 0

[S] Change in coreboot[main]: soc/intel/common/block/cse: Drop unused symbols
by Elyes Haouas (Code Review) 23 Feb '25

23 Feb '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81976?usp=email ) Change subject: soc/intel/common/block/cse: Drop unused symbols ...................................................................... soc/intel/common/block/cse: Drop unused symbols SOC_INTEL_CSE_RW_A_FMAP_NAME, SOC_INTEL_CSE_RW_B_FMAP_NAME and SOC_INTEL_CSE_RW_HASH_CBFS_NAME are not used. Change-Id: I0639f03baf4edcf5f01d6673137dfbab1f2d4a25 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81976 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 0 insertions(+), 18 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 657494a..bfef3d5 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -195,30 +195,12 @@ help Name of CSE region in FMAP -config SOC_INTEL_CSE_RW_A_FMAP_NAME - string "Location of CSE RW A in FMAP" if SOC_INTEL_CSE_RW_UPDATE - default "ME_RW_A" - help - Name of CSE RW A region in FMAP - -config SOC_INTEL_CSE_RW_B_FMAP_NAME - string "Location of CSE RW B in FMAP" if SOC_INTEL_CSE_RW_UPDATE - default "ME_RW_B" - help - Name of CSE RW B region in FMAP - config SOC_INTEL_CSE_RW_CBFS_NAME string "CBFS entry name for CSE RW blob" if SOC_INTEL_CSE_RW_UPDATE default "me_rw" help CBFS entry name for Intel CSE CBFS RW blob -config SOC_INTEL_CSE_RW_HASH_CBFS_NAME - string "CBFS name for CSE RW hash file" if SOC_INTEL_CSE_RW_UPDATE - default "me_rw.hash" - help - CBFS name for Intel CSE CBFS RW hash file - config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME string "CBFS name for CSE RW version file" if SOC_INTEL_CSE_RW_UPDATE default "me_rw.version" -- To view, visit https://review.coreboot.org/c/coreboot/+/81976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0639f03baf4edcf5f01d6673137dfbab1f2d4a25 Gerrit-Change-Number: 81976 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Vince Liu (Code Review) 23 Feb '25

23 Feb '25

Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86538/comment/b42c1d1a_5d97381a?us… : PS4, Line 9: In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB. > Line too long... I guess the issue might be caused by me directly modifying in the Gerrit editor... How should I fix this problem? -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 05:10:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
by Subrata Banik (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, hualin wei. Subrata Banik has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86554?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/86554/comment/eaf5d3d9_d204eedf?us… : PS2, Line 456: DECLARE_WEAK_CROS_GPIOS > We want to modify the gpio of GPIO_PCH_WP to GPP_E17 in the pujjoniru project. This is a modification to Plan B to solve the GPIO write protection problem. We try to directly add macro definition modifications > ``` > #undef GPIO_PCH_WP > > /* WP signal to PCH */ > #define GPIO_PCH_WP GPP_E17 > ``` > However, we found that `cros_gpios` under `variants/baseboard/nissa/gpio.c` will call `GPIO_PCH_WP` under `/variants/baseboard/nissa/include/baseboard/gpio.h`, causing our modifications to not take effect. > Therefore, we add `cros_gpios` in `variants/pujjoniru/gpio.c` to cover `cros_gpios` under `baseboard/nissa/gpio.c` > > This is our plan A > https://review.coreboot.org/c/coreboot/+/86510 then please mention the same in commit msg -- To view, visit https://review.coreboot.org/c/coreboot/+/86554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255 Gerrit-Change-Number: 86554 Gerrit-PatchSet: 2 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 04:58:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: hualin wei <weihualin(a)huaqin.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
by hualin wei (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik. hualin wei has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86554?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/86554/comment/90723179_7634439e?us… : PS2, Line 456: DECLARE_WEAK_CROS_GPIOS > why ? […] We want to modify the gpio of GPIO_PCH_WP to GPP_E17 in the pujjoniru project. This is a modification to Plan B to solve the GPIO write protection problem. We try to directly add macro definition modifications ``` #undef GPIO_PCH_WP /* WP signal to PCH */ #define GPIO_PCH_WP GPP_E17 ``` However, we found that `cros_gpios` under `variants/baseboard/nissa/gpio.c` will call `GPIO_PCH_WP` under `/variants/baseboard/nissa/include/baseboard/gpio.h`, causing our modifications to not take effect. Therefore, we add `cros_gpios` in `variants/pujjoniru/gpio.c` to cover `cros_gpios` under `baseboard/nissa/gpio.c` This is our plan A https://review.coreboot.org/c/coreboot/+/86510 -- To view, visit https://review.coreboot.org/c/coreboot/+/86554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255 Gerrit-Change-Number: 86554 Gerrit-PatchSet: 2 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 04:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Yu-Ping Wu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Vince Liu. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86538/comment/496d03e5_148c0454?us… : PS4, Line 9: In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB. Line too long... -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 04:25:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Disable HWRot's clocks
by Yu-Ping Wu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86553?usp=email ) Change subject: soc/mediatek/mt8196: Disable HWRot's clocks ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86553/comment/083755b1_99266e60?us… : PS3, Line 9: ( space before `(` -- To view, visit https://review.coreboot.org/c/coreboot/+/86553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a Gerrit-Change-Number: 86553 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 04:15:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025