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Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
......................................................................
soc/amd/common/block/lpc: Limit ROM2 to 16MiB
Don't map more than 16MiB when the SPI ROM size is bigger than 16MiB.
Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/amd/common/block/lpc/lpc_util.c
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/86582/1
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 309825a..6e4ddcb 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -277,8 +277,11 @@
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
- pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
+ if (CONFIG_COREBOOT_ROMSIZE_KB <= 16384)
+ pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+ else
+ pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0xff00);
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86581?usp=email )
Change subject: soc/amd/glinda: Enable x86_64 support
......................................................................
soc/amd/glinda: Enable x86_64 support
The code compiles and works fine in x86_64. Thus allow the user
to use x86_64.
TEST: Booted on amd/birman+ to OS using EDK2 as payload.
Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/amd/glinda/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/86581/1
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 39fb785..70bdb69 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -90,6 +90,7 @@
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
+ select HAVE_X86_64_SUPPORT
help
AMD Glinda support
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Change subject: cpu/x86/64bit: Allow to map more of the address space
......................................................................
cpu/x86/64bit: Allow to map more of the address space
On AMD platforms the SPI flash can be accessed using the ROM3
mapping in upper MMIO space. To reach the MMIO window the default
page tables must be extended to cover the address by default.
Add support for a SoC specific default address space being used on
x86_64, where the default of 4GiB/512GiB remains.
The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.
Used in the following patch to use ROM3 mapping on AMD platforms.
TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+
Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/x86/64bit/pt.S
M src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/Kconfig
3 files changed, 19 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86580/1
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 4b2f3c8..55d3ed0 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -20,16 +20,18 @@
.global PM4LE
.align 4096
PM4LE:
-.quad _GEN_DIR(PDPT)
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PM4LE) >> 3))
+.endr
.align 4096
PDT: /* identity map 2MiB pages */
-.rept 2048
+.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB
.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3))
.endr
.align 4096
PDPT: /* Point to PDT */
-.rept 4
+.rept CONFIG_CPU_PT_ROM_MAP_GB
.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3))
.endr
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 3502964..3a0e4b5 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -20,10 +20,12 @@
.global PM4LE
.align 4096
PM4LE:
-.quad _GEN_DIR(PDPT)
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PM4LE) >> 3))
+.endr
.align 4096
-PDPT: /* identity map 1GiB pages * 512 */
-.rept 512
+PDPT: /* identity map 1GiB pages * CONFIG_CPU_PT_ROM_MAP_GB */
+.rept CONFIG_CPU_PT_ROM_MAP_GB
.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3))
.endr
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 828c0f9..ae94f62 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -159,6 +159,15 @@
Select this option from boards/SoCs that do not support the Page1GB
CPUID feature (CPUID.80000001H:EDX.bit26).
+config CPU_PT_ROM_MAP_GB
+ int
+ default 4 if NEED_SMALL_2MB_PAGE_TABLES
+ default 512 if !NEED_SMALL_2MB_PAGE_TABLES
+ help
+ GiB of the lower address space to identity map when using x86_64
+ page tables in ROM. Higher values require more space in SPI flash.
+ SoC can overwrite the value if necessary.
+
config SMM_ASEG
bool
default n
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Change subject: mb/google/trulo: Lock GPIO pad configuration for GPP_F17
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
......................................................................
Patch Set 4:
This change is ready for review.
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Change subject: mb/google/trulo: Update GPIO wake pins
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/brya/variants/trulo/gpio.c:
https://review.coreboot.org/c/coreboot/+/86555/comment/85c7a363_149704ef?us… :
PS2, Line 61: PAD_CFG_GPI_APIC
> this is now getting register as IOAPIC and not like shared interrupt in existing implementation […]
Acknowledged
Previously: IRQ9 + GPE0_DW1_03
Now: IRQ27
https://review.coreboot.org/c/coreboot/+/86555/comment/9a4edd3b_e533a047?us… :
PS2, Line 245: PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
> this should move into a separate CL as you are locking down the EC wake PIN
Acknowledged
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Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Ready for review.
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