coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/amd/glinda: Move AMDFWBODY to upper 16MiB
by Patrick Rudolph (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86585?usp=email ) Change subject: soc/amd/glinda: Move AMDFWBODY to upper 16MiB ...................................................................... soc/amd/glinda: Move AMDFWBODY to upper 16MiB Move the AMDFWBODY into the upper part of the SPI flash. Since this region is not accessed by the host there's no need to have it in the lower 16MiB that is accessible by the ROM2 mapping. While on it fix the SPI flash size being set in Kconfig. Change-Id: Ifdc8618a87588469eb8801cb73eb25cdca486adf Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/board_glinda.fmd M src/mainboard/amd/birman/chromeos_glinda.fmd M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/board_glinda.fmd M src/mainboard/amd/birman_plus/chromeos_glinda.fmd 6 files changed, 19 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/86585/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 9fafae1..a57908e 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -2,7 +2,6 @@ config BOARD_AMD_BIRMAN_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE @@ -16,14 +15,17 @@ select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE config BOARD_AMD_BIRMAN_PHOENIX_FSP + select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_PHOENIX_FSP config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL + select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_PHOENIX_OPENSIL config BOARD_AMD_BIRMAN_GLINDA + select BOARD_ROMSIZE_KB_32768 select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_GLINDA diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd index 3aff7c1..85b52cd 100644 --- a/src/mainboard/amd/birman/board_glinda.fmd +++ b/src/mainboard/amd/birman/board_glinda.fmd @@ -1,10 +1,12 @@ -FLASH@0xFF000000 16M { +FLASH@0xFF000000 32M { BIOS { EC_SIG 4K FMAP 4K COREBOOT(CBFS) - AMDFWBODY 6M EC_BODY@15872K 256K RW_MRC_CACHE 120K } + BIOS_TOP @16M { + AMDFWBODY + } } diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd index 7adfabc..f4acf73 100644 --- a/src/mainboard/amd/birman/chromeos_glinda.fmd +++ b/src/mainboard/amd/birman/chromeos_glinda.fmd @@ -1,4 +1,4 @@ -FLASH@0xFF000000 16M { +FLASH@0xFF000000 32M { SI_BIOS { WP_RO 8M { EC_SIG 4K @@ -9,7 +9,6 @@ COREBOOT(CBFS) GBB 448K } - AMDFWBODY 6M } RW_SECTION_A 3M { VBLOCK_A 8K @@ -33,4 +32,7 @@ EC_BODY@15872K 256K RW_MRC_CACHE(PRESERVE) 120K } + BIOS_TOP @16M { + AMDFWBODY + } } diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 91e39bf..486416f 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -2,7 +2,7 @@ config BOARD_AMD_BIRMANPLUS_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 # Birman+ actually has a 64MiB ROM + select BOARD_ROMSIZE_KB_65536 # Birman+ actually has a 64MiB ROM select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd index eb26a2a..489d2f3 100644 --- a/src/mainboard/amd/birman_plus/board_glinda.fmd +++ b/src/mainboard/amd/birman_plus/board_glinda.fmd @@ -3,9 +3,11 @@ EC_SIG 4K FMAP 4K COREBOOT(CBFS) - AMDFWBODY 6M SMMSTORE(PRESERVE) 256K EC_BODY@15872K 256K RW_MRC_CACHE 120K } + BIOS_TOP @16M { + AMDFWBODY + } } diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd index 7adfabc..b9bfb3d 100644 --- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd +++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd @@ -1,4 +1,4 @@ -FLASH@0xFF000000 16M { +FLASH@0xFF000000 64M { SI_BIOS { WP_RO 8M { EC_SIG 4K @@ -9,7 +9,6 @@ COREBOOT(CBFS) GBB 448K } - AMDFWBODY 6M } RW_SECTION_A 3M { VBLOCK_A 8K @@ -33,4 +32,7 @@ EC_BODY@15872K 256K RW_MRC_CACHE(PRESERVE) 120K } + BIOS_TOP @16M { + AMDFWBODY + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/86585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifdc8618a87588469eb8801cb73eb25cdca486adf Gerrit-Change-Number: 86585 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible
by Patrick Rudolph (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86584?usp=email ) Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ...................................................................... soc/amd/common/block/lpc: Use ROM3 window if possible On x86_64 use the ROM3 window to access the SPI flash. Use the same mechanism as on Intel, where the lower 16Mbyte are mapped using ROM2 window and the upper pages are mapped using the ROM3 window. By default the ROM3 window resides in high MMIO and thus needs 1024GiB of the address space to be identity mapped in the page tables. This allows legacy 32-bit code to work on mappings in the lower 16MiB of the flash chip. TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64 on amd/birman+. Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/Makefile.mk A src/soc/amd/common/block/lpc/mmap_boot_rom3.c M src/soc/amd/glinda/Kconfig 4 files changed, 186 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86584/1 diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index 9f41f22..2e10679 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -65,3 +65,20 @@ SMU will lock up at times if the port80h enable bit is cleared. Select this option to retain the port80 enable bit while clearing other enable bits in the ESPI Decode register. + + +config SOC_AMD_COMMON_BLOCK_LPC_USE_ROM3 + bool + default y if !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA && ROM_SIZE > 0x01000000 + depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE + depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + depends on USE_X86_64_SUPPORT + # Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller + # driver provides a custom boot media device when multiple decode + # windows are used for the BIOS region. + select X86_CUSTOM_BOOTMEDIA + help + AMD specific SPI flash access. The lower 16MiB of the SPI flash are + memory mapped on the ROM2 window and the upper SPI flash is mapped using + the ROM3 window in high MMIO. The ROM3 window maps up to 64MiB of the + SPI flash. diff --git a/src/soc/amd/common/block/lpc/Makefile.mk b/src/soc/amd/common/block/lpc/Makefile.mk index 11de514..60b4059 100644 --- a/src/soc/amd/common/block/lpc/Makefile.mk +++ b/src/soc/amd/common/block/lpc/Makefile.mk @@ -14,3 +14,8 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA all-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_USE_ROM3),y) +all_x86-y += mmap_boot_rom3.c +smm-y += mmap_boot_rom3.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_USE_ROM3 diff --git a/src/soc/amd/common/block/lpc/mmap_boot_rom3.c b/src/soc/amd/common/block/lpc/mmap_boot_rom3.c new file mode 100644 index 0000000..cecef1d --- /dev/null +++ b/src/soc/amd/common/block/lpc/mmap_boot_rom3.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot_device.h> +#include <spi_flash.h> +#include <stdint.h> +#include <amdblocks/lpc.h> + +enum window_type { + /* Fixed decode window of max 16MiB size just below 4G boundary */ + ROM2_DECODE_WINDOW, + /* Additional decode window for mapping BIOS region greater than 16MiB */ + ROM3_DECODE_WINDOW, + TOTAL_DECODE_WINDOWS, +}; + +static struct xlate_region_device real_dev; +static struct mem_region_device shadow_devs[TOTAL_DECODE_WINDOWS]; +static struct xlate_window real_dev_windows[TOTAL_DECODE_WINDOWS]; + +static void initialize_window(const size_t win_idx, const enum window_type type, + uintptr_t host_base, uintptr_t flash_base, size_t size) +{ + mem_region_device_ro_init(&shadow_devs[win_idx], (void *)host_base, size); + xlate_window_init(&real_dev_windows[win_idx], &shadow_devs[win_idx].rdev, + flash_base, size); + printk(BIOS_INFO, "ROM%d Decode Window: ", + (type == ROM2_DECODE_WINDOW) ? 2: 3); + printk(BIOS_INFO, "SPI flash base=0x%lx, Host base=0x%lx, Size=0x%zx\n", + flash_base, host_base, size); +} + +/* + * + * +--------------+ + * | | + * | | + * | | + * CONFIG_ROM_SIZE +------------+--------------------------+--------------------------------+- rom3_end + * | | ^ | | + * | | | | ROM3 | + * | | | | | + * | | | | | + * | | + | | + * | | rom3_size | | + * | | + | | + * | SPI ROM | | | | + * | | +----+-----------------+--------------+ + * | | | | | | + * | | | | | | + * | | | V | | + * | | | +---0xfd00000000--+--------------+- rom3_start + * | | | | | + * | | | | | + * | | | | Other MMIO | + * | | | | | + * +------------+ --------------------+---------0x100000000--+--------------+- rom2_end + * | | ^ | | + * | | | | | + * | | rom2_size | ROM2 | + * | | | | | + * | | V | | + * 0 +------------+ ------------------------------0xFF0000000--+--------------+- rom2_start + * | | + * SPI flash | | + * address | | + * space | | + * +--------------+ + * + * Host address + * space + */ +static void bios_mmap_init(void) +{ + static bool init_done; + size_t win_count = 0; + size_t map_win_size = 0; + + if (init_done) + return; + + /* + * By default, fixed decode window (maximum size 16MiB) is mapped just + * below the 4G boundary. This window maps the bottom part of the BIOS + * region in the SPI flash address space to the host address space. + */ + size_t rom2_size = 0; + const uintptr_t rom2_start = lpc_get_rom2_region(&rom2_size); + if (rom2_start && rom2_size) { + initialize_window(win_count, ROM2_DECODE_WINDOW, rom2_start, 0, rom2_size); + win_count++; + map_win_size += rom2_size; + } + + /* + * Remaining portion of the BIOS region up to a maximum of 64MiB is + * mapped at the bottom of the ROM3 if the BIOS region is greater than 16MiB. + * The ROM3 window is only used when it's inside the identity mapped + * page tables used by x86_64. + * + * If the BIOS region is not greater than 16MiB, then the ROM3 window is not + * enabled. + */ + size_t rom3_size; + const uint64_t rom3_start = lpc_get_rom3_region(&rom3_size); + const uint64_t rom3_end = rom3_start + rom3_size; + + if (CONFIG_ROM_SIZE > 16 * MiB) { + assert (rom3_start); + assert (rom3_size > 16 * MiB); + assert (CONFIG_CPU_PT_ROM_MAP_GB >= DIV_ROUND_UP(rom3_end, GiB)); + } + + if (CONFIG_ROM_SIZE > 16 * MiB && + rom3_start > 0 && + rom3_size > 16 * MiB && + CONFIG_CPU_PT_ROM_MAP_GB >= DIV_ROUND_UP(rom3_end, GiB)) { + + const size_t ext_win_size = MIN(rom3_size, CONFIG_ROM_SIZE - rom2_size); + + initialize_window(win_count, ROM3_DECODE_WINDOW, + rom3_start + rom2_size, rom2_size, ext_win_size); + win_count++; + map_win_size += ext_win_size; + } + + assert (map_win_size == CONFIG_ROM_SIZE); + xlate_region_device_ro_init(&real_dev, win_count, real_dev_windows, map_win_size); + + init_done = true; +} + +const struct region_device *boot_device_ro(void) +{ + bios_mmap_init(); + + return &real_dev.rdev; +} + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + int i; + uint32_t count = 0; + + bios_mmap_init(); + + for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) { + if (region_sz(&real_dev_windows[i].sub_region) == 0) + continue; + + count++; + table->flash_base = region_offset(&real_dev_windows[i].sub_region); + /* FIXME: Allow SPI mmap in 64-bit address space */ + if ((uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev) < 4ULL * GiB) + table->host_base = (uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev); + table->size = region_sz(&real_dev_windows[i].sub_region); + + table++; + } + + return count; +} diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 70bdb69..1f1afec 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -100,6 +100,9 @@ string default "soc/amd/glinda/chipset.cb" +config CPU_PT_ROM_MAP_GB + default 1024 + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/86584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Gerrit-Change-Number: 86584 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
by Patrick Rudolph (Code Review) 24 Feb '25

24 Feb '25

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[XS] Change in coreboot[main]: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
by Patrick Rudolph (Code Review) 24 Feb '25

24 Feb '25

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[XS] Change in coreboot[main]: soc/amd/glinda: Enable x86_64 support
by Patrick Rudolph (Code Review) 24 Feb '25

24 Feb '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86581?usp=email ) Change subject: soc/amd/glinda: Enable x86_64 support ...................................................................... soc/amd/glinda: Enable x86_64 support The code compiles and works fine in x86_64. Thus allow the user to use x86_64. TEST: Booted on amd/birman+ to OS using EDK2 as payload. Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/glinda/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/86581/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 39fb785..70bdb69 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -90,6 +90,7 @@ select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI + select HAVE_X86_64_SUPPORT help AMD Glinda support -- To view, visit https://review.coreboot.org/c/coreboot/+/86581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6 Gerrit-Change-Number: 86581 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: cpu/x86/64bit: Allow to map more of the address space
by Patrick Rudolph (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Jérémy Compostella. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86580?usp=email ) Change subject: cpu/x86/64bit: Allow to map more of the address space ...................................................................... cpu/x86/64bit: Allow to map more of the address space On AMD platforms the SPI flash can be accessed using the ROM3 mapping in upper MMIO space. To reach the MMIO window the default page tables must be extended to cover the address by default. Add support for a SoC specific default address space being used on x86_64, where the default of 4GiB/512GiB remains. The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option. Used in the following patch to use ROM3 mapping on AMD platforms. TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/Kconfig 3 files changed, 19 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86580/1 diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 4b2f3c8..55d3ed0 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -20,16 +20,18 @@ .global PM4LE .align 4096 PM4LE: -.quad _GEN_DIR(PDPT) +.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 +.quad _GEN_DIR(PDPT + 4096 * ((. - PM4LE) >> 3)) +.endr .align 4096 PDT: /* identity map 2MiB pages */ -.rept 2048 +.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB .quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) .endr .align 4096 PDPT: /* Point to PDT */ -.rept 4 +.rept CONFIG_CPU_PT_ROM_MAP_GB .quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) .endr diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 3502964..3a0e4b5 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -20,10 +20,12 @@ .global PM4LE .align 4096 PM4LE: -.quad _GEN_DIR(PDPT) +.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 +.quad _GEN_DIR(PDPT + 4096 * ((. - PM4LE) >> 3)) +.endr .align 4096 -PDPT: /* identity map 1GiB pages * 512 */ -.rept 512 +PDPT: /* identity map 1GiB pages * CONFIG_CPU_PT_ROM_MAP_GB */ +.rept CONFIG_CPU_PT_ROM_MAP_GB .quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) .endr diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 828c0f9..ae94f62 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -159,6 +159,15 @@ Select this option from boards/SoCs that do not support the Page1GB CPUID feature (CPUID.80000001H:EDX.bit26). +config CPU_PT_ROM_MAP_GB + int + default 4 if NEED_SMALL_2MB_PAGE_TABLES + default 512 if !NEED_SMALL_2MB_PAGE_TABLES + help + GiB of the lower address space to identity map when using x86_64 + page tables in ROM. Higher values require more space in SPI flash. + SoC can overwrite the value if necessary. + config SMM_ASEG bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/86580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Gerrit-Change-Number: 86580 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/trulo: Lock GPIO pad configuration for GPP_F17
by Subrata Banik (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86579?usp=email ) Change subject: mb/google/trulo: Lock GPIO pad configuration for GPP_F17 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9211ac70539d251746332448691d22b454bc6a2b Gerrit-Change-Number: 86579 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 09:05:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
by hualin wei (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik. hualin wei has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86510?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86510?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee76fa8b357aa472699f17789b2c718028f812a3 Gerrit-Change-Number: 86510 Gerrit-PatchSet: 4 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 08:46:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Kapil Porwal (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86555?usp=email ) Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/variants/trulo/gpio.c: https://review.coreboot.org/c/coreboot/+/86555/comment/85c7a363_149704ef?us… : PS2, Line 61: PAD_CFG_GPI_APIC > this is now getting register as IOAPIC and not like shared interrupt in existing implementation […] Acknowledged Previously: IRQ9 + GPE0_DW1_03 Now: IRQ27 https://review.coreboot.org/c/coreboot/+/86555/comment/9a4edd3b_e533a047?us… : PS2, Line 245: PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), > this should move into a separate CL as you are locking down the EC wake PIN Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 08:44:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
by SH Kim (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. SH Kim has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 8 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 08:43:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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