coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in coreboot[main]: treewide: Rename PM4LE -> PML4E
by Maximilian Brune (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Hello Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Jérémy Compostella, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86587?usp=email to look at the new patch set (#2). Change subject: treewide: Rename PM4LE -> PML4E ...................................................................... treewide: Rename PM4LE -> PML4E The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry. It is annoying when searching for the wrong abbreviation in the spec so fix it everywhere it occurs. source: Intel 64 spec April 2022 and AMD64 spec April 2024. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I730235beea69b3720f080bbade083c2eeed26587 --- M payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/pt.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/smm/smm_module_loader.c M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 12 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/86587/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Gerrit-Change-Number: 86587 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Disable HWRot's clocks
by Yidi Lin (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86553?usp=email ) Change subject: soc/mediatek/mt8196: Disable HWRot's clocks ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a Gerrit-Change-Number: 86553 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 16:26:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: treewide: Rename PM4LE -> PML4E
by Maximilian Brune (Code Review) 24 Feb '25

24 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86587?usp=email ) Change subject: treewide: Rename PM4LE -> PML4E ...................................................................... treewide: Rename PM4LE -> PML4E The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry. It is annoying when searching for the wrong abbrevation in the spec so fix it everywhere it occurs. source: Intel 64 spec April 2022 and AMD64 spec April 2024. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I730235beea69b3720f080bbade083c2eeed26587 --- M payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/pt.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/smm/smm_module_loader.c M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 12 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/86587/1 diff --git a/payloads/libpayload/arch/x86/head_64.S b/payloads/libpayload/arch/x86/head_64.S index 6524274..1fd0d01 100644 --- a/payloads/libpayload/arch/x86/head_64.S +++ b/payloads/libpayload/arch/x86/head_64.S @@ -70,7 +70,7 @@ movl %eax, cb_header_ptr call init_page_table - movl $pm4le, %eax + movl $pml4e, %eax /* load identity mapped page tables */ movl %eax, %cr3 @@ -107,7 +107,7 @@ movq %rdi, cb_header_ptr call init_page_table - movq $pm4le, %rax + movq $pml4e, %rax /* load identity mapped page tables */ movq %rax, %cr3 diff --git a/payloads/libpayload/arch/x86/pt.S b/payloads/libpayload/arch/x86/pt.S index 0e6e7bf..080d044 100644 --- a/payloads/libpayload/arch/x86/pt.S +++ b/payloads/libpayload/arch/x86/pt.S @@ -41,10 +41,10 @@ #define _D (1ULL << 6) #define _PS (1ULL << 7) -.section .bss.pm4le -.global pm4le +.section .bss.pml4e +.global pml4e .align 4096 -pm4le: +pml4e: .skip 8 .section .bss.main_page_table @@ -144,6 +144,6 @@ leave: or $(_PRES + _RW + _US + _A), %eax - mov %eax, pm4le + mov %eax, pml4e ret diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 227ddf4..de945a9 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -163,7 +163,7 @@ subl $4, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 9485cd4..7186422 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 1cb422d..1843954 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ subl $4, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi /* BIST */ diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index 18c6425..3be56c4 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -21,7 +21,7 @@ mov %esp, %ebp /* Enter long mode, preserves ebx */ - setup_longmode $PM4LE + setup_longmode $PML4E /* Align stack */ movabs $0xfffffffffffffff0, %rax diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 4b2f3c8..1297296 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) -.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT) .align 4096 diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 3502964..42cdfb1 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) -.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT) .align 4096 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index c6d0753..ba92e1ff 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -420,27 +420,27 @@ #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) #define PAGE_SIZE 8 -/* Return the PM4LE */ +/* Return the PML4E */ static uintptr_t install_page_table(const uintptr_t handler_base) { const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26)); /* 4 1G pages or 4 PDPE entries with 512 * 2M pages */ const size_t pages_needed = one_g_pages ? 4 : 2048 + 4; const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096); - const uintptr_t pm4le = ALIGN_DOWN(pages_base - 8, 4096); + const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096); if (one_g_pages) { for (size_t i = 0; i < 4; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i)); - write64p(pm4le, _GEN_DIR(pages_base)); + write64p(pml4e, _GEN_DIR(pages_base)); } else { for (size_t i = 0; i < 2048; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i)); - write64p(pm4le, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); + write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); for (size_t i = 0; i < 4; i++) write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i)); } - return pm4le; + return pml4e; } /* diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 0e0be52..b754588 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -28,7 +28,7 @@ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E #endif /* Clear .bss section */ diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 2c4beeb..b84a06e 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -280,7 +280,7 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4e057f0..ed735db 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -83,7 +83,7 @@ movl %ecx, temp_memory_start #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movl %ebp, %edi shlq $32, %rdi movd %mm1, %rsi -- To view, visit https://review.coreboot.org/c/coreboot/+/86587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Gerrit-Change-Number: 86587 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XS] Change in coreboot[main]: soc/amd/phoenix: Remove outdated TODO comments
by Felix Held (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nick Kochlowski, Patrick Rudolph, Paul Menzel. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85719?usp=email ) Change subject: soc/amd/phoenix: Remove outdated TODO comments ...................................................................... Patch Set 16: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/85719/comment/46733845_d7f520ab?us… : PS16, Line 30: TODO > Good question. […] we probably shouldn't remove those without having a look if the common code selected by this is still correct of this soc. at least that's why those were added so that we know what we checked in detail and what hasn't been checked in detail yet -- To view, visit https://review.coreboot.org/c/coreboot/+/85719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I137dbba5094ae8cbf842b45d6137c5b0528e5413 Gerrit-Change-Number: 85719 Gerrit-PatchSet: 16 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 16:01:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Nick Kochlowski <nickkochlowski(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Support body detection to DPTF
by Kapil Porwal (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86494?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Support body detection to DPTF ...................................................................... Patch Set 2: (2 comments) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/86494/comment/bf4e7a12_d9d52955?us… : PS2, Line 202: \_SB.DPTF.ODVP() same as above. https://review.coreboot.org/c/coreboot/+/86494/comment/c1ec81d1_a733c22e?us… : PS2, Line 480: \_SB.DPTF.ODVP() Is it really required? -- To view, visit https://review.coreboot.org/c/coreboot/+/86494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2 Gerrit-Change-Number: 86494 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 15:24:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: chromeos/Kconfig: BMP_LOGO only if using FSP
by Paz Zcharya (Code Review) 24 Feb '25

24 Feb '25

Paz Zcharya has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86563?usp=email ) Change subject: chromeos/Kconfig: BMP_LOGO only if using FSP ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1d5118401981917d86e09b4b3d2bab5af052d6e Gerrit-Change-Number: 86563 Gerrit-PatchSet: 2 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: refactor: Consolidate bmp_logo_filename() logic
by Paz Zcharya (Code Review) 24 Feb '25

24 Feb '25

Paz Zcharya has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86566?usp=email ) Change subject: refactor: Consolidate bmp_logo_filename() logic ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd91af411aff6ccd6f5974a0b6c849794b9a2794 Gerrit-Change-Number: 86566 Gerrit-PatchSet: 1 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable to...
by Matt DeVillier (Code Review) 24 Feb '25

24 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86542?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable touchpad ...................................................................... mb/google/fatcat/var/felino: Modify the overridetree.cb for enable touchpad Modify the overridetree.cb configuration and gpio.c to enable touchpad. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86542 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/felino/gpio.c M src/mainboard/google/fatcat/variants/felino/overridetree.cb 2 files changed, 15 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index 6c75a41..e5ca754 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -222,10 +222,10 @@ PAD_NC(GPP_E10, NONE), /* GPP_E11: NC */ PAD_NC(GPP_E11, NONE), - /* GPP_E12: I2C0_SOC_SCL */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - /* GPP_E13: I2C0_SOC_SDA */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* GPP_E12: I2C4_SOC_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), + /* GPP_E13: I2C4_SOC_SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* GPP_E14: NC */ PAD_NC(GPP_E14, NONE), /* GPP_E15: NC */ @@ -235,7 +235,7 @@ /* GPP_E17: NC */ PAD_NC(GPP_E17, NONE), /* GPP_E18: TOUCHPAD_INT_N */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), /* GPP_E19: HW_ID5 */ PAD_CFG_GPO(GPP_E19, 1, PLTRST), /* GPP_E20: HW_ID4 */ diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 62b4160..6b4d32e 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -70,6 +70,9 @@ }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 350, + .data_hold_time_ns = 400, }, }" @@ -231,14 +234,13 @@ end # I2C1 device ref i2c4 on - chip drivers/i2c/hid - register "generic.hid" = ""P3840"" - register "generic.desc" = ""Synaptics TOUCHPAD"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" - register "generic.uid" = "5" - register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)" + register "wake" = "GPE0_DW2_18" + register "detect" = "1" + device i2c 0x15 on end end end # I2C4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135 Gerrit-Change-Number: 86542 Gerrit-PatchSet: 3 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: soc/amd/cezanne: Add ACPI opregion to root complex
by Felix Held (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier. Felix Held has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/77682?usp=email ) Change subject: soc/amd/cezanne: Add ACPI opregion to root complex ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/77682/comment/53a5261c_eeedf17e?us… : PS1, Line 195: 0x60 > so is this access done on system startup/reboot/resume or when audio playback is started? if it's th […] with the comment i'm ok with this; mainly due to not having a significantly better solution for the problem. if we find a better solution, this should eventually be reworked -- To view, visit https://review.coreboot.org/c/coreboot/+/77682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443 Gerrit-Change-Number: 77682 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 12:54:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: google/fatcat/var/fatcat: Update GSPI0 CS pin
by Jayvik Desai (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Andy Ebrahiem, Henry Barnor, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Andy Ebrahiem, Henry Barnor, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86480?usp=email to look at the new patch set (#6). Change subject: google/fatcat/var/fatcat: Update GSPI0 CS pin ...................................................................... google/fatcat/var/fatcat: Update GSPI0 CS pin GPP_F18 is currently shared between the FPS GSPI0-CS and the touchpad THC1-INT. This commit moves the FPS GSPI0-CS signal to GPP_E17, which is a GSPI-0 CS alternative option. BUG=b:395147436 TEST=build fatcat Change-Id: I9d80e163fd4e3e21cc153091bb40763e78d6c595 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86480/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86480?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d80e163fd4e3e21cc153091bb40763e78d6c595 Gerrit-Change-Number: 86480 Gerrit-PatchSet: 6 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Henry Barnor <hbarnor(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Henry Barnor <hbarnor(a)chromium.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025