coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in coreboot[main]: drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed
by Matt DeVillier (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86401?usp=email ) Change subject: drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: this needs to be moved after CB:86400 so you're dereferencing the GPIO struct and not an integer -- To view, visit https://review.coreboot.org/c/coreboot/+/86401?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4 Gerrit-Change-Number: 86401 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:31:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: util/cbfstool: Add missing \n in debug messages
by Jérémy Compostella (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Intel coreboot Reviewers, Jincheng Li, Patrick Rudolph, Shuo Liu. Jérémy Compostella has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86567?usp=email ) Change subject: util/cbfstool: Add missing \n in debug messages ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Could you as well mention that it replaces a hardcoded function name with `__func__` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8 Gerrit-Change-Number: 86567 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:20:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/cnvi: Increase the reset delay to 160ms from 105ms
by Matt DeVillier (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Paul Menzel, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86489?usp=email ) Change subject: soc/intel/cnvi: Increase the reset delay to 160ms from 105ms ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86489?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19c1bf7eeffa340e2564381a184ebfaca89bf364 Gerrit-Change-Number: 86489 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:18:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
by Jérémy Compostella (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Ronak Kanabar, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86452?usp=email ) Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Gerrit-Change-Number: 86452 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:13:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: commonlib/device_tree: fix 64-bit misaligned member access
by Joel Bueno (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Carlos López, Maximilian Brune, Philipp Hug, ron minnich. Joel Bueno has posted comments on this change by Joel Bueno. ( https://review.coreboot.org/c/coreboot/+/85800?usp=email ) Change subject: commonlib/device_tree: fix 64-bit misaligned member access ...................................................................... Patch Set 4: (3 comments) Patchset: PS4: Added a secondary change to actually add the FDT parsing for Spike target: https://review.coreboot.org/c/coreboot/+/86588/1 This one is to fix one of the issues we found for RV when doing so. Commit Message: https://review.coreboot.org/c/coreboot/+/85800/comment/7ceb6170_86ac0e01?us… : PS3, Line 16: his does not happen on qemu because, for that target, we parse the : FDT instead of manually probing memory. > Its your choice, but you might as well re-use this patch. Acknowledged https://review.coreboot.org/c/coreboot/+/85800/comment/269f5e9a_3e0aa45e?us… : PS3, Line 19: TEST=boot verified on SPIKE-RISCV > Could you also add the cmdline of spike that you tested with? (makes it easier to reproduce). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Gerrit-Change-Number: 85800 Gerrit-PatchSet: 4 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Joel Bueno <joel.bueno(a)openchip.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts
by Jayvik Desai (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Brian Hsu, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro. Jayvik Desai has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/86535?usp=email ) Change subject: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Gerrit-Change-Number: 86535 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:08:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table
by Jayvik Desai (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, Wonkyu Kim. Jayvik Desai has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:08:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: soc/riscv/ucb: Switch to FDT parsing to get memory size
by Joel Bueno (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Joel Bueno has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86588?usp=email ) Change subject: soc/riscv/ucb: Switch to FDT parsing to get memory size ...................................................................... soc/riscv/ucb: Switch to FDT parsing to get memory size Currently, coreboot tries to manually probe the memory for the Spike target as part of the SOC_UCB_RISCV target. However, Spike already passes a pointer to the device tree, so use it instead to get the memory size (like qemu-riscv does). TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf) Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43 Signed-off-by: joel.bueno <joel.bueno(a)openchip.com> --- M src/soc/ucb/riscv/Kconfig M src/soc/ucb/riscv/cbmem.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/86588/1 diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index bd0945e..e8a8d37 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -9,6 +9,7 @@ select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select RISCV_USE_ARCH_TIMER + select FLATTENED_DEVICE_TREE bool default n diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 5c423a0..6d2f20d 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <commonlib/device_tree.h> +#include <mcall.h> uintptr_t cbmem_top_chipset(void) { - return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + uint64_t top; + + top = fdt_get_memory_top((void *)HLS()->fdt); + ASSERT_MSG(top, "Failed reading memory range from FDT"); + + return MIN(top, (uint64_t)4 * GiB - 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43 Gerrit-Change-Number: 86588 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

1 0

[S] Change in coreboot[main]: commonlib/device_tree: fix 64-bit misaligned member access
by Joel Bueno (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Carlos López, Joel Bueno, Philipp Hug, ron minnich. Hello Carlos López, Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85800?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Carlos López, Verified+1 by build bot (Jenkins) Change subject: commonlib/device_tree: fix 64-bit misaligned member access ...................................................................... commonlib/device_tree: fix 64-bit misaligned member access On RISC-V (or any other platform), pointers to 64-bit values in the device tree (spanning 2 cells) are not guaranteed to be aligned to a 64-bit boundary, which can cause a load access fault on some platforms (see [0]). This is observed with the default Spike device tree. Thus, perform two 32-bit loads instead. [0] https://lore.kernel.org/qemu-devel/41c1c574-da5c-654a-f993-4b87e089380e@red… Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Signed-off-by: joel.bueno <joel.bueno(a)openchip.com> --- M src/commonlib/device_tree.c 1 file changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85800/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Gerrit-Change-Number: 85800 Gerrit-PatchSet: 4 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Attention: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

1 0

[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Jayvik Desai (Code Review) 24 Feb '25

24 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro. Jayvik Desai has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86555?usp=email ) Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 18:03:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025