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Change subject: mb/intel/ptlrvp: Initial commit for Intel Panther Lake RVP
......................................................................
Patch Set 4:
This change is ready for review.
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Change subject: soc/riscv/ucb: Switch to FDT parsing to get memory size
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
......................................................................
Patch Set 1:
(2 comments)
File src/soc/amd/common/block/lpc/lpc_util.c:
https://review.coreboot.org/c/coreboot/+/86582/comment/7f3ac32c_ad4f9ec8?us… :
PS1, Line 280: if (CONFIG_COREBOOT_ROMSIZE_KB <= 16384)
nit:
add comment like:
```
limit the mapping to a maximum of 16MiB.
```
https://review.coreboot.org/c/coreboot/+/86582/comment/ce4234bc_49441020?us… :
PS1, Line 284: pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0xff00);
nit:
I guess you could also write:
```
pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 - (MIN(CONFIG_COREBOOT_ROMSIZE_KB, 16384) >> 6));
```
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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
......................................................................
Patch Set 22:
(1 comment)
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85454/comment/4e50e22f_30035a74?us… :
PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> > I have raised a bug to track the discussion further here: b/398872610. […]
What would be the expected syntax? `TODO:b:398872610` ?
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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 22: Code-Review+2
(1 comment)
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85454/comment/31115bd5_7341bac2?us… :
PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> I have raised a bug to track the discussion further here: b/398872610.
>
> I am OK with adding a TODO here pointing to that bug.
@jeremy.compostella@intel.corp-partner.google.com are you okay to add a bug id in the code and push new patch set ?
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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
......................................................................
Patch Set 22: Code-Review+1
(1 comment)
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85454/comment/1088bed5_17cf3fd2?us… :
PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> > Combining the comment from a similar discussion here: […]
I have raised a bug to track the discussion further here: b/398872610.
I am OK with adding a TODO here pointing to that bug.
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Change subject: cpu/x86/64bit: Allow to map more of the address space
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/64bit/pt1G.S:
https://review.coreboot.org/c/coreboot/+/86580/comment/5e910449_aeb4cb7f?us… :
PS1, Line 23: .rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
> It points to every PDPT entry in the specified address space. […]
Thats what I was trying to say. We agree on that. I would just like to see a small comment making that clear. Its not particularly important, but the page table assembly can be hard to read for people who have never seen it before, so it would be nice to have small comment explaining what the PML4E entries do.
At this point we could also rename it to PML4T, since it is the table and not a single entry. Similarly to what we do down below using PDPT instead of PDPE.
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Attention is currently required from: Joel Bueno, Philipp Hug, ron minnich.
Hello Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86588?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/riscv/ucb: Switch to FDT parsing to get memory size
......................................................................
soc/riscv/ucb: Switch to FDT parsing to get memory size
Currently, coreboot tries to manually probe the memory for
the Spike target as part of the SOC_UCB_RISCV target.
However, Spike already passes a pointer to the device tree,
so use it instead to get the memory size (like qemu-riscv does).
TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf)
Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43
Signed-off-by: joel.bueno <joel.bueno(a)openchip.com>
---
M src/soc/ucb/riscv/Kconfig
M src/soc/ucb/riscv/cbmem.c
2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/86588/3
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