coreboot-gerrit February 2025

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[S] Change in coreboot[main]: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts
by Subrata Banik (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Brian Hsu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/86535?usp=email ) Change subject: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Gerrit-Change-Number: 86535 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Feb 2025 02:17:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: util/inteltool: Add gen_coreboot_ifd.py
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Pratikkumar V Prajapati. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86577?usp=email ) Change subject: util/inteltool: Add gen_coreboot_ifd.py ...................................................................... util/inteltool: Add gen_coreboot_ifd.py This tool takes an UEFI IFWI, extract the IFD and update its content to support 16MB+ BIOS region. DoC ID referred to: 642713 Change-Id: Ieb01e295ea1fbb08a1c7d19a536a55e4dcd6f9c1 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- A util/inteltool/gen_coreboot_ifd.py 1 file changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/86577/1 diff --git a/util/inteltool/gen_coreboot_ifd.py b/util/inteltool/gen_coreboot_ifd.py new file mode 100644 index 0000000..99ea0a6 --- /dev/null +++ b/util/inteltool/gen_coreboot_ifd.py @@ -0,0 +1,71 @@ +#! /usr/bin/env python3 +# +# SPDX-License-Identifier: BSD-3-Clause + +import sys +import getopt + +def ifd_replace(input_file, output_file, bios_size): + # + # Extract the first 4K of UEFI IFWI binary + # + with open(input_file,"rb") as input: + first_4k = input.read(4 * 1024) + with open(output_file,"wb") as output: + output.write(first_4k) + + # + # Replace the data + # + with open(output_file,"r+b") as file: + # 1. 0x15 -- Number of Components + # Chapter 4.1.1.2 of Doc#642713 + data = b'\x00' + hex_offset = '0x15' + offset=int(hex_offset,16) + file.seek(offset) + file.write(data) + + # 2. 0x44 -- Flash Region Base Address (BIOS) + # Chapter 4.1.3.2 of Doc#642713 + if bios_size == '16M': + data = b'\x00\x30\xFF\x3F' + elif bios_size == '32M': + data = b'\x00\x20\xFF\x3F' + elif bios_size == '48M': + data = b'\x00\x10\xFF\x3F' + hex_offset = '0x44' # FRBA + 004h + offset=int(hex_offset,16) + file.seek(offset) + file.write(data) + + # 3. 0x48-0x7F -- Flash Region Base Address (Reserved) + # Chapter 4.1.3.3 of Doc#642713 + num = 14 # Number of Flash Region + data = b'\xFF\x7F\x00\x00' # 7FFFh is not used data + hex_offset = '0x48' # FRBA + 008h + offset=int(hex_offset,16) + file.seek(offset) + # Go through flash region from 2 to 15 + for _ in range(num): + file.write(data) + + print(output_file + ' is generated.') + +if __name__ == '__main__': + print('Creating Flash Descriptor...') + argv = sys.argv[1:] + try: + opts, args = getopt.getopt(argv, "b:") + except: + print ('ERROR: Incorrect arguments! -b <UEFI IFWI>') + print ('For example: gen_coreboot_ifd.py -b BHSDCRB1.xxx_SP_1.bin') + sys.exit(2) + + for opt, arg in opts: + if opt in ['-b']: + binary = arg + + ifd_replace(binary, 'descriptor_16m.bin','16M') + ifd_replace(binary, 'descriptor_32m.bin','32M') + ifd_replace(binary, 'descriptor_48m.bin','48M') -- To view, visit https://review.coreboot.org/c/coreboot/+/86577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb01e295ea1fbb08a1c7d19a536a55e4dcd6f9c1 Gerrit-Change-Number: 86577 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[S] Change in coreboot[main]: mainboard/intel/beechnutcity_crb: Support configurable BIOS region
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

1 0

[S] Change in coreboot[main]: mainboard/intel/avenuecity_crb: Support configurable BIOS region
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Config FIXED_MMIO_REGION_BASE/SIZE
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve SoC MMIO region in CBFS
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86573?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Reserve SoC MMIO region in CBFS ...................................................................... soc/intel/xeon_sp: Reserve SoC MMIO region in CBFS Ensure CBFS does not overlap with SoC MMIO by reserving space with mmio_reserved.bin for BIOS sizes over 16MB. Change-Id: I122821975afde9e234147a66e2f4c09dbe10815d Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.mk 2 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86573/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index f61de56..2356c20 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -116,4 +116,16 @@ default y select SHADOW_ROM_TABLE_TO_EBDA +config FIXED_MMIO_REGION_BASE + hex + help + MMIO reservation windows below 4GB-16MB boundary to hold + SoC fixed mapping like CACHE as RAM, local APIC, et al. + +config FIXED_MMIO_REGION_SIZE + hex + help + MMIO reservation windows below 4GB-16MB boundary to hold + SoC fixed mapping like CACHE as RAM, local APIC, et al. + endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index c66b8ad..2227c99 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -32,4 +32,21 @@ CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h -endif ## XEON_SP_COMMON_BASE +ifeq ($(call int-gt, $(CONFIG_BIOS_SIZE) 0x01000000), 1) +DD_COUNT=$(call int-divide, $(CONFIG_FIXED_MMIO_REGION_SIZE) 0x100000) +$(shell `dd if=/dev/zero of=$(obj)/mmio_reserved.bin bs=M count=$(DD_COUNT)`) +cbfs-files-y += mmio_reserved.bin + +mmio_reserved.bin-file ?= $(obj)/mmio_reserved.bin +mmio_reserved.bin-type := raw +mmio_reserved.bin-align := 16 + +ifneq ($(CONFIG_FIXED_MMIO_REGION_BASE),) +mmio_reserved.bin-COREBOOT-position := $(CONFIG_FIXED_MMIO_REGION_BASE) +else +$(warning "FIXED_MMIO_REGION_BASE should be set!") +endif + +endif + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I122821975afde9e234147a66e2f4c09dbe10815d Gerrit-Change-Number: 86573 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: util/cbfstool: Support CONFIG_BIOS_SIZE in cbfstool
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Chen, Gang C. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86572?usp=email to review the following change. Change subject: util/cbfstool: Support CONFIG_BIOS_SIZE in cbfstool ...................................................................... util/cbfstool: Support CONFIG_BIOS_SIZE in cbfstool Update cbfstool to refer to CONFIG_BIOS_SIZE for support of BIOS sizes exceeding 16MB Change-Id: I6fd4fb216611fda3d261d4fff9871cfff1ed655f Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M util/cbfstool/Makefile.mk M util/cbfstool/cbfstool.c 2 files changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/86572/1 diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk index 8577874..53c672e 100644 --- a/util/cbfstool/Makefile.mk +++ b/util/cbfstool/Makefile.mk @@ -124,6 +124,7 @@ TOOLCPPFLAGS += -I$(objutil)/cbfstool TOOLCPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h +TOOLCPPFLAGS += -include $(obj)/config.h TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/host/include @@ -161,43 +162,43 @@ DEBUG= \ hostlib -$(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c +$(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/flashmap/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/flashmap/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/C/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/C/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/src/commonlib/%.c +$(objutil)/cbfstool/%.o: $(top)/src/commonlib/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/src/commonlib/bsd/%.c +$(objutil)/cbfstool/%.o: $(top)/src/commonlib/bsd/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) $(LZ4CFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/fpt_formats/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/fpt_formats/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/bpdt_formats/%.c +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/bpdt_formats/%.c $(obj)/config.h printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index bde61b5..eb55eea 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -392,7 +392,7 @@ } #define DEFAULT_DECODE_WINDOW_TOP (4ULL * GiB) -#define DEFAULT_DECODE_WINDOW_MAX_SIZE (16 * MiB) +#define DEFAULT_DECODE_WINDOW_MAX_SIZE MAX(16 * MiB, CONFIG_BIOS_SIZE) static bool create_mmap_windows(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fd4fb216611fda3d261d4fff9871cfff1ed655f Gerrit-Change-Number: 86572 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com>

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[M] Change in coreboot[main]: tree: Rename CBFS_SIZE to BIOS_SIZE
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Alexander Couzens, Alicja Michalska, Angel Pons, Christian Walter, Dinesh Gehlot, Eran Mitrani, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jason Glenesk, Jason Nien, Jayvik Desai, Jeremy Soller, Jonathon Hall, Kapil Porwal, Martin L Roth, Martin Roth, Maxim Polyakov, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nicholas Chin, Nick Vaccaro, Patrick Rudolph, Piotr Król, Pranava Y N, Stefan Ott, Subrata Banik, Tarun, Tim Crawford, Werner Zeh, yuchi.chen(a)intel.com. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86571?usp=email ) Change subject: tree: Rename CBFS_SIZE to BIOS_SIZE ...................................................................... tree: Rename CBFS_SIZE to BIOS_SIZE Kconfig item CBFS_SIZE is actually indicating the host firmware size, a.k.a. the size of the BIOS region. Do the rename for clarification. Change-Id: I762042fae6357ee368b22a47b8e1168902041675 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M Documentation/getting_started/kconfig.md M Documentation/mainboard/lenovo/Ivy_Bridge_series.md M Documentation/releases/coreboot-24.02-relnotes.md M Documentation/releases/coreboot-24.05-relnotes.md M Documentation/releases/coreboot-24.08-relnotes.md M Documentation/releases/coreboot-4.20.1-relnotes.md M Documentation/releases/coreboot-4.21-relnotes.md M Documentation/releases/coreboot-4.22-relnotes.md M Documentation/tutorial/part1.md M Makefile.mk M configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 M configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 M configs/config.emulation_qemu_aarch64_fit_support_timestamps M configs/config.intel_harcuvar M configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs M configs/config.msi_ms7d25_ddr5 M configs/config.protectli_vp2420 M src/Kconfig M src/mainboard/acer/aspire_vn7_572g/Kconfig M src/mainboard/amd/bilby/Kconfig M src/mainboard/amd/mandolin/Kconfig M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/asrock/imb-1222/Kconfig M src/mainboard/asrock/z97_extreme6/Kconfig M src/mainboard/asus/h61-series/Kconfig M src/mainboard/bostentech/gbyt4/Kconfig M src/mainboard/clevo/cml-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/dell/e6400/Kconfig M src/mainboard/dell/optiplex_3050/Kconfig M src/mainboard/dell/optiplex_9020/Kconfig M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/mainboard/dell/xps_8300/Kconfig M src/mainboard/erying/tgl/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/veyron/Kconfig M src/mainboard/hp/pro_3500_series/Kconfig M src/mainboard/hp/snb_ivb_desktops/Kconfig M src/mainboard/intel/dcp847ske/Kconfig M src/mainboard/intel/frost_creek/Kconfig M src/mainboard/intel/strago/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/lenovo/m920q/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/msi/ms7707/Kconfig M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7e06/Kconfig M src/mainboard/novacustom/mtl-h/Kconfig M src/mainboard/portwell/m107/Kconfig M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/protectli/vault_adl_p/Kconfig M src/mainboard/protectli/vault_bsw/Kconfig M src/mainboard/protectli/vault_cml/Kconfig M src/mainboard/protectli/vault_ehl/Kconfig M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/purism/librem_cnl/Kconfig M src/mainboard/purism/librem_jsl/Kconfig M src/mainboard/purism/librem_l1um_v2/Kconfig M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/roda/rk9/Kconfig M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/supermicro/x10slm-f/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x9scl/Kconfig M src/mainboard/system76/addw1/Kconfig M src/mainboard/system76/bonw14/Kconfig M src/mainboard/system76/cml-u/Kconfig M src/mainboard/system76/gaze15/Kconfig M src/mainboard/system76/kbl-u/Kconfig M src/mainboard/system76/oryp5/Kconfig M src/mainboard/system76/oryp6/Kconfig M src/mainboard/system76/whl-u/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/pantherlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/southbridge/intel/common/firmware/Kconfig M util/cbfstool/default-x86.fmd M util/cbfstool/default.fmd M util/ifdtool/ifdtool.c 100 files changed, 108 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/86571/1 diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 4aa00a2..d48919c 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -969,7 +969,7 @@ Example of various symbol types in the config.h file: #define CONFIG_BOOTBLOCK_SOURCE "bootblock_simple.c" # String - #define CONFIG_CBFS_SIZE 0x00300000 # Hex + #define CONFIG_BIOS_SIZE 0x00300000 # Hex #define CONFIG_TTYS0_BAUD 115200 # Int #define CONFIG_HAVE_ACPI_TABLES 1 # Bool enabled #define CONFIG_EXPERT 0 # Bool disabled @@ -990,7 +990,7 @@ ## General setup ## CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # String - CONFIG_CBFS_SIZE=0x00300000 # Hex + CONFIG_BIOS_SIZE=0x00300000 # Hex CONFIG_TTYS0_BAUD=115200 # Int CONFIG_HAVE_ACPI_TABLES=y # Bool enabled # CONFIG_EXPERT is not set # Bool disabled diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index a7893e7..1542efd 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -34,7 +34,7 @@ * The *Flash layout* shows that by default 7MiB of space are available for the use with coreboot. * In that case you only want to use a part of the BIOS region that must not - exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. + exceed 4MiB in size, which means CONFIG_BIOS_SIZE must be smaller than 4MiB. * ROM chip size should be set to 12MiB. ```{eval-rst} diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md index 90bd138..5d8173c 100644 --- a/Documentation/releases/coreboot-24.02-relnotes.md +++ b/Documentation/releases/coreboot-24.02-relnotes.md @@ -255,7 +255,7 @@ +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ -| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +| 457 | Haswell (t440p): CAR mem region conflicts with BIOS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | +-----+-----------------------------------------------------------------+ diff --git a/Documentation/releases/coreboot-24.05-relnotes.md b/Documentation/releases/coreboot-24.05-relnotes.md index 6d34e5b..8251072 100644 --- a/Documentation/releases/coreboot-24.05-relnotes.md +++ b/Documentation/releases/coreboot-24.05-relnotes.md @@ -231,7 +231,7 @@ +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ -| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +| 457 | Haswell (t440p): CAR mem region conflicts with BIOS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | +-----+-----------------------------------------------------------------+ diff --git a/Documentation/releases/coreboot-24.08-relnotes.md b/Documentation/releases/coreboot-24.08-relnotes.md index 046b77b..5962dec 100644 --- a/Documentation/releases/coreboot-24.08-relnotes.md +++ b/Documentation/releases/coreboot-24.08-relnotes.md @@ -379,7 +379,7 @@ +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ -| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +| 457 | Haswell (t440p): CAR mem region conflicts with BIOS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | +-----+-----------------------------------------------------------------+ diff --git a/Documentation/releases/coreboot-4.20.1-relnotes.md b/Documentation/releases/coreboot-4.20.1-relnotes.md index d0c537d..6e8fe89 100644 --- a/Documentation/releases/coreboot-4.20.1-relnotes.md +++ b/Documentation/releases/coreboot-4.20.1-relnotes.md @@ -238,7 +238,7 @@ +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ -| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +| 457 | Haswell (t440p): CAR mem region conflicts with BIOS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio device not showing up after libgfxinit | +-----+-----------------------------------------------------------------+ diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md index 661c019..37b04ed 100644 --- a/Documentation/releases/coreboot-4.21-relnotes.md +++ b/Documentation/releases/coreboot-4.21-relnotes.md @@ -368,7 +368,7 @@ +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ -| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +| 457 | Haswell (t440p): CAR mem region conflicts with BIOS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio device not showing up after libgfxinit | +-----+-----------------------------------------------------------------+ diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index f5ca7e8..015e5d3 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -304,7 +304,7 @@ +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ -| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +| 457 | Haswell (t440p): CAR mem region conflicts with BIOS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | +-----+-----------------------------------------------------------------+ diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index cd22b0b..9d5b27f 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -136,7 +136,7 @@ toolchain): ```Text -CONFIG_CBFS_SIZE=0x00400000 +CONFIG_BIOS_SIZE=0x00400000 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 diff --git a/Makefile.mk b/Makefile.mk index 054ac13..470914a 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1100,8 +1100,8 @@ FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE -FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) -FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) +FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_BIOS_SIZE)), 0x10000) +FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_BIOS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE # @@ -1179,7 +1179,7 @@ # # position and size of CBFS, relative to BIOS_BASE FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) -FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +FMAP_BIOS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) @@ -1190,7 +1190,7 @@ # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE FMAP_BIOS_BASE := 0 -FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +FMAP_BIOS_SIZE := $(CONFIG_BIOS_SIZE) # position and size of flashmap, relative to BIOS_BASE FMAP_FMAP_BASE := 0x20000 FMAP_FMAP_SIZE := 0x200 @@ -1228,7 +1228,7 @@ # # position and size of CBFS, relative to BIOS_BASE FMAP_CBFS_BASE := $(FMAP_CURRENT_BASE) -FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +FMAP_BIOS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) endif # ifeq ($(CONFIG_ARCH_X86),y) @@ -1246,7 +1246,7 @@ -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ -e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ - -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ + -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp mv $@.tmp $@ else # ifeq ($(CONFIG_FMDFILE),) diff --git a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 index d389ac0..0d09586 100644 --- a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 +++ b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 @@ -15,7 +15,7 @@ CONFIG_UBSAN=y CONFIG_VENDOR_ASROCK=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y -CONFIG_CBFS_SIZE=0x200000 +CONFIG_BIOS_SIZE=0x200000 CONFIG_BOARD_ASROCK_B85M_PRO4=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_PCIEXP_CLK_PM=y diff --git a/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 b/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 index 167909d..252b968 100644 --- a/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 +++ b/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 @@ -10,7 +10,7 @@ # + VESA framebuffer # + EM100 support CONFIG_VENDOR_ASUS=y -CONFIG_CBFS_SIZE=0x200000 +CONFIG_BIOS_SIZE=0x200000 CONFIG_BOARD_ASUS_P8Z77_V_LX2=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_PCIEXP_CLK_PM=y diff --git a/configs/config.emulation_qemu_aarch64_fit_support_timestamps b/configs/config.emulation_qemu_aarch64_fit_support_timestamps index 2b5234a..f5dbc79 100644 --- a/configs/config.emulation_qemu_aarch64_fit_support_timestamps +++ b/configs/config.emulation_qemu_aarch64_fit_support_timestamps @@ -2,7 +2,7 @@ CONFIG_COLLECT_TIMESTAMPS=y CONFIG_TIMESTAMPS_ON_CONSOLE=y CONFIG_MAINBOARD_VENDOR="Emulation" -CONFIG_CBFS_SIZE=0x1000000 +CONFIG_BIOS_SIZE=0x1000000 CONFIG_BOARD_EMULATION_QEMU_AARCH64=y CONFIG_COREBOOT_ROMSIZE_KB_16384=y CONFIG_PAYLOAD_FIT_SUPPORT=y diff --git a/configs/config.intel_harcuvar b/configs/config.intel_harcuvar index 3476817..1d7c2ed 100644 --- a/configs/config.intel_harcuvar +++ b/configs/config.intel_harcuvar @@ -1,6 +1,6 @@ CONFIG_COLLECT_TIMESTAMPS=y CONFIG_VENDOR_INTEL=y -CONFIG_CBFS_SIZE=0x800000 +CONFIG_BIOS_SIZE=0x800000 CONFIG_BOARD_INTEL_HARCUVAR=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_ENABLE_HSUART=y diff --git a/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs b/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs index 752e37f..4d40ddf 100644 --- a/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs +++ b/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs @@ -1,5 +1,5 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_VENDOR_LENOVO=y -CONFIG_CBFS_SIZE=0x200000 +CONFIG_BIOS_SIZE=0x200000 CONFIG_BOARD_LENOVO_X220=y CONFIG_DEBUG_TPM=y diff --git a/configs/config.msi_ms7d25_ddr5 b/configs/config.msi_ms7d25_ddr5 index e26e99e..d81c203 100644 --- a/configs/config.msi_ms7d25_ddr5 +++ b/configs/config.msi_ms7d25_ddr5 @@ -1,5 +1,5 @@ CONFIG_VENDOR_MSI=y -CONFIG_CBFS_SIZE=0x1000000 +CONFIG_BIOS_SIZE=0x1000000 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_EDK2_BOOT_TIMEOUT=3 CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR5=y diff --git a/configs/config.protectli_vp2420 b/configs/config.protectli_vp2420 index 899a956..f708c7d 100644 --- a/configs/config.protectli_vp2420 +++ b/configs/config.protectli_vp2420 @@ -1,5 +1,5 @@ CONFIG_VENDOR_PROTECTLI=y -CONFIG_CBFS_SIZE=0x900000 +CONFIG_BIOS_SIZE=0x900000 CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_EDK2_BOOT_TIMEOUT=6 diff --git a/src/Kconfig b/src/Kconfig index e4c8467..60c8768 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -629,11 +629,11 @@ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS default "" help - The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, + The build system creates a default FMAP from ROM_SIZE and BIOS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format. -config CBFS_SIZE +config BIOS_SIZE hex "Size of CBFS filesystem in ROM" depends on FMDFILE = "" # Default value set at the end of the file @@ -1538,7 +1538,7 @@ depends on BOOTSPLASH_CONVERT_RESIZE default "1024x768" -config CBFS_SIZE +config BIOS_SIZE default ROM_SIZE config HAVE_BOOTBLOCK diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig index cee7b7e..dc8059b 100644 --- a/src/mainboard/acer/aspire_vn7_572g/Kconfig +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -25,7 +25,7 @@ select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP -config CBFS_SIZE +config BIOS_SIZE default 0x600000 config CONSOLE_SERIAL diff --git a/src/mainboard/amd/bilby/Kconfig b/src/mainboard/amd/bilby/Kconfig index 9573204..9a3f477 100644 --- a/src/mainboard/amd/bilby/Kconfig +++ b/src/mainboard/amd/bilby/Kconfig @@ -43,7 +43,7 @@ default 0x4e if BILBY_SMSC_SIO1036_BASE_4E default 0x164e if BILBY_SMSC_SIO1036_BASE_164E -config CBFS_SIZE +config BIOS_SIZE default 0xfef000 # Maximum size for the Bilby FMAP config MAINBOARD_DIR diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index ce3af3b..182f956 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -47,7 +47,7 @@ default 0x4e if SMSC_SIO1036_BASE_4E default 0x164e if SMSC_SIO1036_BASE_164E -config CBFS_SIZE +config BIOS_SIZE default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 65da20d..60af5e6 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -18,7 +18,7 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config MAINBOARD_DIR diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 4edd2bc..2732351 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -20,7 +20,7 @@ select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config MAINBOARD_DIR diff --git a/src/mainboard/asrock/imb-1222/Kconfig b/src/mainboard/asrock/imb-1222/Kconfig index 93fe111..f0a5bdf 100644 --- a/src/mainboard/asrock/imb-1222/Kconfig +++ b/src/mainboard/asrock/imb-1222/Kconfig @@ -32,7 +32,7 @@ config MAINBOARD_VERSION default "imb-1222" -config CBFS_SIZE +config BIOS_SIZE default 0xc00000 config CONSOLE_POST diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig index 3cef429..abffbd0 100644 --- a/src/mainboard/asrock/z97_extreme6/Kconfig +++ b/src/mainboard/asrock/z97_extreme6/Kconfig @@ -18,7 +18,7 @@ select SUPERIO_NUVOTON_NCT6791D select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config MAINBOARD_DIR diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 4c4fd7e..36043c4 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -99,7 +99,7 @@ config CMOS_LAYOUT_FILE default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout" -config CBFS_SIZE +config BIOS_SIZE default 0x280000 if BOARD_ASUS_P8H67_I_DELUXE # diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index acfa313..0c5abaf 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -12,7 +12,7 @@ select SOC_INTEL_BAYTRAIL select SUPERIO_ITE_IT8728F -config CBFS_SIZE +config BIOS_SIZE default 0x500000 config MAINBOARD_DIR diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 5961b68..3ad2194 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -43,7 +43,7 @@ config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -config CBFS_SIZE +config BIOS_SIZE default 0xc00000 if BOARD_CLEVO_L140CU_BASE config CONSOLE_POST diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index 8de8be2..5a5e3a6 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -43,7 +43,7 @@ config MAINBOARD_PART_NUMBER default "N130WU" if BOARD_CLEVO_N130WU -config CBFS_SIZE +config BIOS_SIZE default 0x600000 if BOARD_CLEVO_N130WU config DEVICETREE diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig index 3ab0e91..aa9240b 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -42,7 +42,7 @@ config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -config CBFS_SIZE +config BIOS_SIZE default 0xb00000 if BOARD_CLEVO_L140MU config CONSOLE_POST diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig index 417d95f..29bfa4d 100644 --- a/src/mainboard/dell/e6400/Kconfig +++ b/src/mainboard/dell/e6400/Kconfig @@ -28,7 +28,7 @@ config USBDEBUG_HCD_INDEX default 1 -config CBFS_SIZE +config BIOS_SIZE default 0x1A0000 endif # BOARD_DELL_E6400 diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig index 6c8e729..cacb5f5 100644 --- a/src/mainboard/dell/optiplex_3050/Kconfig +++ b/src/mainboard/dell/optiplex_3050/Kconfig @@ -19,7 +19,7 @@ select SOC_INTEL_KABYLAKE select SUPERIO_SMSC_SCH555x -config CBFS_SIZE +config BIOS_SIZE default 0x900000 config MAINBOARD_DIR diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig index 38c3281..b336619 100644 --- a/src/mainboard/dell/optiplex_9020/Kconfig +++ b/src/mainboard/dell/optiplex_9020/Kconfig @@ -20,7 +20,7 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_SMSC_SCH555x -config CBFS_SIZE +config BIOS_SIZE default 0x600000 config MAINBOARD_DIR diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig index a1e446e..7d2e0a3 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -55,7 +55,7 @@ int default 2 -config CBFS_SIZE +config BIOS_SIZE default 0x600000 config INCLUDE_SMSC_SCH5545_EC_FW diff --git a/src/mainboard/dell/xps_8300/Kconfig b/src/mainboard/dell/xps_8300/Kconfig index 09bd4c8..68d7294 100644 --- a/src/mainboard/dell/xps_8300/Kconfig +++ b/src/mainboard/dell/xps_8300/Kconfig @@ -29,7 +29,7 @@ config VGA_BIOS_DGPU_ID default "10de,1082" -config CBFS_SIZE +config BIOS_SIZE default 0x26F000 endif diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig index e8a2a1f..12ae8b4 100644 --- a/src/mainboard/erying/tgl/Kconfig +++ b/src/mainboard/erying/tgl/Kconfig @@ -27,7 +27,7 @@ config MAINBOARD_PART_NUMBER default "TigerLake (mATX)" -config CBFS_SIZE +config BIOS_SIZE default 0xA00000 config PCIEXP_ASPM diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 1ea2ae6..c05d7fb 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -53,7 +53,7 @@ config MAINBOARD_PART_NUMBER default "FBG-1701" -config CBFS_SIZE +config BIOS_SIZE default 0x00600000 config MRC_SETTINGS_CACHE_SIZE diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 0762d28..36bd0af 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -18,7 +18,7 @@ config DISABLE_HECI1_AT_PRE_BOOT default y -config CBFS_SIZE +config BIOS_SIZE default 0x00900000 config MAINBOARD_DIR diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index eacc8ef..deef00a9 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -106,7 +106,7 @@ config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config MAINBOARD_SMBIOS_MANUFACTURER diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 60630fe..dc1cbe8 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -98,7 +98,7 @@ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/baseboard/chromeos.fmd" if CHROMEOS default "" help - The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, + The build system creates a default FMAP from ROM_SIZE and BIOS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format. diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 08af442..8996b05 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -75,7 +75,7 @@ int default 0 -config CBFS_SIZE +config BIOS_SIZE default 0x100000 if CHROMEOS default ROM_SIZE diff --git a/src/mainboard/hp/pro_3500_series/Kconfig b/src/mainboard/hp/pro_3500_series/Kconfig index ab77654..43fe4ca 100644 --- a/src/mainboard/hp/pro_3500_series/Kconfig +++ b/src/mainboard/hp/pro_3500_series/Kconfig @@ -17,7 +17,7 @@ select SUPERIO_ITE_IT8772F select USE_NATIVE_RAMINIT -config CBFS_SIZE +config BIOS_SIZE default 0x400000 config MAINBOARD_DIR diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig index c23e854..9d6ca79 100644 --- a/src/mainboard/hp/snb_ivb_desktops/Kconfig +++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig @@ -60,7 +60,7 @@ select VBOOT_NO_BOARD_SUPPORT select VBOOT_VBNV_FLASH -config CBFS_SIZE +config BIOS_SIZE default 0x2F0000 if BOARD_ROMSIZE_KB_8192 default 0x570000 if BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index b8aeeb6..1471a1c 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -45,7 +45,7 @@ int default 2 -config CBFS_SIZE +config BIOS_SIZE default 0x00640000 config MAINBOARD_SMBIOS_MANUFACTURER diff --git a/src/mainboard/intel/frost_creek/Kconfig b/src/mainboard/intel/frost_creek/Kconfig index f93ab78..08c57eb 100644 --- a/src/mainboard/intel/frost_creek/Kconfig +++ b/src/mainboard/intel/frost_creek/Kconfig @@ -18,7 +18,7 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" -config CBFS_SIZE +config BIOS_SIZE default 0xc00000 config DIMM_MAX diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 3cb99eb..11ede00 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -38,7 +38,7 @@ The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.mk as 8086,22b1 -config CBFS_SIZE +config BIOS_SIZE default 0x200000 endif # BOARD_INTEL_STRAGO diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index 588596c..dbe64fb 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -47,7 +47,7 @@ config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config CBFS_SIZE +config BIOS_SIZE default 0x600000 if BOARD_SIEMENS_BOXER26 config DIMM_MAX diff --git a/src/mainboard/lenovo/m920q/Kconfig b/src/mainboard/lenovo/m920q/Kconfig index a83b477..045070a 100644 --- a/src/mainboard/lenovo/m920q/Kconfig +++ b/src/mainboard/lenovo/m920q/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER default "ThinkCentre M920 Tiny" -config CBFS_SIZE +config BIOS_SIZE default 0x900000 endif diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 5afcde8..13d1099 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -63,7 +63,7 @@ int default 2 -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config PS2K_EISAID diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 9c78cb1..e4aaa68 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -38,7 +38,7 @@ config VBOOT_SLOTS_RW_A default y -config CBFS_SIZE +config BIOS_SIZE default 0x300000 config FMDFILE diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 29e2f6c..1766300 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -57,7 +57,7 @@ int default 2 -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config PS2K_EISAID diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig index e0dd825..4301abb 100644 --- a/src/mainboard/libretrend/lt1000/Kconfig +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -34,7 +34,7 @@ config DIMM_SPD_SIZE default 512 -config CBFS_SIZE +config BIOS_SIZE default 0x600000 config USE_PM_ACPI_TIMER diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index e784bba..cdf1aac 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -29,7 +29,7 @@ int default 2 -config CBFS_SIZE +config BIOS_SIZE default 0x200000 endif diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 1b23f03..2478600 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -50,7 +50,7 @@ bool default n -config CBFS_SIZE +config BIOS_SIZE hex default 0x1000000 diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig index b0ba216..08c2ef8 100644 --- a/src/mainboard/msi/ms7e06/Kconfig +++ b/src/mainboard/msi/ms7e06/Kconfig @@ -44,7 +44,7 @@ config USE_LEGACY_8254_TIMER default y -config CBFS_SIZE +config BIOS_SIZE default 0x1000000 config TPM_PIRQ diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig index 5d608b4..d1eb203 100644 --- a/src/mainboard/novacustom/mtl-h/Kconfig +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -58,7 +58,7 @@ string default "Not Applicable" # Match Insyde firmware, for Windows Update -config CBFS_SIZE +config BIOS_SIZE default 0xA00000 config CONSOLE_POST diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index e2cd988..176597b 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER default "PQ7-M107" -config CBFS_SIZE +config BIOS_SIZE default 0x00600000 config MRC_SETTINGS_CACHE_SIZE diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index cbd625c..5b916e3 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -45,7 +45,7 @@ int default 0 -config CBFS_SIZE +config BIOS_SIZE default 0x800000 config PCIEXP_ASPM diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index c943f6f..772c869 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -58,7 +58,7 @@ bool default n -config CBFS_SIZE +config BIOS_SIZE default 0x900000 endif # BOARD_PRODRIVE_HERMES_BASEBOARD diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig index b7578ab..dd5653d 100644 --- a/src/mainboard/protectli/vault_adl_p/Kconfig +++ b/src/mainboard/protectli/vault_adl_p/Kconfig @@ -35,7 +35,7 @@ config USE_PM_ACPI_TIMER default n -config CBFS_SIZE +config BIOS_SIZE default 0xa80000 config TPM_PIRQ diff --git a/src/mainboard/protectli/vault_bsw/Kconfig b/src/mainboard/protectli/vault_bsw/Kconfig index 8650b57..26c8b42 100644 --- a/src/mainboard/protectli/vault_bsw/Kconfig +++ b/src/mainboard/protectli/vault_bsw/Kconfig @@ -40,7 +40,7 @@ default 2 if BOARD_PROTECTLI_FW2B default 4 if BOARD_PROTECTLI_FW4B -config CBFS_SIZE +config BIOS_SIZE default 0x500000 config PXE_ROM_ID diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 87de088..c682044 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -35,7 +35,7 @@ config DIMM_SPD_SIZE default 512 -config CBFS_SIZE +config BIOS_SIZE default 0xa00000 config GFX_GMA_PANEL_1_ON_EDP diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig index 5f283ee..b81cbf6 100644 --- a/src/mainboard/protectli/vault_ehl/Kconfig +++ b/src/mainboard/protectli/vault_ehl/Kconfig @@ -26,7 +26,7 @@ config MAX_CPUS default 4 -config CBFS_SIZE +config BIOS_SIZE default 0x900000 config DIMM_MAX diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 10f8c40..5330ef34 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -41,7 +41,7 @@ string default "8086,150c" -config CBFS_SIZE +config BIOS_SIZE default 0x600000 config USE_PM_ACPI_TIMER diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index a718678..4ea99d6 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -61,7 +61,7 @@ config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config CBFS_SIZE +config BIOS_SIZE default 0x800000 if BOARD_PURISM_LIBREM_MINI default 0xA00000 if BOARD_PURISM_LIBREM_MINI_V2 default 0x900000 if BOARD_PURISM_LIBREM_14 diff --git a/src/mainboard/purism/librem_jsl/Kconfig b/src/mainboard/purism/librem_jsl/Kconfig index 2198dd6..5138450 100644 --- a/src/mainboard/purism/librem_jsl/Kconfig +++ b/src/mainboard/purism/librem_jsl/Kconfig @@ -37,7 +37,7 @@ int default 4 -config CBFS_SIZE +config BIOS_SIZE default 0x700000 if BOARD_PURISM_BASEBOARD_LIBREM_JSL config DIMM_MAX diff --git a/src/mainboard/purism/librem_l1um_v2/Kconfig b/src/mainboard/purism/librem_l1um_v2/Kconfig index 946e5a4..7288e7d 100644 --- a/src/mainboard/purism/librem_l1um_v2/Kconfig +++ b/src/mainboard/purism/librem_l1um_v2/Kconfig @@ -35,7 +35,7 @@ config MAINBOARD_PART_NUMBER default "Librem L1UM v2" -config CBFS_SIZE +config BIOS_SIZE default 0x1000000 endif diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 5f3ed06..b546bdd 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -72,7 +72,7 @@ config DIMM_SPD_SIZE default 512 -config CBFS_SIZE +config BIOS_SIZE default 0xe00000 # This platform has limited means to display POST codes diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 3f7aa49..d63c6b0 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -23,7 +23,7 @@ config MAINBOARD_PART_NUMBER default "RK9" -config CBFS_SIZE +config BIOS_SIZE default ROM_SIZE endif # BOARD_RODA_RK9 diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig index bc1c027..44c2d3b 100644 --- a/src/mainboard/siemens/chili/Kconfig +++ b/src/mainboard/siemens/chili/Kconfig @@ -52,7 +52,7 @@ string default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt" -config CBFS_SIZE +config BIOS_SIZE default 0xb00000 config POST_DEVICE diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 2557b48..195f8ac 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -15,7 +15,7 @@ select TPM_MEASURED_BOOT select HAS_RECOVERY_MRC_CACHE -config CBFS_SIZE +config BIOS_SIZE default 0xb4e000 config VBOOT diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 00abfd2b..4776eea 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -17,7 +17,7 @@ config UART_FOR_CONSOLE default 1 -config CBFS_SIZE +config BIOS_SIZE default 0xb4e000 config VBOOT diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 9804553..9b96532 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -18,7 +18,7 @@ select TPM_MEASURED_BOOT select HAS_RECOVERY_MRC_CACHE -config CBFS_SIZE +config BIOS_SIZE default 0xb4e000 config VBOOT diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 212fc90..311b7d8 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -16,7 +16,7 @@ select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 -config CBFS_SIZE +config BIOS_SIZE default 0xb00000 config MAINBOARD_DIR diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 85f815a..7feaa93 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -82,7 +82,7 @@ bool default y -config CBFS_SIZE +config BIOS_SIZE default 0xb00000 config CONSOLE_POST diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index 1499012..540ee12 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -37,7 +37,7 @@ depends on PXE default "8086:10d3" -config CBFS_SIZE +config BIOS_SIZE default 0x400000 #config SUPERMICRO_BOARDID diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig index 089ca7a..f200089 100644 --- a/src/mainboard/system76/addw1/Kconfig +++ b/src/mainboard/system76/addw1/Kconfig @@ -51,7 +51,7 @@ default "addw1" if BOARD_SYSTEM76_ADDW1 default "addw2" if BOARD_SYSTEM76_ADDW2 -config CBFS_SIZE +config BIOS_SIZE default 0xa00000 if BOARD_SYSTEM76_ADDW1 default 0xc00000 diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig index b12c514..9464d7a 100644 --- a/src/mainboard/system76/bonw14/Kconfig +++ b/src/mainboard/system76/bonw14/Kconfig @@ -38,7 +38,7 @@ config MAINBOARD_VERSION default "bonw14" -config CBFS_SIZE +config BIOS_SIZE default 0xc00000 config CONSOLE_POST diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig index 4bb4729..016a1ee 100644 --- a/src/mainboard/system76/cml-u/Kconfig +++ b/src/mainboard/system76/cml-u/Kconfig @@ -54,7 +54,7 @@ default "darp6" if BOARD_SYSTEM76_DARP6 default "lemp9" if BOARD_SYSTEM76_LEMP9 -config CBFS_SIZE +config BIOS_SIZE default 0xc00000 config CONSOLE_POST diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index 09616c9..2766ffa 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -48,7 +48,7 @@ default "gaze14" if BOARD_SYSTEM76_GAZE14 default "gaze15" if BOARD_SYSTEM76_GAZE15 -config CBFS_SIZE +config BIOS_SIZE default 0xa00000 if BOARD_SYSTEM76_GAZE14 default 0xc00000 diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig index c8410f2..738439f 100644 --- a/src/mainboard/system76/kbl-u/Kconfig +++ b/src/mainboard/system76/kbl-u/Kconfig @@ -47,7 +47,7 @@ default "galp3" if BOARD_SYSTEM76_GALP3 default "galp3-b" if BOARD_SYSTEM76_GALP3_B -config CBFS_SIZE +config BIOS_SIZE default 0x600000 config CONSOLE_POST diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig index 91a36f3..153a735 100644 --- a/src/mainboard/system76/oryp5/Kconfig +++ b/src/mainboard/system76/oryp5/Kconfig @@ -41,7 +41,7 @@ string default "oryp5" -config CBFS_SIZE +config BIOS_SIZE default 0xA00000 config CONSOLE_POST diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index b096821..a9e6a6f 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -49,7 +49,7 @@ default "oryp6" if BOARD_SYSTEM76_ORYP6 default "oryp7" if BOARD_SYSTEM76_ORYP7 -config CBFS_SIZE +config BIOS_SIZE default 0xc00000 config CONSOLE_POST diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig index b8cb4fc..8a36865 100644 --- a/src/mainboard/system76/whl-u/Kconfig +++ b/src/mainboard/system76/whl-u/Kconfig @@ -50,7 +50,7 @@ default "galp3-c" if BOARD_SYSTEM76_GALP3_C default "darp5" if BOARD_SYSTEM76_DARP5 -config CBFS_SIZE +config BIOS_SIZE default 0xA00000 config CONSOLE_POST diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fef0d735..b6dec8c 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -17,7 +17,7 @@ config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK -config CBFS_SIZE +config BIOS_SIZE default 0x100000 config VGA_BIOS_ID diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 2bafebf..55a1812 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -19,7 +19,7 @@ # CPU is reset without platform/TPM during romstage select TPM_STARTUP_IGNORE_POSTINIT -config CBFS_SIZE +config BIOS_SIZE default 0x100000 config VGA_BIOS_ID diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 973eed8..4213fca 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -88,7 +88,7 @@ specification. Consider this to be an overclocking option. Handle with care! -config CBFS_SIZE +config BIOS_SIZE default 0x100000 config VGA_BIOS_ID diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 097e111..91afea2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -14,7 +14,7 @@ if NORTHBRIDGE_INTEL_X4X -config CBFS_SIZE +config BIOS_SIZE default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX config VGA_BIOS_ID diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fc94695..178f25c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -382,7 +382,7 @@ hex default 0x1000 -config CBFS_SIZE +config BIOS_SIZE default 0x400000 config PRERAM_CBMEM_CONSOLE_SIZE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 59b09a5..de435b1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -289,7 +289,7 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index ff3c82f..dbda412 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -183,7 +183,7 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config FSP_HEADER_PATH diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 3fd6826..0a6a215 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -182,7 +182,7 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config FSP_HEADER_PATH diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index bc0183d..cc5638b 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -332,7 +332,7 @@ hex default 0x1000 -config CBFS_SIZE +config BIOS_SIZE hex default 0x200000 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index df95e52..a1ed24a 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -314,7 +314,7 @@ hex default 0x1000 -config CBFS_SIZE +config BIOS_SIZE hex default 0x200000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 22017c8..11de077 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -115,7 +115,7 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config DCACHE_RAM_BASE diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 1b04fbc..65b4ac8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -229,7 +229,7 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config CBFS_SIZE +config BIOS_SIZE default 0x200000 config FSP_TYPE_IOT diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 95eda31..af3b460 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -216,7 +216,7 @@ endchoice -config CBFS_SIZE +config BIOS_SIZE default 0x100000 help Reduce CBFS size to give room to the IFD blobs. diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f008889..4e2265e 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -16,6 +16,6 @@ ##VPD_ENTRY## ##HSPHY_FW_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## - COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##BIOS_SIZE## } } diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd index 8f4819e..26648be 100644 --- a/util/cbfstool/default.fmd +++ b/util/cbfstool/default.fmd @@ -15,6 +15,6 @@ FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## - COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##BIOS_SIZE## } } diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 94105ef..4eba494 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1160,7 +1160,7 @@ "\t\t##SPD_CACHE_ENTRY##\n" "\t\t##VPD_ENTRY##\n" "\t\tFMAP@##FMAP_BASE## ##FMAP_SIZE##\n" - "\t\tCOREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##\n" + "\t\tCOREBOOT(CBFS)@##CBFS_BASE## ##BIOS_SIZE##\n" "\t}\n" "}\n"; if (write(layout_fd, ebuf, strlen(ebuf)) < 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I762042fae6357ee368b22a47b8e1168902041675 Gerrit-Change-Number: 86571 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

1 0

[XS] Change in coreboot[main]: util/cbfstool: Place XIP components and FIT at high flash addresses
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Andrey Petrov, Chen, Gang C, Intel coreboot Reviewers, Julius Werner, Ronak Kanabar, Yu-Ping Wu. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86570?usp=email to review the following change. Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses ...................................................................... util/cbfstool: Place XIP components and FIT at high flash addresses By default, CACHE_ROM_SIZE is limited to 16MB, but still covers the whole CBFS. When CBFS spans larger than 16MB, XIP components and FIT might be laid outside the cached region. Place XIP components and FIT as high as possible so that always to maximize the opportunity for them to being cached. Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M Makefile.mk M src/cpu/intel/fit/Makefile.mk M src/drivers/intel/fsp2_0/Makefile.mk M src/security/vboot/Makefile.mk 4 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86570/1 diff --git a/Makefile.mk b/Makefile.mk index bc547de..054ac13 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1371,7 +1371,7 @@ # If CAR does not support execution of code, romstage on x86 is expected to be # xip. ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) -$(CONFIG_CBFS_PREFIX)/romstage-options += --xip +$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -z # For efficient MTRR utilisation use natural alignment for romstage. ifeq ($(CONFIG_SETUP_XIP_CACHE),y) diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk index f405c57..7861859 100644 --- a/src/cpu/intel/fit/Makefile.mk +++ b/src/cpu/intel/fit/Makefile.mk @@ -12,6 +12,7 @@ intel_fit-file := fit_table.c:struct intel_fit-type := intel_fit intel_fit-align := 16 +intel_fit-options := -z $(call add_intermediate, set_fit_ptr, $(IFITTOOL)) @printf " UPDATE-FIT set FIT pointer to table\n" diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk index 18a62e3..cce2cba 100644 --- a/src/drivers/intel/fsp2_0/Makefile.mk +++ b/src/drivers/intel/fsp2_0/Makefile.mk @@ -72,8 +72,8 @@ $(FSP_M_CBFS)-type := fsp $(FSP_M_CBFS_2)-type := fsp ifeq ($(CONFIG_FSP_M_XIP),y) -$(FSP_M_CBFS)-options := --xip $(TXTIBB) -$(FSP_M_CBFS_2)-options := --xip $(TXTIBB) +$(FSP_M_CBFS)-options := --xip $(TXTIBB) -z +$(FSP_M_CBFS_2)-options := --xip $(TXTIBB) -z endif ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZMA),y) $(FSP_M_CBFS)-compression := LZMA diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk index e9b3eb6..f1eb54a 100644 --- a/src/security/vboot/Makefile.mk +++ b/src/security/vboot/Makefile.mk @@ -166,7 +166,7 @@ # If CAR does not support execution of code, verstage on x86 is expected to be # xip. ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) -$(CONFIG_CBFS_PREFIX)/verstage-options += --xip +$(CONFIG_CBFS_PREFIX)/verstage-options += --xip -z endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c Gerrit-Change-Number: 86570 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[M] Change in coreboot[main]: util/cbfstool: Optionally place new components as high as possible
by Shuo Liu (Code Review) 23 Feb '25

23 Feb '25

Attention is currently required from: Chen, Gang C, Jincheng Li. Hello Chen, Gang C, Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86569?usp=email to review the following change. Change subject: util/cbfstool: Optionally place new components as high as possible ...................................................................... util/cbfstool: Optionally place new components as high as possible cbfstool by default places new components as low as possible. Add option -z to place them as high as possible. This useful to put files into cached region when only the highest portion close to 4G boundary is cached. Change-Id: Ida3131694f3e8883424351a68bba6a8da612ae09 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c M util/cbfstool/common.h 4 files changed, 45 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/86569/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3d768b0..cdcf8fa 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1948,21 +1948,24 @@ } static size_t absolute_align(const struct cbfs_image *image, size_t val, - size_t align) + size_t align, bool up) { const size_t region_offset = buffer_offset(&image->buffer); /* To perform alignment on absolute address, take the region offset */ /* of the image into account. */ - return align_up(val + region_offset, align) - region_offset; + size_t aligned = up ? align_up(val + region_offset, align) : + align_down(val + region_offset, align); + return aligned - region_offset; } int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, - size_t page_size, size_t align, size_t metadata_size) + size_t page_size, size_t align, size_t metadata_size, + bool close_to_top) { struct cbfs_file *entry; size_t need_len; - size_t addr, addr_next, addr2, addr3, offset; + size_t addr, addr_next, addr2, addr3, offset, offset2; /* Default values: allow fitting anywhere in ROM. */ if (!page_size) @@ -2007,6 +2010,7 @@ * For stage targets, the address is also used to re-link stage before * being added into CBFS. */ + offset = (uint32_t)-1; for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { @@ -2021,7 +2025,20 @@ if (addr_next - addr < need_len) continue; - offset = absolute_align(image, addr + metadata_size, align); + if (close_to_top) { + offset2 = absolute_align(image, addr_next - size, align, false); + if (is_in_same_page(offset2, size, page_size) && + is_in_range(addr, addr_next, metadata_size, offset2, size)) { + offset = offset2; + } + /* + * By now, extra page alignment is not needed. + * TODO: add page alignment based on needs. + */ + continue; + } + + offset = absolute_align(image, addr + metadata_size, align, true); if (is_in_same_page(offset, size, page_size) && is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1).\n"); @@ -2029,7 +2046,7 @@ } addr2 = align_up(addr, page_size); - offset = absolute_align(image, addr2, align); + offset = absolute_align(image, addr2, align, true); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2).\n"); return offset; @@ -2039,11 +2056,15 @@ * definitely provide the space for header. */ assert(page_size >= metadata_size); addr3 = addr2 + page_size; - offset = absolute_align(image, addr3, align); + offset = absolute_align(image, addr3, align, true); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3).\n"); return offset; } } + + if (close_to_top && (offset != (uint32_t)-1)) + return offset; + return -1; } diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 85ba023..8f00d8a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -118,7 +118,8 @@ * "align" specifies starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, - size_t page_size, size_t align, size_t metadata_size); + size_t page_size, size_t align, size_t metadata_size, + bool close_to_top); /* Callback function used by cbfs_legacy_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 9acfd26..bde61b5 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -108,6 +108,7 @@ */ uint32_t ext_win_base; uint32_t ext_win_size; + bool close_to_top; } param = { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, @@ -116,6 +117,7 @@ .headeroffset = HEADER_OFFSET_UNKNOWN, .region_name = SECTION_NAME_PRIMARY_CBFS, .u64val = -1, + .close_to_top = false, }; /* @@ -612,7 +614,7 @@ metadata_size += cbfs_file_attr_hash_size(param.hash); int32_t address = cbfs_locate_entry(&image, data_size, param.pagesize, - param.alignment, metadata_size); + param.alignment, metadata_size, param.close_to_top); if (address < 0) { ERROR("'%s'(%u + %zu) can't fit in CBFS for page-size %#x, align %#x.\n", @@ -1801,12 +1803,12 @@ } static const struct command commands[] = { - {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gh?", cbfs_add, true, true}, + {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gzh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:p:vA:gh?", cbfs_add_flat_binary, true, true}, {"add-payload", "H:r:f:n:c:b:a:C:I:p:vA:gh?", cbfs_add_payload, true, true}, - {"add-stage", "a:H:r:f:n:t:c:b:P:QS:p:yvA:gh?", cbfs_add_stage, + {"add-stage", "a:H:r:f:n:t:c:b:P:QS:p:yvA:gzh?", cbfs_add_stage, true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?j:", cbfs_add_master_header, true, true}, @@ -2304,6 +2306,9 @@ case 'U': param.unprocessed = true; break; + case 'z': + param.close_to_top = true; + break; case LONGOPT_IBB: param.ibb = true; break; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 88d5238..50e4ceb 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -30,6 +30,13 @@ return value; } +static inline uint32_t align_down(uint32_t value, uint32_t align) +{ + if (value % align) + value -= (value % align); + return value; +} + /* Buffer and file I/O */ struct buffer { char *name; -- To view, visit https://review.coreboot.org/c/coreboot/+/86569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3131694f3e8883424351a68bba6a8da612ae09 Gerrit-Change-Number: 86569 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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coreboot-gerrit February 2025