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Change subject: soc/amd/glinda/cpu: Update smbios parameters
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85637/comment/e081a709_028978f6?us… :
PS3, Line 9: Update smbios parameters for cache type, operation mode & error
: correction type.
could you add the source of your information?
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Change subject: soc/amd/cpu: smbios: update external clock
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85636/comment/d53012bd_aff269a2?us… :
PS3, Line 9: Se
could you add the source of this information?
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Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME
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Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86422/comment/17ddda96_c1539547?us… :
PS1, Line 10: Also trigger a fail-safe board
: reset if the system resumes from S3.
> Agree, System is not expected to reach S3 state. The fail safe code has been removed.
Thank you.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86552/comment/5fe0a6fa_63b667ed?us… :
PS3, Line 9: Adjust thermal trip point parameters so the thermal can trigger the interrupt at the expected trip point.
Please re-flow for 72 characters per line.
https://review.coreboot.org/c/coreboot/+/86552/comment/7a581a6c_e370bd04?us… :
PS3, Line 10:
Why are the new values correct?
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Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86551/comment/f7153724_bb10fddf?us… :
PS2, Line 10: after the system suspends and resumes
Does this effect resume time?
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Change subject: mb/cwwk/adl: Various device tree fixes
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Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86260/comment/8beba4b3_53c19815?us… :
PS2, Line 7: Various device tree fixes
Please make it a statement.
https://review.coreboot.org/c/coreboot/+/86260/comment/0677d834_140ff207?us… :
PS2, Line 9: - Set pmc_gpe0_dw{0-3} to resolve a warning
Please paste the warning.
https://review.coreboot.org/c/coreboot/+/86260/comment/0bd8799e_ca36df71?us… :
PS2, Line 10: vendor firmware
Please add the version.
https://review.coreboot.org/c/coreboot/+/86260/comment/81330df7_e4d2982e?us… :
PS2, Line 9: - Set pmc_gpe0_dw{0-3} to resolve a warning
: - Set CLKREQ# based on register value from vendor firmware
: - Enable ITE environment controller
Listing changes is always an indicator to make a separate commit per item. ;-)
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Change subject: mb/google/nissa/var/meliks: Add VBT data file
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86508/comment/3ecf5f4f_26c1baa6?us… :
PS1, Line 11: The VBT
: file is copied from chrome-internal:8030469
Unfortunately, I am denied access. Please add, who created the file.
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Change subject: device/dram/ddr5.c: Add 7500 MT/s support
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86543/comment/6a9da342_24eeb94b?us… :
PS1, Line 7: .c
Not necessary in the prefix.
https://review.coreboot.org/c/coreboot/+/86543/comment/b2283b40_20f01b86?us… :
PS1, Line 8:
Any test?
File src/device/dram/ddr5.c:
https://review.coreboot.org/c/coreboot/+/86543/comment/6ae9228d_7420dd69?us… :
PS1, Line 112: 7500] = {
: .min_clock_mhz = 3201,
: .max_clock_mhz = 3750,
Unrelated: I wonder, if min and max clock could be calculated.
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Change subject: google/fatcat/var/fatcat: Update GSPI0 CS pin
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Patch Set 5: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86480/comment/0a29e902_822f4968?us… :
PS5, Line 9: TouchPad
touchpad
https://review.coreboot.org/c/coreboot/+/86480/comment/ead27ea7_ecffc442?us… :
PS5, Line 11: This commit moves the FPS GSPI0-CS signal to GPP_E17, which is an GSPI-0 CS alternative option
Please wrap the line, and add a dot/period at the end.
https://review.coreboot.org/c/coreboot/+/86480/comment/ecfa366a_2f4a0aa9?us… :
PS5, Line 12:
Please document the schematic version.
https://review.coreboot.org/c/coreboot/+/86480/comment/6ac751ad_e9dfbc7a?us… :
PS5, Line 14: TEST=build fatcat
No run-time test?
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Change subject: util/cbmem: Use uintN_t instead of uN int types
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86556/comment/d07cc31a_9d16a9f8?us… :
PS1, Line 10: alternatives of uint8_t. There is no need to unnecessarily compress code
Maybe "alternatives of uint{8,16,32,64}_t"?
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