coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: mb/google/brya: Do not select HAVE_ACPI_RESUME
by Matt DeVillier (Code Review) 21 Feb '25

21 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86422?usp=email ) Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME ...................................................................... mb/google/brya: Do not select HAVE_ACPI_RESUME This patch removes the HAVE_ACPI_RESUME config option from the Google Brya mainboard configuration. The Intel Alder Lake SoC does not support S3 (ACPI sleep state) entry/exit, and attempting S3 validation could lead to abnormal platform behavior. This change ensures that `_S3` is not listed as a valid wake source in the DSDT (Differentiated System Description Table) after booting to the OS. BUG=b:337274309 TEST=Boot verfied google/trulo. TEST=Veified that the _S3 name variable is not present in the DSDT ASL. Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86422 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index aac2393..1ca5094 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -28,7 +28,6 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select I2C_TPM -- To view, visit https://review.coreboot.org/c/coreboot/+/86422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Gerrit-Change-Number: 86422 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/dirks: Update ddi_ports_config
by Matt DeVillier (Code Review) 21 Feb '25

21 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86537?usp=email ) Change subject: mb/google/nissa/var/dirks: Update ddi_ports_config ...................................................................... mb/google/nissa/var/dirks: Update ddi_ports_config Update ddi_ports_config to match VBT's settings. DDI_PORT_A = HDMI DDI_PORT_B = HDMI DDI_PORT_1 = Type-C DP BUG=b:389391653 TEST=emerge-nissa coreboot Change-Id: I67e9fcf4a3caa303ec8d873507a7533389c095ae Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86537 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dirks/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: David Wu: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb index bc1c186..a953b4c 100644 --- a/src/mainboard/google/brya/variants/dirks/overridetree.cb +++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb @@ -87,6 +87,16 @@ # Enable the Cnvi BT Audio Offload register "cnvi_bt_audio_offload" = "1" + # Disable eDP on DDI portA + register "ddi_portA_config" = "0" + + # Enable HPD and DDC for DDI port A + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/86537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67e9fcf4a3caa303ec8d873507a7533389c095ae Gerrit-Change-Number: 86537 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
by Matt DeVillier (Code Review) 21 Feb '25

21 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85634?usp=email ) Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver ...................................................................... drivers/amd/opensil/memmap.c: Factor out common memmap code to driver Refactor the vendorcode openSIL memory map code and move all common calls that do not require any openSIL headers to the driver. Improve the legibility of the logic to return memory hole type string. Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85634 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/memmap.c M src/drivers/amd/opensil/opensil.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/phoenix/memmap.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/ramstage.c 8 files changed, 124 insertions(+), 90 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk index 9837718..6ed46d1 100644 --- a/src/drivers/amd/opensil/Makefile.mk +++ b/src/drivers/amd/opensil/Makefile.mk @@ -8,5 +8,6 @@ ramstage-y += acpi.c ramstage-y += ramstage.c +ramstage-y += memmap.c endif diff --git a/src/drivers/amd/opensil/memmap.c b/src/drivers/amd/opensil/memmap.c new file mode 100644 index 0000000..9b80a88 --- /dev/null +++ b/src/drivers/amd/opensil/memmap.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <cbmem.h> +#include <cpu/amd/mtrr.h> +#include <string.h> +#include <vendorcode/amd/opensil/opensil.h> + +#include "opensil.h" + +/* + * This structure definition must align exactly with the MEMORY_HOLE_TYPES structure + * defined in openSIL to ensure accurate casting. + */ +typedef struct { + uint64_t base; + uint64_t size; + uint32_t type; + uint32_t reserved; +} HOLE_INFO; + +/* This assumes holes are allocated */ +void amd_opensil_add_memmap(struct device *dev, unsigned long *idx) +{ + uint64_t top_of_mem = 0; + uint32_t n_holes = 0; + void *hole_info = NULL; + + /* Account for UMA and TSEG */ + const uint32_t mem_usable = cbmem_top(); + const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB); + if (mem_usable != top_mem) + reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); + + /* Holes in upper DRAM */ + /* This assumes all the holes in upper DRAM are continuous */ + opensil_get_hole_info(&n_holes, &top_of_mem, &hole_info); + if (hole_info == NULL) + return; + + /* Check if we're done */ + if (top_of_mem <= 4ULL * GiB) + return; + + HOLE_INFO *holes = (HOLE_INFO *)hole_info; + + uint64_t lowest_upper_hole_base = top_of_mem; + uint64_t highest_upper_hole_end = 4ULL * GiB; + for (size_t hole = 0; hole < n_holes; hole++) { + if (!strcmp(opensil_get_hole_info_type(holes[hole].type), "MMIO")) + continue; + if (holes[hole].base < 4ULL * GiB) + continue; + lowest_upper_hole_base = MIN(lowest_upper_hole_base, holes[hole].base); + highest_upper_hole_end = MAX(highest_upper_hole_end, holes[hole].base + holes[hole].size); + if (!strcmp(opensil_get_hole_info_type(holes[hole].type), "UMA")) + mmio_range(dev, (*idx)++, holes[hole].base, holes[hole].size); + else + reserved_ram_range(dev, (*idx)++, holes[hole].base, holes[hole].size); + } + + ram_from_to(dev, (*idx)++, 4ULL * GiB, lowest_upper_hole_base); + + if (top_of_mem > highest_upper_hole_end) + ram_from_to(dev, (*idx)++, highest_upper_hole_end, top_of_mem); +} + +static void print_memory_holes(void *unused) +{ + uint64_t top_of_mem = 0; + uint32_t n_holes = 0; + void *hole_info = NULL; + + opensil_get_hole_info(&n_holes, &top_of_mem, &hole_info); + if (hole_info == NULL) + return; + + HOLE_INFO *holes = (HOLE_INFO *)hole_info; + + printk(BIOS_DEBUG, "APOB: top of memory 0x%016llx\n", top_of_mem); + printk(BIOS_DEBUG, "The following holes are reported in APOB\n"); + for (size_t hole = 0; hole < n_holes; hole++) { + printk(BIOS_DEBUG, " Base: 0x%016llx, Size: 0x%016llx, Type: %02d:%s\n", + holes[hole].base, holes[hole].size, holes[hole].type, + opensil_get_hole_info_type(holes[hole].type)); + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL); diff --git a/src/drivers/amd/opensil/opensil.h b/src/drivers/amd/opensil/opensil.h index f2bcd6b..e6efbdc 100644 --- a/src/drivers/amd/opensil/opensil.h +++ b/src/drivers/amd/opensil/opensil.h @@ -4,11 +4,14 @@ #define OPENSIL_DRIVER_H #include <acpi/acpi.h> +#include <device/device.h> /* Set up openSIL env and call TP1 */ void amd_opensil_silicon_init(void); /* Set global and per-device MPIO configurations */ void configure_mpio(void); +/* Add the memory map to dev, starting at index idx, returns last use idx */ +void amd_opensil_add_memmap(struct device *dev, unsigned long *idx); /* Fill in FADT from openSIL */ void amd_opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 65b1395..d45d317 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -9,17 +9,16 @@ #include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> +#include <drivers/amd/opensil/opensil.h> #include <types.h> -#include <vendorcode/amd/opensil/opensil.h> - #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0 void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { read_lower_soc_memmap_resources(domain, idx); - add_opensil_memmap(domain, idx); + amd_opensil_add_memmap(domain, idx); } static void genoa_domain_set_resources(struct device *domain) diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c index d29dcbe..1b45b9c 100644 --- a/src/soc/amd/phoenix/memmap.c +++ b/src/soc/amd/phoenix/memmap.c @@ -4,8 +4,8 @@ #include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <device/device.h> +#include <drivers/amd/opensil/opensil.h> #include <stdint.h> -#include <vendorcode/amd/opensil/opensil.h> /* * +--------------------------------+ @@ -69,5 +69,5 @@ if (CONFIG(PLATFORM_USES_FSP2_0)) read_fsp_resources(dev, idx); else - add_opensil_memmap(dev, idx); + amd_opensil_add_memmap(dev, idx); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index ece9877..eed1be7 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -1,20 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> -#include <stdint.h> -#include <stdbool.h> #include <SilCommon.h> #include <Sil-api.h> // needed above ApobCmn.h #include <ApobCmn.h> -#include <device/device.h> #include <xPRF-api.h> -#include <cpu/amd/mtrr.h> -#include <cbmem.h> -#include <amdblocks/memmap.h> #include "../opensil.h" -static const char *hole_info_type(MEMORY_HOLE_TYPES type) +_Static_assert(sizeof(uint32_t) == sizeof(((MEMORY_HOLE_DESCRIPTOR){0}).Type), + "Unexpected size of MEMORY_HOLE_TYPES in the MEMORY_HOLE_DESCRIPTOR " + "struct which doesn't match the code in drivers/amd/opensil/memmap.c"); + +const char *opensil_get_hole_info_type(uint32_t type) { const struct hole_type { MEMORY_HOLE_TYPES type; @@ -40,85 +37,21 @@ }; int i; + MEMORY_HOLE_TYPES enum_type = (MEMORY_HOLE_TYPES)type; // Cast int to enum for (i = 0; i < ARRAY_SIZE(types); i++) - if (type == types[i].type) - break; - if (i == ARRAY_SIZE(types)) - return "Unknown type"; - return types[i].string; + if (enum_type == types[i].type) + return types[i].string; + return "Unknown type"; } -static uint64_t top_of_mem; -static uint32_t n_holes; -static MEMORY_HOLE_DESCRIPTOR *hole_info; - -static void get_hole_info(void) +void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info) { - static bool done; - if (done) - return; - SIL_STATUS status = xPrfGetSystemMemoryMap(&n_holes, &top_of_mem, (void **)&hole_info); + SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info); SIL_STATUS_report("xPrfGetSystemMemoryMap", status); // Make sure hole_info does not get initialized to something odd by xPRF on failure - if (status != SilPass) - hole_info = NULL; - done = true; -} - - -static void print_memory_holes(void *unused) -{ - get_hole_info(); - if (hole_info == NULL) - return; - - printk(BIOS_DEBUG, "APOB: top of memory 0x%016llx\n", top_of_mem); - printk(BIOS_DEBUG, "The following holes are reported in APOB\n"); - for (int hole = 0; hole < n_holes; hole++) { - printk(BIOS_DEBUG, " Base: 0x%016llx, Size: 0x%016llx, Type: %02d:%s\n", - hole_info[hole].Base, hole_info[hole].Size, hole_info[hole].Type, - hole_info_type(hole_info[hole].Type)); + if (status != SilPass) { + *hole_info = NULL; + *n_holes = 0; + *top_of_mem = 0; } } - -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL); - -// This assumes holes are allocated -void add_opensil_memmap(struct device *dev, unsigned long *idx) -{ - // Account for UMA and TSEG - const uint32_t mem_usable = cbmem_top(); - const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB); - if (mem_usable != top_mem) - reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); - - // Check if we're done - if (top_of_mem <= 4ULL * GiB) - return; - - // Holes in upper DRAM - // This assumes all the holes in upper DRAM are continuous - get_hole_info(); - if (hole_info == NULL) - return; - uint64_t lowest_upper_hole_base = top_of_mem; - uint64_t highest_upper_hole_end = 4ULL * GiB; - for (int hole = 0; hole < n_holes; hole++) { - if (hole_info[hole].Type == MMIO) - continue; - if (hole_info[hole].Base < 4ULL * GiB) - continue; - lowest_upper_hole_base = MIN(lowest_upper_hole_base, hole_info[hole].Base); - highest_upper_hole_end = MAX(highest_upper_hole_end, hole_info[hole].Base + hole_info[hole].Size); - if (hole_info[hole].Type == UMA) - mmio_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); - else - reserved_ram_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); - } - - ram_from_to(dev, (*idx)++, 4ULL * GiB, lowest_upper_hole_base); - - // Do we need this? - if (top_of_mem > highest_upper_hole_end) - ram_from_to(dev, (*idx)++, highest_upper_hole_end, top_of_mem); -} diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h index c84a180..3ed8960 100644 --- a/src/vendorcode/amd/opensil/opensil.h +++ b/src/vendorcode/amd/opensil/opensil.h @@ -8,8 +8,9 @@ #include <types.h> void SIL_STATUS_report(const char *function, const int status); -// Add the memory map to dev, starting at index idx, returns last use idx -void add_opensil_memmap(struct device *dev, unsigned long *idx); + +void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info); +const char *opensil_get_hole_info_type(uint32_t type); void opensil_fill_fadt(acpi_fadt_t *fadt); unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp); diff --git a/src/vendorcode/amd/opensil/stub/ramstage.c b/src/vendorcode/amd/opensil/stub/ramstage.c index 5da6134..d2e3d6a 100644 --- a/src/vendorcode/amd/opensil/stub/ramstage.c +++ b/src/vendorcode/amd/opensil/stub/ramstage.c @@ -5,9 +5,17 @@ #include "../opensil.h" -void add_opensil_memmap(struct device *dev, unsigned long *idx) +void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info) +{ + *n_holes = 0; + *top_of_mem = 0xc0000000; + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +const char *opensil_get_hole_info_type(uint32_t type) { printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); + return ""; } void opensil_fill_fadt(acpi_fadt_t *fadt) -- To view, visit https://review.coreboot.org/c/coreboot/+/85634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Gerrit-Change-Number: 85634 Gerrit-PatchSet: 24 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable CNVi wifi core
by Matt DeVillier (Code Review) 21 Feb '25

21 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86549?usp=email ) Change subject: mb/google/fatcat/var/felino: Enable CNVi wifi core ...................................................................... mb/google/fatcat/var/felino: Enable CNVi wifi core Enable CNVi wifi core for felino. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: Ib5a98dc481b0c64612ffd50242262714f114b5b7 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86549 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/felino/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index d401ed2..62b4160 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -28,6 +28,9 @@ .tdp_pl2_override = 25, }" + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 # USB HUB (USB2 Camera) -- To view, visit https://review.coreboot.org/c/coreboot/+/86549?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5a98dc481b0c64612ffd50242262714f114b5b7 Gerrit-Change-Number: 86549 Gerrit-PatchSet: 2 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable to...
by Matt DeVillier (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Tongtong Pan. Matt DeVillier has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/86542?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for enable touchpad ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/felino/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86542/comment/5e315c1a_a1b68809?us… : PS1, Line 237: register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)" needs tabs vs spaces here and 3 lines below -- To view, visit https://review.coreboot.org/c/coreboot/+/86542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135 Gerrit-Change-Number: 86542 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 14:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Kapil Porwal (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86555?usp=email to look at the new patch set (#2). Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... mb/google/trulo: Update GPIO wake pins List of changes - 1. Lock GPIO GPP_F17 pad configuration. 2. Make GPP_B3 IRQ only pin. 3. Remove redundant GPE option from touchpad device. BUG=b:397905085 TEST=Verified wake from S0ix using touchpad and charger. Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c M src/mainboard/google/brya/variants/trulo/overridetree.cb 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/86555/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Kapil Porwal (Code Review) 21 Feb '25

21 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86555?usp=email ) Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/trulo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86555/comment/43d555cb_fe655681?us… : PS1, Line 457: WAKE Only marking this IRQ as wake capable, making a difference. -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Feb 2025 14:03:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/trulo: Update GPIO wake pins
by Kapil Porwal (Code Review) 21 Feb '25

21 Feb '25

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86555?usp=email ) Change subject: mb/google/trulo: Update GPIO wake pins ...................................................................... mb/google/trulo: Update GPIO wake pins List of changes - 1. Lock GPIO GPP_F17 pad configuration. 2. Make GPP_B3 IRQ only pin. 3. Remove redundant GPE option from touchpad device. BUG=b:397905085 TEST=Verified wake from S0ix using touchpad and charger. Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c M src/mainboard/google/brya/variants/trulo/overridetree.cb 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/86555/1 diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c index c813154..cfb3aed 100644 --- a/src/mainboard/google/brya/variants/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -58,7 +58,7 @@ /* B2 : NC */ PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> EC_TP_INT */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT), + PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT), /* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */ PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : GPP_B5 ==> ISH_I2C0_SCL */ @@ -242,7 +242,7 @@ /* F16 : NC */ PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : Not available */ diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index cdc777b..4c21173 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -455,7 +455,6 @@ register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW1_03" register "detect" = "1" device i2c 15 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4 Gerrit-Change-Number: 86555 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: amdfwtool: Add combo_index into context
by Felix Held (Code Review) 21 Feb '25

21 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85590?usp=email ) Change subject: amdfwtool: Add combo_index into context ...................................................................... amdfwtool: Add combo_index into context We need to know how many combo entries have been processed. It will be checked in functions in later change. Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85590 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 14 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 89aff6a..7b5e70e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1628,7 +1628,6 @@ int main(int argc, char **argv) { int retval = 0; - int combo_index = 0; int targetfd; context ctx = { 0 }; uint32_t romsig_offset; @@ -1719,17 +1718,17 @@ ctx.bhd_combo_dir = new_combo_dir(&ctx, BHD2_COOKIE); } - combo_index = 0; + ctx.combo_index = 0; if (cb_config.config) cb_config.combo_config[0] = cb_config.config; do { if (cb_config.use_combo && cb_config.debug) - printf("Processing %dth combo entry\n", combo_index); + printf("Processing %dth combo entry\n", ctx.combo_index); /* The pspdir level 1 is special. For new combo layout, all the combo entries share one pspdir L1. It should not be cleared at each iteration. */ - if (!cb_config.combo_new_rab || combo_index == 0) { + if (!cb_config.combo_new_rab || ctx.combo_index == 0) { ctx.pspdir = NULL; ctx.pspdir_bak = NULL; } @@ -1746,14 +1745,14 @@ * and make it clear this will not affect non-combo * case. */ - if (cb_config.use_combo && combo_index > 0) { + if (cb_config.use_combo && ctx.combo_index > 0) { /* Restore the table as clean data. */ memcpy(amd_psp_fw_table, ctx.amd_psp_fw_table_clean, sizeof(amd_psp_fw_table)); memcpy(amd_bios_table, ctx.amd_bios_table_clean, sizeof(amd_bios_table)); - assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); - open_process_config(cb_config.combo_config[combo_index], &cb_config); + assert_fw_entry(ctx.combo_index, MAX_COMBO_ENTRIES, &ctx); + open_process_config(cb_config.combo_config[ctx.combo_index], &cb_config); /* In most cases, the address modes are same. */ if (cb_config.need_ish) @@ -1763,7 +1762,7 @@ else ctx.address_mode = AMD_ADDR_PHYSICAL; - register_apcb_combo(&cb_config, combo_index, &ctx); + register_apcb_combo(&cb_config, ctx.combo_index, &ctx); } if (cb_config.multi_level) { @@ -1781,7 +1780,7 @@ } integrate_bios_levels(&ctx, &cb_config); } - if (!cb_config.combo_new_rab || combo_index == 0) + if (!cb_config.combo_new_rab || ctx.combo_index == 0) integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); integrate_psp_levels(&ctx, &cb_config); @@ -1791,13 +1790,13 @@ amd_psp_fw_table, PSP_COOKIE, &cb_config); } - if (!cb_config.use_combo || (cb_config.combo_new_rab && combo_index == 0)) { + if (!cb_config.use_combo || (cb_config.combo_new_rab && ctx.combo_index == 0)) { /* For new combo layout, there is only 1 PSP level 1 directory. */ fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config); fill_psp_bak_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir_bak, &ctx, &cb_config); } else if (cb_config.use_combo && !cb_config.combo_new_rab) { fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.psp_combo_dir, &ctx, &cb_config); - add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config); + add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, ctx.combo_index, &ctx, &cb_config); } if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) { @@ -1822,13 +1821,13 @@ */ fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.bhd_combo_dir, &ctx, &cb_config); - add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, combo_index, &ctx, &cb_config); + add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, ctx.combo_index, &ctx, &cb_config); } } if (cb_config.debug) dump_image_addresses(&ctx); - } while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES && - cb_config.combo_config[combo_index] != NULL); + } while (cb_config.use_combo && ++ctx.combo_index < MAX_COMBO_ENTRIES && + cb_config.combo_config[ctx.combo_index] != NULL); targetfd = open(cb_config.output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index f87fbf5..3c773f7 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -447,6 +447,7 @@ uint32_t current; /* pointer within flash & proxy buffer */ uint32_t current_pointer_saved; uint32_t current_table; + uint32_t combo_index; void *amd_psp_fw_table_clean; void *amd_bios_table_clean; struct _combo_apcb { -- To view, visit https://review.coreboot.org/c/coreboot/+/85590?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8 Gerrit-Change-Number: 85590 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: amdfwtool: Merge all the steps for A/B recovery into one branch
by Felix Held (Code Review) 21 Feb '25

21 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84531?usp=email ) Change subject: amdfwtool: Merge all the steps for A/B recovery into one branch ...................................................................... amdfwtool: Merge all the steps for A/B recovery into one branch Clean up the code to make it more logical. This is for later changes to reorder the PSP Level 1, Level 2, ISH and BIOS tables. TEST=Identical test on all AMD platform Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84531 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 19 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 0de0475..89aff6a 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1770,34 +1770,21 @@ /* Do 2nd PSP directory followed by 1st */ integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); - if (cb_config.recovery_ab) + if (cb_config.recovery_ab) { integrate_bios_firmwares(&ctx, amd_bios_table, BHDL2_COOKIE, &cb_config); - - if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { - /* Create a copy of PSP Directory 2 in the backup slot B. - Related biosdir2_b copy will be created later. */ - integrate_psp_firmwares(&ctx, + if (!cb_config.recovery_ab_single_copy) { + integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); - integrate_bios_firmwares(&ctx, + integrate_bios_firmwares(&ctx, amd_bios_table, BHDL2_COOKIE, &cb_config); - } else { - /* - * Either the platform is using only - * one slot or B is same as above - * directories for A. Skip creating - * pspdir2_b here to save flash space. - * Related biosdir2_b will be skipped - * automatically. - */ - ctx.pspdir2_b = NULL; /* More explicitly */ + } + integrate_bios_levels(&ctx, &cb_config); } if (!cb_config.combo_new_rab || combo_index == 0) integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); integrate_psp_levels(&ctx, &cb_config); - if (cb_config.recovery_ab) - integrate_bios_levels(&ctx, &cb_config); } else { /* flat: PSP 1 cookie and no pointer to 2nd table */ integrate_psp_firmwares(&ctx, -- To view, visit https://review.coreboot.org/c/coreboot/+/84531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Gerrit-Change-Number: 84531 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>

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