coreboot-gerrit February 2025

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[M] Change in coreboot[main]: mb/google/nissa/var/meliks: Update memory DQ/DQS map
by Matt DeVillier (Code Review) 25 Feb '25

25 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86376?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/meliks: Update memory DQ/DQS map ...................................................................... mb/google/nissa/var/meliks: Update memory DQ/DQS map Update memory DQ/DQS map configuration by following schematics. BUG=b:394359785 TEST=Build coreboot and verified booting to depthcharge Change-Id: Iae3f2c65b4d1004d1d9ebf76b099fc7f50e8365f Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86376 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- A src/mainboard/google/brya/variants/meliks/Makefile.mk A src/mainboard/google/brya/variants/meliks/memory.c 2 files changed, 99 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk new file mode 100644 index 0000000..c44e4f0 --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/meliks/memory.c b/src/mainboard/google/brya/variants/meliks/memory.c new file mode 100644 index 0000000..d7f73fb --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/memory.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> +#include <boardid.h> + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 15, 10, 8, 11, 14, 13, 9, 12 }, + .dq1 = { 3, 1, 2, 0, 7, 5, 4, 6 }, + }, + .ddr1 = { + .dq0 = { 7, 0, 3, 2, 1, 4, 6, 5 }, + .dq1 = { 12, 9, 8, 11, 10, 13, 15, 14 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 15, 10, 8, 11, 14, 13, 9, 12 }, + .dq1 = { 3, 1, 2, 0, 7, 5, 4, 6 }, + }, + .ddr5 = { + .dq0 = { 7, 0, 3, 2, 1, 4, 6, 5 }, + .dq1 = { 12, 9, 8, 11, 10, 13, 15, 14 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + if (board_id() == BOARD_ID_UNKNOWN) + return 0; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae3f2c65b4d1004d1d9ebf76b099fc7f50e8365f Gerrit-Change-Number: 86376 Gerrit-PatchSet: 4 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/{byte_adl,starlite_adl}: Enable RTD3 for CNVi
by Matt DeVillier (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86428?usp=email ) Change subject: mb/starlabs/{byte_adl,starlite_adl}: Enable RTD3 for CNVi ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86428?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib172230f2c9e926870e35f040ce1b80628561863 Gerrit-Change-Number: 86428 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 25 Feb 2025 20:33:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: driver/usb/intel_bluetooth: Add PS0 and PS3 methods
by Matt DeVillier (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86507?usp=email ) Change subject: driver/usb/intel_bluetooth: Add PS0 and PS3 methods ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32 Gerrit-Change-Number: 86507 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 25 Feb 2025 20:33:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Naresh Solanki (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Paul Menzel. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/e4184592_4d6f423a?us… : PS4, Line 41: __fls(info->num_cores_shared-1); > What Max suggests is using `log2()` since that's what the spec says. […] info->num_cores_shared will be minimal 1. Check line 35 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 20:28:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[L] Change in coreboot[main]: mb/asus: Add SABERTOOTH P67
by Riku Viitanen (Code Review) 25 Feb '25

25 Feb '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86484?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus: Add SABERTOOTH P67 ...................................................................... mb/asus: Add SABERTOOTH P67 New board port based on autoport. One of the PCIe ports is muxed between the slot and USB 3.0 front panel header. CMOS option is implemented to select which one to connect. It defaults to autodetect, which selects the slot if a card is present (presence detect pin is wired to a GPIO but it is ignored by vendor firmware, which only has the manual toggle). There is an additional ASUS specific coprocessor on board: a KB3720QF "TPU" which has an external 64KiB SPI flash near it for its firmware. On vendor firmware, it facilitates automatic overclocking and presumably some power/voltage management features, but it seems like we don't need to do anything with it at least to just boot to coreboot. It is connected to LPC and SMBus among other things. Tested: - Native raminit, i5-2500K - SeaBIOS 1.16.3 booting to Void Linux (6.12.16) - dGPU graphics - All PCIe slots - PCI slot - PCIEX1_2 / USB3_34 muxing - All SATA ports work in SeaBIOS - All rear USB ports - Ethernet - Serial - S3 resume - PS/2 keyboard OR mouse (splitter cables cant't work) - Rear line out jack - me_cleaner Untested: - eSATA - All USB headers - Firewire (just confirmed the controller shows in lspci) - CPU_LED (gpio48) Not working: - MemOK button (connected to TPU) - DRAM_LED (gpio39: on vendor FW it stays lit if there's RAM problems) - VGA_LED (gpio38: same but VGA) - BOOT_DEVICE_LED (gpio22) Change-Id: If643a9ceb944ba2a2c552202b56829b0a0c87925 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asus/sabertooth_p67/Kconfig A src/mainboard/asus/sabertooth_p67/Kconfig.name A src/mainboard/asus/sabertooth_p67/Makefile.mk A src/mainboard/asus/sabertooth_p67/acpi/ec.asl A src/mainboard/asus/sabertooth_p67/acpi/platform.asl A src/mainboard/asus/sabertooth_p67/acpi/superio.asl A src/mainboard/asus/sabertooth_p67/board_info.txt A src/mainboard/asus/sabertooth_p67/cmos.default A src/mainboard/asus/sabertooth_p67/cmos.layout A src/mainboard/asus/sabertooth_p67/devicetree.cb A src/mainboard/asus/sabertooth_p67/dsdt.asl A src/mainboard/asus/sabertooth_p67/early_init.c A src/mainboard/asus/sabertooth_p67/gpio.c A src/mainboard/asus/sabertooth_p67/hda_verb.c A src/mainboard/asus/sabertooth_p67/mainboard.c 15 files changed, 576 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86484/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86484?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If643a9ceb944ba2a2c552202b56829b0a0c87925 Gerrit-Change-Number: 86484 Gerrit-PatchSet: 7 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asus: Add SABERTOOTH P67
by Riku Viitanen (Code Review) 25 Feb '25

25 Feb '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86484?usp=email to look at the new patch set (#6). Change subject: mb/asus: Add SABERTOOTH P67 ...................................................................... mb/asus: Add SABERTOOTH P67 New board port based on autoport. One of the PCIe ports is muxed between the slot and USB 3.0 front panel header. CMOS option is implemented to select which one to connect. It defaults to autodetect, which selects the slot if a card is present (presence detect pin is wired to a GPIO but it is ignored by vendor firmware, which only has the manual toggle). There is an additional ASUS specific coprocessor on board: a KB3720QF "TPU" which has an external 64KiB SPI flash near it for its firmware. On vendor firmware, it facilitates automatic overclocking and presumably some power/voltage management features, but it seems like we don't need to do anything with it at least to just boot to coreboot. It is connected to LPC and SMBus among other things. Tested: - Native raminit, i5-2500K - SeaBIOS 1.16.3 booting to Void Linux (6.12.16) - dGPU graphics - All PCIe slots - PCI slot - PCIEX1_2 / USB3_34 muxing - All SATA ports work in SeaBIOS - All rear USB ports - Ethernet - Serial - S3 resume - PS/2 keyboard OR mouse (splitter cables cant't work) - Rear line out jack - me_cleaner Untested: - eSATA - All USB headers - Firewire (just confirmed the controller shows in lspci) - CPU_LED (gpio48) Not working: - MemOK button (connected to TPU) - DRAM_LED (gpio39: on vendor FW it stays lit if there's RAM problems) - VGA_LED (gpio38: same but VGA) - BOOT_DEVICE_LED (gpio22) Change-Id: If643a9ceb944ba2a2c552202b56829b0a0c87925 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asus/sabertooth_p67/Kconfig A src/mainboard/asus/sabertooth_p67/Kconfig.name A src/mainboard/asus/sabertooth_p67/Makefile.mk A src/mainboard/asus/sabertooth_p67/acpi/ec.asl A src/mainboard/asus/sabertooth_p67/acpi/platform.asl A src/mainboard/asus/sabertooth_p67/acpi/superio.asl A src/mainboard/asus/sabertooth_p67/board_info.txt A src/mainboard/asus/sabertooth_p67/cmos.default A src/mainboard/asus/sabertooth_p67/cmos.layout A src/mainboard/asus/sabertooth_p67/devicetree.cb A src/mainboard/asus/sabertooth_p67/dsdt.asl A src/mainboard/asus/sabertooth_p67/early_init.c A src/mainboard/asus/sabertooth_p67/gpio.c A src/mainboard/asus/sabertooth_p67/hda_verb.c A src/mainboard/asus/sabertooth_p67/mainboard.c 15 files changed, 576 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86484/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86484?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If643a9ceb944ba2a2c552202b56829b0a0c87925 Gerrit-Change-Number: 86484 Gerrit-PatchSet: 6 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Zhixing Ma (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel. Zhixing Ma has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 19:22:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/emulation/qemu-x86: Disable SB SSDT
by Patrick Rudolph (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86601?usp=email to look at the new patch set (#2). Change subject: mb/emulation/qemu-x86: Disable SB SSDT ...................................................................... mb/emulation/qemu-x86: Disable SB SSDT On QEMU the DSDT contains the _PRT, thus disable the southbridge SSDT generator to prevent an ACPI naming conflict. Change-Id: I894980dc7094f6047a088c39e10cac7381b74f86 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-q35/mainboard.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86601/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86601?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I894980dc7094f6047a088c39e10cac7381b74f86 Gerrit-Change-Number: 86601 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: mb/emulation/qemu-q35: Disable SB SSDT
by Patrick Rudolph (Code Review) 25 Feb '25

25 Feb '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86601?usp=email ) Change subject: mb/emulation/qemu-q35: Disable SB SSDT ...................................................................... mb/emulation/qemu-q35: Disable SB SSDT On QEMU the DSDT contains the _PRT, thus disable the southbridge SSDT generator to prevent an ACPI naming conflict. Change-Id: I894980dc7094f6047a088c39e10cac7381b74f86 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-q35/mainboard.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86601/1 diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 7debf8c..0b2e2bb 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -29,6 +29,11 @@ if (d) pci_assign_irqs(d, qemu_i440fx_irqs + (i % 4)); } + + /* Disable ACPI SSDT on LPC, it's already part of DSDT (by QEMU) */ + struct device *lpc = pcidev_on_root(0x1f, 0); + if (lpc && lpc->ops) + lpc->ops->acpi_fill_ssdt = NULL; } static void qemu_nb_read_resources(struct device *dev) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 1ff4c04..23ccb7c 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -42,6 +42,11 @@ if (d) pci_assign_irqs(d, qemu_q35_irqs); } + + /* Disable ACPI SSDT on LPC, it's already part of DSDT (by QEMU) */ + struct device *lpc = pcidev_on_root(0x1f, 0); + if (lpc && lpc->ops) + lpc->ops->acpi_fill_ssdt = NULL; } static void qemu_nb_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/86601?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I894980dc7094f6047a088c39e10cac7381b74f86 Gerrit-Change-Number: 86601 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/dedede: Add support to get sku ID
by Aamir Bohra (Code Review) 25 Feb '25

25 Feb '25

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86600?usp=email ) Change subject: mb/google/dedede: Add support to get sku ID ...................................................................... mb/google/dedede: Add support to get sku ID Implement SKU ID function. This will be used for sending the SKU ID information via coreboot tables. BUG=b:396366352 TEST=Verify coreboot table has valid SKU ID entry Change-Id: I1a928272db7d82747132c9c2c241ebcd1b5ed559 Signed-off-by: Aamir Bohra <aamirbohra(a)google.com> --- M src/mainboard/google/dedede/board_info.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86600/1 diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index 22d35d7..6e4074b 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <boardid.h> #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> @@ -7,3 +8,8 @@ { return google_chromeec_cbi_get_fw_config(fw_config); } + +uint32_t sku_id(void) +{ + return google_chromeec_get_board_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a928272db7d82747132c9c2c241ebcd1b5ed559 Gerrit-Change-Number: 86600 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com>

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