coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) ( 22 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... soc/intel/pantherlake: Display Sign-of-Life during memory training This commit activates the Firmware Support Package (FSP) Memory Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the display of a user-configurable text message on-screen during memory initialization. This feature enhances the user experience by providing reassurance that the memory training process is underway and may take some time. The following FSP-M UPDs (Updateable Product Data) are utilized: - VgaInitControl (boolean): Initializes graphics, establishes VGA text mode, and centers the VgaMessage text on the screen. It clears the screen, disables VGA text mode, and deactivates graphics upon exiting the FSP-M (Firmware Support Package - Memory Initialization). - VbtPtr (address): This is a pointer to the VBT (Video BIOS Table) binary. - VbtSize (unsigned integer): Indicates the size of the VBT binary. - LidStatus (boolean): Given the limited resources available at early boot stages, the text message is shown on a single monitor. The lid status determines the most appropriate display to use: - 0: If the lid is closed, display the text message on an external display if one is available; otherwise, display nothing. - 1: If the lid is open, display the message on the internal display; if unavailable, default to an external display. - VgaMessage (string): Specifies the text message to be displayed. When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured to use the UPDs mentioned above to show a text message during the memory training phase. This text message can be customized through the locale text mechanism using the identifier memory_training_desc. In addition, the newly introduced code records an extra event to indicate when early Sign-Of-Life has been requested, to cover the Memory Reference Code (MRC) training scenario. This event logging is crucial for debugging and analyzing the boot process, especially in production environments where it helps in pinpointing the exact stage where a boot issue might occur. TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon the first boot, and a message is displayed on the screen while the FSP performs MRC training. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85454 Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 37 insertions(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Ronak Kanabar: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index df95e52..a54f0de 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -17,6 +17,7 @@ select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP + select FSP_UGOP_EARLY_SIGN_OF_LIFE select FSP_USES_CB_DEBUG_EVENT_HANDLER select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 0c17d02..8de99d2 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> +#include <elog.h> #include <fsp/debug.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> @@ -11,6 +13,7 @@ #include <soc/pcie.h> #include <soc/romstage.h> #include <static.h> +#include <ux_locales.h> #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 @@ -355,6 +358,35 @@ fsp_control_log_level(mupd, fsp_debug_enable); } +static void fill_fspm_sign_of_life(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; + void *vbt; + size_t vbt_size; + + if (arch_upd->NvsBufferPtr) + return; + + /* To enhance the user experience, let's display on-screen guidance during memory + training, acknowledging that the process may require patience. */ + + vbt = cbfs_map("vbt.bin", &vbt_size); + if (!vbt) { + printk(BIOS_ERR, "Could not load vbt.bin\n"); + return; + } + + printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); + + m_cfg->VgaInitControl = 1; + m_cfg->VbtPtr = (efi_uintn_t)vbt; + m_cfg->VbtSize = vbt_size; + m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_pantherlake_config *config = config_of_soc(); @@ -363,6 +395,10 @@ fill_fsp_event_handler(mupd); soc_memory_init_params(&mupd->FspmConfig, config); + + if (CONFIG(FSP_UGOP_EARLY_SIGN_OF_LIFE)) + fill_fspm_sign_of_life(mupd); + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 24 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86578?usp=email ) Change subject: soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn ...................................................................... soc/intel/common/reset: Mark do_low_battery_poweroff with __noreturn In the low battery poweroff scenario, the platform should halt after issuing the poweroff command. This ensures that no further code execution occurs, preventing potential issues. Additionally, the do_low_battery_poweroff() function is marked with __noreturn to indicate that it does not return. This is appropriate because the platform will either power off or halt. TEST=Able to compile google/fatcat. Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86578 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/soc/intel/common/reset.c M src/soc/intel/common/reset.h 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: Jayvik Desai: Looks good to me, approved build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 3fefa57..307be57 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -32,4 +32,5 @@ } poweroff(); + halt(); } diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index 8331853..71fe05d 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -30,6 +30,6 @@ * * Call this function to power off the platform if the battery level is critically low. */ -void do_low_battery_poweroff(void); +__noreturn void do_low_battery_poweroff(void); #endif /* _INTEL_COMMON_RESET_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c Gerrit-Change-Number: 86578 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: treewide: Rename PM4LE -> PML4E
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86587?usp=email ) Change subject: treewide: Rename PM4LE -> PML4E ...................................................................... treewide: Rename PM4LE -> PML4E The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry. It is annoying when searching for the wrong abbreviation in the spec so fix it everywhere it occurs. source: Intel 64 spec April 2022 and AMD64 spec April 2024. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> --- M payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/pt.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/smm/smm_module_loader.c M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 12 files changed, 22 insertions(+), 22 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved Angel Pons: Looks good to me, approved Patrick Rudolph: Looks good to me, approved Andy Ebrahiem: Looks good to me, but someone else must approve Benjamin Doron: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/libpayload/arch/x86/head_64.S b/payloads/libpayload/arch/x86/head_64.S index 6524274..1fd0d01 100644 --- a/payloads/libpayload/arch/x86/head_64.S +++ b/payloads/libpayload/arch/x86/head_64.S @@ -70,7 +70,7 @@ movl %eax, cb_header_ptr call init_page_table - movl $pm4le, %eax + movl $pml4e, %eax /* load identity mapped page tables */ movl %eax, %cr3 @@ -107,7 +107,7 @@ movq %rdi, cb_header_ptr call init_page_table - movq $pm4le, %rax + movq $pml4e, %rax /* load identity mapped page tables */ movq %rax, %cr3 diff --git a/payloads/libpayload/arch/x86/pt.S b/payloads/libpayload/arch/x86/pt.S index 0e6e7bf..080d044 100644 --- a/payloads/libpayload/arch/x86/pt.S +++ b/payloads/libpayload/arch/x86/pt.S @@ -41,10 +41,10 @@ #define _D (1ULL << 6) #define _PS (1ULL << 7) -.section .bss.pm4le -.global pm4le +.section .bss.pml4e +.global pml4e .align 4096 -pm4le: +pml4e: .skip 8 .section .bss.main_page_table @@ -144,6 +144,6 @@ leave: or $(_PRES + _RW + _US + _A), %eax - mov %eax, pm4le + mov %eax, pml4e ret diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 227ddf4..de945a9 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -163,7 +163,7 @@ subl $4, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 9485cd4..7186422 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 1cb422d..1843954 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ subl $4, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi /* BIST */ diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index 18c6425..3be56c4 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -21,7 +21,7 @@ mov %esp, %ebp /* Enter long mode, preserves ebx */ - setup_longmode $PM4LE + setup_longmode $PML4E /* Align stack */ movabs $0xfffffffffffffff0, %rax diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 4b2f3c8..1297296 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) -.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT) .align 4096 diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 3502964..42cdfb1 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) -.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT) .align 4096 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index c6d0753..ba92e1ff 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -420,27 +420,27 @@ #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) #define PAGE_SIZE 8 -/* Return the PM4LE */ +/* Return the PML4E */ static uintptr_t install_page_table(const uintptr_t handler_base) { const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26)); /* 4 1G pages or 4 PDPE entries with 512 * 2M pages */ const size_t pages_needed = one_g_pages ? 4 : 2048 + 4; const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096); - const uintptr_t pm4le = ALIGN_DOWN(pages_base - 8, 4096); + const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096); if (one_g_pages) { for (size_t i = 0; i < 4; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i)); - write64p(pm4le, _GEN_DIR(pages_base)); + write64p(pml4e, _GEN_DIR(pages_base)); } else { for (size_t i = 0; i < 2048; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i)); - write64p(pm4le, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); + write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); for (size_t i = 0; i < 4; i++) write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i)); } - return pm4le; + return pml4e; } /* diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 0e0be52..b754588 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -28,7 +28,7 @@ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E #endif /* Clear .bss section */ diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 2c4beeb..b84a06e 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -280,7 +280,7 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4e057f0..ed735db 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -83,7 +83,7 @@ movl %ecx, temp_memory_start #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movl %ebp, %edi shlq $32, %rdi movd %mm1, %rsi -- To view, visit https://review.coreboot.org/c/coreboot/+/86587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Gerrit-Change-Number: 86587 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: soc/intel/pantherlake: Implement UX help APIs for eSOL handling
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86509?usp=email ) Change subject: soc/intel/pantherlake: Implement UX help APIs for eSOL handling ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/pantherlake/romstage/ux.c: https://review.coreboot.org/c/coreboot/+/86509/comment/2cee661c_29933132?us… : PS3, Line 24: static bool ux_done = false; > nit: Unnecessary initialization. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd Gerrit-Change-Number: 86509 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:30:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[M] Change in coreboot[main]: soc/intel/pantherlake: Implement UX help APIs for eSOL handling
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86509?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/pantherlake: Implement UX help APIs for eSOL handling ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/soc/intel/pantherlake/romstage/ux.c: https://review.coreboot.org/c/coreboot/+/86509/comment/cfa451bc_414a62d1?us… : PS3, Line 24: static bool ux_done = false; nit: Unnecessary initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/86509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd Gerrit-Change-Number: 86509 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:30:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84564/comment/85de9e83_de97a5fa?us… : PS5, Line 7: Initial commit for Intel Panther Lake RVP > Please make it a statement. Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:20:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Zhixing Ma. Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84564?usp=email to look at the new patch set (#6). Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat This commit introduces the Intel Panther Lake (PTL) Reference Validation Platform (RVP) mainboard definition. It is aligned with the Google Fatcat mainboard in the coreboot codebase, with the commit hash e2ea7f22c6355d15515c049ca0dc4352173a0c01. Intel's proprietary platform, commonly referred to as PTLRVP, and Google's Fatcat mainboard share a considerable degree of similarity in their design and capabilities. Nevertheless, Intel faces unique challenges and requires specific board configurations that Google does not. Consequently, there is a necessity for a specialized mainboard tailored to Intel's individual needs. To maintain consistency with the Fatcat board definition, the Chrome OS Board Information (CBI) firmware configuration aligns with that of Google Fatcat. If necessary, new bits will be appended, starting from the end of the 32-bit firmware configuration field. BUG=b:398880064 TEST=The Intel PTLRVP board successfully boots to the operating System. Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- A src/mainboard/intel/ptlrvp/Kconfig A src/mainboard/intel/ptlrvp/Kconfig.name A src/mainboard/intel/ptlrvp/Makefile.mk A src/mainboard/intel/ptlrvp/board_info.txt A src/mainboard/intel/ptlrvp/bootblock.c A src/mainboard/intel/ptlrvp/chromeos-debug-fsp.fmd A src/mainboard/intel/ptlrvp/chromeos.c A src/mainboard/intel/ptlrvp/chromeos.fmd A src/mainboard/intel/ptlrvp/dsdt.asl A src/mainboard/intel/ptlrvp/ec.c A src/mainboard/intel/ptlrvp/mainboard.c A src/mainboard/intel/ptlrvp/romstage.c A src/mainboard/intel/ptlrvp/smihandler.c A src/mainboard/intel/ptlrvp/spd/Makefile.mk A src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk A src/mainboard/intel/ptlrvp/variants/ptlrvp/devicetree.cb A src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/baseboard/ec.h A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/baseboard/gpio.h A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt A src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb A src/mainboard/intel/ptlrvp/variants/ptlrvp/ramstage.c A src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c 37 files changed, 3,386 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/84564/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[M] Change in coreboot[main]: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 9: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:16:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86532?usp=email ) Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > we are having discussion at https://review.coreboot. […] As we could not hold back the [85454 soc/intel/pantherlake: Display Sign-of-Life during memory training](https://review.coreboot.org/c/coreboot/+/85454) CL without any good justification, we are moving the discussion from [85454 3280809d_e258c525](https://review.coreboot.org/c/coreboot/+/85454/comment/3… here. -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Felix Held (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/acpi.c: https://review.coreboot.org/c/coreboot/+/86466/comment/983ad22c_d8fedc54?us… : PS3, Line 113: acpigen_write_integer(smn_address); good catch! my code didn't write the DWORD_PREFIX before the DWORD value which explains the malfunction -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:09:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025