coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Sean Rhodes (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Paul Menzel, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email ) Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84620/comment/6fcdfa48_bb703935?us… : PS7, Line 9: ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS : complaining about interrupt routing. > Please paste the log message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:23:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Sean Rhodes (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Sean Rhodes, Subrata Banik. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84620?usp=email to look at the new patch set (#8). Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS complaining about interrupt routing: pcieport 0000:00:06.0: can't derive routing for PCI INT A Tested on `starbook_adl` with Ubuntu 24.04 by running SSD benchmark with GNOME disks and suspend. Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/alderlake/acpi/pcie.asl M src/soc/intel/alderlake/acpi/pcie_pch_s.asl 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/84620/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Paul Menzel (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Sean Rhodes, Subrata Banik. Paul Menzel has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email ) Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84620/comment/55056e7c_1b485311?us… : PS7, Line 9: ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS : complaining about interrupt routing. Please paste the log message. -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:20:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/cpu: smbios: update external clock
by Paul Menzel (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Angel Pons, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Paul Menzel has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85636?usp=email ) Change subject: soc/amd/cpu: smbios: update external clock ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85636/comment/b20a8840_593bbbf0?us… : PS3, Line 7: update external clock Set external clock to 100 MHz https://review.coreboot.org/c/coreboot/+/85636/comment/9e5388f1_f117fba0?us… : PS3, Line 9: Se > Processor Programming Reference document. Please add it to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/85636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f73695019612d58b0c78c6985370d23c78b729 Gerrit-Change-Number: 85636 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Paul Menzel (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Shuo Liu, Tim Chu. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 6: (4 comments) File src/cpu/x86/64bit/mmu.c: https://review.coreboot.org/c/coreboot/+/85806/comment/88a901cc_771e434e?us… : PS6, Line 45: PT), fits on the line above. https://review.coreboot.org/c/coreboot/+/85806/comment/91053c69_a4702e7c?us… : PS6, Line 132: uint64_t *limit = (uint64_t *)gp; Add a blank line above? https://review.coreboot.org/c/coreboot/+/85806/comment/5f506ca1_3e8a99e9?us… : PS6, Line 160: if (cpu_supports_1gb_hugepage()) : return BITS_PER_VA_LVL4; : return 40; ```suggestion return cpu_supports_1gb_hugepage() ? BITS_PER_VA_LVL4 : 40; ``` https://review.coreboot.org/c/coreboot/+/85806/comment/26e6b0dc_1f5f0edf?us… : PS6, Line 178: printk(BIOS_DEBUG, "MMU: Upper MEM limit is 0x%llx\n", limit); : printk(BIOS_DEBUG, "MMU: New page tables are%s required\n", : (limit > mmu_default_map_size()) ? "" : "n't"); Also log mmu_default_map_size()? > MMU: New page tables are%s required (limit = x, default map size = y) -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:17:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible
by Paul Menzel (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86584?usp=email ) Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: The linter found several things. Most(?) of them valid. Commit Message: https://review.coreboot.org/c/coreboot/+/86584/comment/419d9e9b_410c75f6?us… : PS1, Line 21: Maybe paste the new log messages. File src/soc/amd/common/block/lpc/mmap_boot_rom3.c: https://review.coreboot.org/c/coreboot/+/86584/comment/0e15d61d_844faedc?us… : PS1, Line 27: (type == ROM2_DECODE_WINDOW) ? 2: 3); > `spaces required around that ':' (ctx:VxW)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/86584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Gerrit-Change-Number: 86584 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:09:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/cpu: smbios: update external clock
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Angel Pons, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Maximilian Brune has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85636?usp=email ) Change subject: soc/amd/cpu: smbios: update external clock ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85636/comment/f1a59cda_033bd17c?us… : PS3, Line 9: Se > Processor Programming Reference document. I mean in the commit message in the form: ``` source: PPR #57396 Rev 3.10 chapter "<chapter-name>" ``` I know it is tedious, but it helps a lot in verifying the information. -- To view, visit https://review.coreboot.org/c/coreboot/+/85636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f73695019612d58b0c78c6985370d23c78b729 Gerrit-Change-Number: 85636 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:08:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XS] Change in coreboot[main]: device/pci_rom: Support non VGA iGPUs
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Patrick Rudolph. Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86386?usp=email ) Change subject: device/pci_rom: Support non VGA iGPUs ...................................................................... Patch Set 4: (1 comment) File src/device/pci_rom.c: https://review.coreboot.org/c/coreboot/+/86386/comment/c702d3ac_4b191716?us… : PS4, Line 231: PCI_BASE_CLASS_DISPLAY I tested the image and I noticed that I get a bunch of error messages from coreboot for dGPUs. I am not sure if dGPUs are usually VGA compatible these days, but I think they are, so I probably got this error before this change too. -- To view, visit https://review.coreboot.org/c/coreboot/+/86386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I623cd80b45b148b91f2796b22a589bbede0feeeb Gerrit-Change-Number: 86386 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 14:19:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: device/pci_rom: Support non VGA iGPUs
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

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[XS] Change in coreboot[main]: device/pci_rom: Support non VGA iGPUs
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Patrick Rudolph. Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86386?usp=email ) Change subject: device/pci_rom: Support non VGA iGPUs ...................................................................... Patch Set 4: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86386/comment/3a92e88a_3a15ab93?us… : PS4, Line 9: any more anymore https://review.coreboot.org/c/coreboot/+/86386/comment/49348185_1ef9f9ad?us… : PS4, Line 10: any more anymore File src/device/pci_rom.c: https://review.coreboot.org/c/coreboot/+/86386/comment/b3b7b75a_d72b024a?us… : PS4, Line 210: ((uintptr_t)rom < MiB) ? "initialized " : "", rom); > The original code assumed that VGA_ROM_RUN was being used and the ROM in the C-segment had been run. […] Can we just remove the "initialized" stuff from the printing message? I don't think we should assume that the rom has been run/initialized just because it was already loaded into lower memory. -- To view, visit https://review.coreboot.org/c/coreboot/+/86386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I623cd80b45b148b91f2796b22a589bbede0feeeb Gerrit-Change-Number: 86386 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 14:12:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit February 2025