coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/adl: Delegate low-battery shutdown notification to platform
by Jayvik Desai (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86453?usp=email ) Change subject: soc/intel/adl: Delegate low-battery shutdown notification to platform ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86453?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9f68b2b5cc710e00584b451f904e60d724d1e32 Gerrit-Change-Number: 86453 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 16:04:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/pantherlake: Implement UX help APIs for eSOL handling
by Jayvik Desai (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Pranava Y N, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86509?usp=email ) Change subject: soc/intel/pantherlake: Implement UX help APIs for eSOL handling ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd Gerrit-Change-Number: 86509 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 16:03:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email ) Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > the change for picasso is still missing in this series; would be good to create a patch for that soc […] CB:86598 But I am not sure about genoa. It is a bit more complicated on that SOC. -- To view, visit https://review.coreboot.org/c/coreboot/+/86272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Gerrit-Change-Number: 86272 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 16:03:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Karthik Ramasubramanian (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jeremy Compostella, Julius Werner, Jérémy Compostella, Paul Menzel, Pranava Y N, Subrata Banik, Vikrant L Jadeja. Karthik Ramasubramanian has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 23: Code-Review+1 (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/c0e93de0_c917204c?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > > We have an open ticket to track the idea of whether to refactor some code or not. […] Even if we decide to take no action, we can update the TODO with the reason for code duplication. That way in future, everybody in the community know why the code duplication approach is chosen. -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 23 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 16:02:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86598?usp=email ) Change subject: soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default ...................................................................... soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb M src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb M src/soc/amd/picasso/chipset.cb 3 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/86598/1 diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb index e8b73ca..4af7231 100644 --- a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb @@ -344,6 +344,7 @@ device ref hda off end # HDA device ref mp2 on end # non-Sensor Fusion Hub device end + device ref internal_bridge_b off end # internal bridge to bus B device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias cros_ec on diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb index d6f2136..9b5a4c0 100644 --- a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb @@ -370,6 +370,7 @@ device ref hda off end # HDA device ref mp2 on end # non-Sensor Fusion Hub device end + device ref internal_bridge_b off end # internal bridge to bus B device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias cros_ec on diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index c11d502..a254cea 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -17,7 +17,7 @@ device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + device pci 08.1 alias internal_bridge_a on # internal bridge to bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller @@ -32,7 +32,7 @@ device pci 0.6 alias hda off end # main HD Audio Controller device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) end - device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + device pci 08.2 alias internal_bridge_b on # internal bridge to bus B ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata off ops amd_sata_ops end device pci 0.1 alias xgbe_0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Gerrit-Change-Number: 86598 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence
by Paul Menzel (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Frank Wu, Jayvik Desai, Pranava Y N. Paul Menzel has posted comments on this change by Frank Wu. ( https://review.coreboot.org/c/coreboot/+/86593?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86593/comment/11345354_98c83841?us… : PS1, Line 13: TEST=Build francka and do EC reset to check the SSD boots to OS successfully How much was the boot time improvement? -- To view, visit https://review.coreboot.org/c/coreboot/+/86593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Gerrit-Change-Number: 86593 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:56:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
by Jayvik Desai (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86452?usp=email ) Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Gerrit-Change-Number: 86452 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:44:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add early shutdown notification hook
by Jayvik Desai (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Pranava Y N, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86476?usp=email ) Change subject: soc/intel/pantherlake: Add early shutdown notification hook ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041 Gerrit-Change-Number: 86476 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:43:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Paul Menzel (Code Review) 25 Feb '25

25 Feb '25

Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8189/gpio.c: https://review.coreboot.org/c/coreboot/+/86538/comment/117311a6_083030fe?us… : PS4, Line 23: [SPI_NOR_CK] = { 0x10, 12, 3, }, : [SPI_NOR_CS] = { 0x10, 27, 3, }, : [SPI_NOR_IO0] = { 0x10, 15, 3, }, : [SPI_NOR_IO1] = { 0x10, 18, 3, }, : [SPI_NOR_IO2] = { 0x10, 21, 3, }, : [SPI_NOR_IO3] = { 0x10, 24, 3, }, A comment would have been nice, that to compare the tables SPI_NOR_GPIO_BASE has to be added. -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Maximilian Brune (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Naresh Solanki, Patrick Rudolph, Paul Menzel. Maximilian Brune has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 4: (2 comments) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/d834717d_22715c9e?us… : PS4, Line 39: s maybe add a comment like: `get local APIC ID` at the end of the line. That begs the question if we should use one of the existing functions (e.g. `lapicid()`) to get this information? https://review.coreboot.org/c/coreboot/+/85640/comment/1feaa30c_d15cf0e2?us… : PS4, Line 41: __fls(info->num_cores_shared-1); it may make sense to use `log2` directly, since that is also what is used in the AMD64 specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 15:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit February 2025