coreboot-gerrit February 2025

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[S] Change in coreboot[main]: brya: Add support to get sku ID
by Aamir Bohra (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86599?usp=email to look at the new patch set (#2). Change subject: brya: Add support to get sku ID ...................................................................... brya: Add support to get sku ID Implement SKU ID function. This will be used for sending the SKU ID information via coreboot tables. BUG=b:396366352 TEST=Verify coreboot table has valid SKU ID entry Change-Id: Ie55a9d83871f41e191574e554fe7d287c1ee60bd Signed-off-by: Aamir Bohra <aamirbohra(a)google.com> --- M src/mainboard/google/brya/Makefile.mk A src/mainboard/google/brya/sku_id.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86599/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie55a9d83871f41e191574e554fe7d287c1ee60bd Gerrit-Change-Number: 86599 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: brya: Add support to get sku ID
by Aamir Bohra (Code Review) 25 Feb '25

25 Feb '25

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86599?usp=email ) Change subject: brya: Add support to get sku ID ...................................................................... brya: Add support to get sku ID Implement SKU ID function. This will be used for sending the SKU ID information via coreboot tables. Change-Id: Ie55a9d83871f41e191574e554fe7d287c1ee60bd Signed-off-by: Aamir Bohra <aamirbohra(a)google.com> --- M src/mainboard/google/brya/Makefile.mk A src/mainboard/google/brya/sku_id.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86599/1 diff --git a/src/mainboard/google/brya/Makefile.mk b/src/mainboard/google/brya/Makefile.mk index 8c7e42d..fbacd91 100644 --- a/src/mainboard/google/brya/Makefile.mk +++ b/src/mainboard/google/brya/Makefile.mk @@ -10,6 +10,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += sku_id.c BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR)) diff --git a/src/mainboard/google/brya/sku_id.c b/src/mainboard/google/brya/sku_id.c new file mode 100644 index 0000000..7acf0c4 --- /dev/null +++ b/src/mainboard/google/brya/sku_id.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint32_t sku_id(void) +{ + return google_chromeec_get_board_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie55a9d83871f41e191574e554fe7d287c1ee60bd Gerrit-Change-Number: 86599 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper
by Angel Pons (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Jérémy Compostella, Maximilian Brune, Naresh Solanki, Patrick Rudolph, Paul Menzel. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Implement soc_fill_cpu_cache_info helper ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/309f493e_bcc11bc1?us… : PS4, Line 41: __fls(info->num_cores_shared-1); > Yes __fls it uses log2. What Max suggests is using `log2()` since that's what the spec says. Especially considering that `__fls()` literally just calls `log2()`: https://github.com/coreboot/coreboot/blob/8bb59ca2faee83ba50850900c8b4edf93… ``` static inline int __fls(u32 x) { return log2(x); } ``` I agree with this change and I would also add spaces around the `-`: ```suggestion info->unique_id = cpuid_cpu_id >> log2(info->num_cores_shared - 1); ``` Though now I wonder, is `info->num_cores_shared` ever 0? (Subtracting would underflow) And is it ever 1? (`log2(0)` is -1, IIRC negative shifts are undefined behaviour) -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 18:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Bora Guvendik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Zhixing Ma. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 18:30:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Jérémy Compostella (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Paul Menzel, Sean Rhodes, Subrata Banik. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email ) Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 17:59:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add early shutdown notification hook
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86476?usp=email ) Change subject: soc/intel/pantherlake: Add early shutdown notification hook ...................................................................... soc/intel/pantherlake: Add early shutdown notification hook This commit display UX message for low-battery shutdown using platform_display_early_shutdown_notification(). This commit also enables the HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR Kconfig option, which is required for displaying the VGA text message during early shutdown. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86476 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index a54f0de..fc8664a 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -22,6 +22,7 @@ select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP + select HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR if CHROMEOS_ENABLE_ESOL select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select HAVE_HYPERTHREADING diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index a8f86a8..93c8777 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -289,6 +289,14 @@ m_cfg->EnableFastVmode[i] = 0; } +#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) +void platform_display_early_shutdown_notification(void *arg) +{ + FSPM_UPD *mupd = arg; + ux_inform_user_of_poweroff_operation("low-battery shutdown", mupd); +} +#endif + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041 Gerrit-Change-Number: 86476 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Centralize FSP-M eSOL UX with common APIs
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86592?usp=email ) Change subject: soc/intel/pantherlake: Centralize FSP-M eSOL UX with common APIs ...................................................................... soc/intel/pantherlake: Centralize FSP-M eSOL UX with common APIs Refactor the FSP-M early Sign-of-Life (eSOL) implementation to utilize the UX APIs defined in `ux.c`. This eliminates redundant code and ensures consistent messaging during critical boot phases, such as memory training. BUG=b:339673254 TEST=Verified eSOL message over eDP while booting google/fatcat. Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86592 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 8de99d2..a8f86a8 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> #include <elog.h> @@ -13,7 +12,8 @@ #include <soc/pcie.h> #include <soc/romstage.h> #include <static.h> -#include <ux_locales.h> + +#include "ux.h" #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 @@ -360,31 +360,16 @@ static void fill_fspm_sign_of_life(FSPM_UPD *mupd) { - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; - void *vbt; - size_t vbt_size; if (arch_upd->NvsBufferPtr) return; /* To enhance the user experience, let's display on-screen guidance during memory training, acknowledging that the process may require patience. */ - - vbt = cbfs_map("vbt.bin", &vbt_size); - if (!vbt) { - printk(BIOS_ERR, "Could not load vbt.bin\n"); - return; - } - printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); - - m_cfg->VgaInitControl = 1; - m_cfg->VbtPtr = (efi_uintn_t)vbt; - m_cfg->VbtSize = vbt_size; - m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); + ux_inform_user_of_update_operation("memory training", mupd); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/86592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a Gerrit-Change-Number: 86592 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Implement UX help APIs for eSOL handling
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86509?usp=email ) Change subject: soc/intel/pantherlake: Implement UX help APIs for eSOL handling ...................................................................... soc/intel/pantherlake: Implement UX help APIs for eSOL handling This patch refactors the eSOL implementation for Panther Lake and introduces two new APIs, mirroring those in Alder Lake, to manage: - Low battery shutdown notifications - Firmware update memory training BUG=b:397302064 TEST=Built and booted google/fatcat successfully. Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86509 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/romstage/Makefile.mk A src/soc/intel/pantherlake/romstage/ux.c A src/soc/intel/pantherlake/romstage/ux.h 3 files changed, 77 insertions(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Jayvik Desai: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/romstage/Makefile.mk b/src/soc/intel/pantherlake/romstage/Makefile.mk index 99c1d2c..999241c 100644 --- a/src/soc/intel/pantherlake/romstage/Makefile.mk +++ b/src/soc/intel/pantherlake/romstage/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c +romstage-y += ux.c diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c new file mode 100644 index 0000000..9fcb418 --- /dev/null +++ b/src/soc/intel/pantherlake/romstage/ux.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <console/console.h> +#include <fsp/util.h> +#include <timestamp.h> +#include <ux_locales.h> + +#include "ux.h" + +static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id, + FSPM_UPD *mupd) +{ + timestamp_add_now(TS_ESOL_START); + + if (!CONFIG(CHROMEOS_ENABLE_ESOL)) { + timestamp_add_now(TS_ESOL_END); + return false; + } + + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *vbt; + size_t vbt_size; + static bool ux_done = false; + + /* + * Prevents multiple VGA text messages from being rendered during the boot process. + * + * This function is designed to be called only once. Subsequent calls are intentionally + * ignored to avoid overwriting previously displayed messages. For example, if a + * low-battery shutdown notification is scheduled, a later call with a firmware + * update notification could result in the low-battery message being lost. + */ + if (ux_done) { + timestamp_add_now(TS_ESOL_END); + return true; + } + + printk(BIOS_INFO, "Informing user on-display of %s.\n", name); + + vbt = cbfs_map("vbt.bin", &vbt_size); + if (!vbt) { + printk(BIOS_ERR, "Could not load vbt.bin\n"); + return false; + } + + m_cfg->VgaInitControl = 1; + m_cfg->VbtPtr = (efi_uintn_t)vbt; + m_cfg->VbtSize = vbt_size; + m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(id); + + ux_done = true; + + timestamp_add_now(TS_ESOL_END); + return true; +} + +bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd) +{ + return ux_inform_user_of_operation(name, UX_LOCALE_MSG_MEMORY_TRAINING, mupd); +} + +bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd) +{ + return ux_inform_user_of_operation(name, UX_LOCALE_MSG_LOW_BATTERY, mupd); +} diff --git a/src/soc/intel/pantherlake/romstage/ux.h b/src/soc/intel/pantherlake/romstage/ux.h new file mode 100644 index 0000000..bcee87f --- /dev/null +++ b/src/soc/intel/pantherlake/romstage/ux.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ +#define _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ + +bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd); +bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd); + +#endif /* _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd Gerrit-Change-Number: 86509 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/adl: Delegate low-battery shutdown notification to platform
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86453?usp=email ) Change subject: soc/intel/adl: Delegate low-battery shutdown notification to platform ...................................................................... soc/intel/adl: Delegate low-battery shutdown notification to platform This commit removes the SoC-specific implementation of the early low-battery shutdown notification. The generic implementation now resides within the FSP driver layer, requiring only platform-specific customization. Platforms can now implement platform_display_early_shutdown_notification() when CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) is enabled. This function utilizes ux_inform_user_of_poweroff_operation() to display a "low-battery shutdown" message using libgfxinit. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: If9f68b2b5cc710e00584b451f904e60d724d1e32 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86453 Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 7 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved Andy Ebrahiem: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 71791ae..24b2c8c 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -415,6 +415,13 @@ debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode); } +#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) +void platform_display_early_shutdown_notification(void *arg) +{ + ux_inform_user_of_poweroff_operation("low-battery shutdown"); +} +#endif + static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, FSPM_ARCH_UPD *arch_upd) { @@ -429,28 +436,6 @@ * user with an on-screen text message. */ if (!arch_upd->NvsBufferPtr) { - /* - * Low Battery Check During Firmware Update (Chrome OS specific): - * - If `PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR` is enabled AND the - * system is in firmware update mode (If valid MRC cache data is not found, - * it means that the system needs to perform), it checks if the battery level is - * critically low. - * - This is because memory training, which can take a significant amount of - * time, might cause an abrupt shutdown due to low battery, interrupting the - * firmware update process and potentially leaving the system in an unstable - * state. - * - To prevent this, if the battery is critically low, the system is powered - * off to allow it to charge. This ensures that the firmware update process - * can complete without interruption. - * - Since a functional GFX mode display may not be ready at this stage, VGA - * mode is used to display a text message informing the user about the - * shutdown. - */ - if (CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) && - platform_is_low_battery_shutdown_needed()) { - ux_inform_user_of_poweroff_operation("low-battery shutdown"); - do_low_battery_poweroff(); - } esol_required = true; name = "memory training"; elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); -- To view, visit https://review.coreboot.org/c/coreboot/+/86453?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9f68b2b5cc710e00584b451f904e60d724d1e32 Gerrit-Change-Number: 86453 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86452?usp=email ) Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init ...................................................................... drivers/intel/fsp2_0: Add early low-battery shutdown during memory init This commit introduces an early low-battery shutdown mechanism during FSP memory initialization. This is particularly important during firmware updates, where memory training can consume significant power and lead to abrupt shutdowns, potentially corrupting the firmware. The changes include: - Adding platform_display_early_shutdown_notification() to notify the user of the impending shutdown. - Checking platform_is_low_battery_shutdown_needed() to determine if a shutdown is necessary. - Implementing a shutdown sequence if low battery is detected during memory init, especially when no MRC cache is found (i.e. firmware update). - Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT so that FSP-M (uGOP) can display a message. This prevents firmware update corruption due to low battery. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86452 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 56 insertions(+), 0 deletions(-) Approvals: Jayvik Desai: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 28b24ce..d159b71 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -63,6 +63,26 @@ #else static inline bool platform_is_low_battery_shutdown_needed(void) { return false; } #endif + +/* + * Displays an early shutdown notification to the user. + * + * This function is responsible to perform the needful operations for informing + * the user that the system is about to shut down prematurely. The implementation + * might be different depending upon the underlying technology that can be used for + * implementing eSOL for user notification. + * + * Argument: NULL for platform with libgfxinit and FSP-M UPD pointer for uGOP. + * + * Note: This function should be called before the actual shutdown process begins, + * allowing the user to potentially save data or take other necessary actions. + */ +#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) +void platform_display_early_shutdown_notification(void *arg); +#else +static inline void platform_display_early_shutdown_notification(void *arg) { /* nop */ } +#endif + /* Check if MultiPhase Si Init is enabled */ bool fsp_is_multi_phase_init_enabled(void); /* diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index ce0d283..38627c6 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -19,6 +19,7 @@ #include <security/tpm/tspi.h> #include <security/vboot/antirollback.h> #include <security/vboot/vboot_common.h> +#include <soc/intel/common/reset.h> #include <string.h> #include <symbols.h> #include <timestamp.h> @@ -331,6 +332,31 @@ timestamp_add_now(TS_FSP_MULTI_PHASE_MEM_INIT_END); } +/** + * Checks for low battery during firmware update and initiates shutdown if necessary. + * + * This function checks if the system is in firmware update mode (indicated by + * a missing MRC cache) and if the battery is critically low. If both conditions + * are met, it initiates a shutdown to prevent interruption of the firmware + * update process. + */ +static void handle_low_battery_during_firmware_update(bool *defer_shutdown, FSPM_UPD *fspm_upd) +{ + if (!CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) || + !platform_is_low_battery_shutdown_needed()) + return; + + if (CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT)) { + platform_display_early_shutdown_notification(NULL); + /* User has been notified of low battery; safe to power off. */ + do_low_battery_poweroff(); /* Do not return */ + } + + /* Defer shutdown until FSP-M (uGOP) display text message for user notification */ + platform_display_early_shutdown_notification(fspm_upd); + *defer_shutdown = true; +} + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { efi_return_status_t status; @@ -338,6 +364,7 @@ FSPM_UPD fspm_upd, *upd; FSPM_ARCHx_UPD *arch_upd; uint32_t version; + bool poweroff_after_fsp_execution = false; const struct fsp_header *hdr = &context->header; const struct memranges *memmap = &context->memmap; @@ -389,6 +416,11 @@ early_ramtop_enable_cache_range(); #endif + /* Low battery check during firmware update */ + if (!arch_upd->NvsBufferPtr) + handle_low_battery_during_firmware_update(&poweroff_after_fsp_execution, + &fspm_upd); + /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, version); @@ -425,6 +457,10 @@ null_breakpoint_init(); stack_canary_breakpoint_init(); + /* User has been notified of low battery; safe to power off. */ + if (poweroff_after_fsp_execution) + do_low_battery_poweroff(); + post_code(POSTCODE_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); -- To view, visit https://review.coreboot.org/c/coreboot/+/86452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Gerrit-Change-Number: 86452 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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