Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86535?usp=email )
Change subject: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
......................................................................
mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name Vendor Model Spec ID to assign
K3KL8L80CM-MGCT Samsung LPDDR5X 7500 32Gb 0 (0000)
K3KL6L60GM-MGCT Samsung LPDDR5X 7500 16Gb 1 (0001)
H58G56AK6BX069 SK hynix LPDDR5 6400 32Gb 2 (0010)
H9JCNNNBK3MLYR-N6E SK hynix LPDDR5 6400 16Gb 3 (0011)
H58G66AK6BX070 SK hynix LPDDR5 6400 64Gb 4 (0100)
K3KL9L90CM-MGCT Samsung LPDDR5X 7500 64Gb 5 (0101)
K3LKBKB0BM-MGCP Samsung LPDDR5 6400 16Gb 2 (0010)
BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/guren/memory/ \
src/mainboard/google/brya/variants/guren/memory/\
mem_parts_used.txt"
Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232
Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86535
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jayvik Desai <jayvik(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/google/brya/variants/guren/memory/Makefile.mk
M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
3 files changed, 28 insertions(+), 2 deletions(-)
Approvals:
Paul Menzel: Looks good to me, but someone else must approve
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Jayvik Desai: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
index eace2e4..943dfba 100644
--- a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
@@ -1,5 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 3(0b0011) Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 4(0b0100) Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 5(0b0101) Parts = K3KL9L90CM-MGCT
diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
index fa24790..62cd085 100644
--- a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
@@ -1 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+
DRAM Part Name ID to assign
+K3KL8L80CM-MGCT 0 (0000)
+K3KL6L60GM-MGCT 1 (0001)
+H58G56AK6BX069 2 (0010)
+H9JCNNNBK3MLYR-N6E 3 (0011)
+H58G66AK6BX070 4 (0100)
+K3KL9L90CM-MGCT 5 (0101)
+K3LKBKB0BM-MGCP 2 (0010)
diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
index 2499005..a7e8120 100644
--- a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
@@ -9,3 +9,10 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+K3KL8L80CM-MGCT
+K3KL6L60GM-MGCT
+H58G56AK6BX069
+H9JCNNNBK3MLYR-N6E
+H58G66AK6BX070
+K3KL9L90CM-MGCT
+K3LKBKB0BM-MGCP
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Change subject: mb/google/trulo/var/uldrenite: Support body detection to DPTF
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Change subject: treewide: Rename PM4LE -> PML4E
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Change subject: cpu/x86/64bit: Install extended page tables in BSS
......................................................................
Patch Set 6:
(1 comment)
File src/cpu/x86/64bit/mmu.c:
https://review.coreboot.org/c/coreboot/+/85806/comment/9530efdf_2dd99651?us… :
PS6, Line 157: * when 1GB PT aren't supported it maps 40 bits of the address space (512GiB).
512GiB -> 39bits?
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Change subject: brya: Add support to get sku ID
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
sorry, unable to follow why can't we call into `google_chromeec_xxx` API directly and need to introduce one more wrapper around it (which doesn't perform any additional benefit over the existing API ?
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Change subject: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Dear all, If no concern, please kindly help to submit the CL. Thanks.
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Change subject: commonlib/device_tree: fix 64-bit misaligned member access
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Patch Set 5:
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PS5:
> I was under the impression that the decode functions are all common code only?
Well, you can change that, right? You can put an `#if ENV_RISCV` in there. I think doing that in the endianness accessor header would be much better than in this code here.
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Change subject: commonlib/device_tree: fix 64-bit misaligned member access
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Patch Set 5:
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PS5:
> I don't think we should make changes to architecture-independent code to support the quirks of a sin […]
You are right. This issue has come up before and will likely do so again. I am trying to avoid the misaligned exception handler because it adds a hefty overhead. But I agree that it doesn't make sense to impose that limitation onto all the other architectures.
But I don't understand how be64dec can use RISC-V specific implementations? I was under the impression that the decode functions are all common code only? As far as I know only the MMIO read/write functions are architecture code.
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Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86377/comment/75c9ffe3_fd5d441f?us… :
PS8, Line 15:
> > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […]
Done
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Gerrit-Comment-Date: Wed, 26 Feb 2025 00:24:05 +0000
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Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>