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Change subject: tree: Rename CBFS_SIZE to BIOS_SIZE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS2:
> I think BIOS_BASE/SIZE is equivalent to CB_BASE/SIZE, but BIOS_BASE/SIZE is more understandable.
Then maybe the current naming strategy is usable?
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Change subject: tree: Rename CBFS_SIZE to BIOS_SIZE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS2:
> A point to clarify is - based on this patch (not the original HEAD), the renaming means BIOS_BASE/SI […]
I think BIOS_BASE/SIZE is equivalent to CB_BASE/SIZE, but BIOS_BASE/SIZE is more understandable.
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Change subject: tree: Rename CBFS_SIZE to BIOS_SIZE
......................................................................
Patch Set 5:
(1 comment)
This change is ready for review.
Patchset:
PS2:
> Does CBFS stand for coreboot file system? If so, I think the renaming is more meaningful because `RW […]
A point to clarify is - based on this patch (not the original HEAD), the renaming means BIOS_BASE/SIZE to CB_BASE/SIZE, right?
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Attention is currently required from: Boris Mittelberg, Caveh Jalali, Eric Lai, Felix Singer, Intel coreboot Reviewers, Subrata Banik.
Hello Boris Mittelberg, Caveh Jalali, Eric Lai, Intel coreboot Reviewers, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82314?usp=email
to look at the new patch set (#17).
Change subject: spd_bin.h: Deduplicate SPD definitions
......................................................................
spd_bin.h: Deduplicate SPD definitions
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/include/spd_bin.h
M src/lib/spd_bin.c
M src/lib/spd_cache.c
M src/mainboard/google/cyan/spd/spd.c
M src/soc/intel/common/block/smbus/smbuslib.c
5 files changed, 67 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/82314/17
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Change subject: mb/google/ovis/var/deku: Update retimer tcss port number
......................................................................
Patch Set 2: -Code-Review
(1 comment)
Patchset:
PS2:
After looking into the code in src/drivers/intel/usb4/retimer/retimer.c, I think we should correct the `tcss_usb3_port` and `ec_port` mapping in `retimer_get_index_for_typec` instead of changing the device tree.
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SH Kim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86508?usp=email )
Change subject: mb/google/nissa/var/meliks: Add VBT data file
......................................................................
Abandoned
This change is not necessary.
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Derek Huang has posted comments on this change by Tony Huang. ( https://review.coreboot.org/c/coreboot/+/86603?usp=email )
Change subject: mb/google/ovis/var/deku: Update retimer tcss port number
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> wondering how it was working so far ? your ports were swapped ?
It never works on Deku due to the wrong configuration. This patch fixes the problem.
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Change subject: mb/google/ovis/var/deku: Update retimer tcss port number
......................................................................
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(1 comment)
Patchset:
PS2:
wondering how it was working so far ? your ports were swapped ?
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Hello Derek Huang, Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86603?usp=email
to look at the new patch set (#2).
Change subject: mb/google/ovis/var/deku: Update retimer tcss port number
......................................................................
mb/google/ovis/var/deku: Update retimer tcss port number
Deku use tcss_usb3_port2 for C1 port and tcss_usb3_port1 for C2 port.
Verify the HBR can be enumerated in 1-0:1.1 (C1) or 0-0:3.1 (C2)
by command.
C1 port:
cd /sys/bus/thunderbolt/devices
echo 1 > 1-0/usb4_port1/offline
echo 1 > 1-0/usb4_port1/rescan
C2 port:
cd /sys/bus/thunderbolt/devices
echo 1 > 0-0/usb4_port3/offline
echo 1 > 0-0/usb4_port3/rescan
BUG=b:399032094
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
verify HBR can be enumerated by command
Change-Id: I763d11c5caae28c49514745d47fda0d6ca200faf
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/rex/variants/deku/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/86603/2
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