coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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2886 discussions

[S] Change in coreboot[main]: soc/mediatek/mt8196: Save HW protect temperature to SRAM
by Zhaoqing Jiu (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Zhaoqing Jiu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86551?usp=email ) Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86551/comment/fd8a0644_18bf387a?us… : PS2, Line 10: after the system suspends and resumes > Does this effect resume time? No, won't affect resume time. We just give a correct value here, not affect logic. File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86551/comment/4a63a91e_562c5023?us… : PS2, Line 606: if (tc_num == LVTS_AP_CONTROLLER0) : tc_index = 0; : else if (tc_num == LVTS_AP_CONTROLLER1) : tc_index = 1; : : if (tc_index != 0xff) { : thermal_write_reboot_msr_sram(tc_index, raw_high); : if (tc_index == 0) : thermal_write_reboot_temp_sram(tc->reboot_temperature); : } > I feel like the flow should be controlled by the `lvts_thermal_controller` struct, because that's ho […] not reserve sram slot for controllers 2 and 3. File src/soc/mediatek/mt8196/thermal_sram.c: https://review.coreboot.org/c/coreboot/+/86551/comment/493a2ef0_21a0ce9e?us… : PS2, Line 68: write32 > write32p ? there will be compile error if use write32p -- To view, visit https://review.coreboot.org/c/coreboot/+/86551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 Gerrit-Change-Number: 86551 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 12:11:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: cpu/x86/64bit: Allow to map more of the address space
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Jérémy Compostella, Patrick Rudolph. Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86580?usp=email ) Change subject: cpu/x86/64bit: Allow to map more of the address space ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Gerrit-Change-Number: 86580 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 12:05:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Use default turbo ratio
by Patrick Rudolph (Code Review) 26 Feb '25

26 Feb '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86604?usp=email ) Change subject: soc/intel/xeon_sp/spr: Use default turbo ratio ...................................................................... soc/intel/xeon_sp/spr: Use default turbo ratio Allow a board to use the default turbo ratio by not specifying turbo_ratio_limit and turbo_ratio_limit_cores in the devicetree.cb. FIXES: Intel PTAT tool no longer complains about 0Mhz turbo frequency. Change-Id: Ib8fbc78997fc7f8e6c80b2029d63b70f6117542e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/cpu.c 1 file changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86604/1 diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index febc72b..383bf5f 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -95,14 +95,18 @@ wrmsr(MSR_VR_CURRENT_CONFIG, msr); /* Set Turbo Ratio Limits */ - msr.lo = chip_config->turbo_ratio_limit & 0xffffffff; - msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff; - wrmsr(MSR_TURBO_RATIO_LIMIT, msr); + if (chip_config->turbo_ratio_limit) { + msr.lo = chip_config->turbo_ratio_limit & 0xffffffff; + msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff; + wrmsr(MSR_TURBO_RATIO_LIMIT, msr); + } /* Set Turbo Ratio Limit Cores */ - msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff; - msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff; - wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr); + if (chip_config->turbo_ratio_limit_cores) { + msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff; + msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff; + wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr); + } /* Set energy policy */ msr = rdmsr(MSR_ENERGY_PERF_BIAS_CONFIG); -- To view, visit https://review.coreboot.org/c/coreboot/+/86604?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib8fbc78997fc7f8e6c80b2029d63b70f6117542e Gerrit-Change-Number: 86604 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Tim Chu. Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > `CPU_PT_ROM_MAP_GB` affects all stages. […] Considering that we use 1GB pages for almost all platforms (especially the more recent ones) we don't really save much space do we? So it doesn't really have an effect on any platform besides QEMU maybe. All other platforms that need 2MB pages for are already ~10 year old and don't have this much RAM anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: drivers/smmstore: add logic to disable capsule update handling code
by Krystian Hebel (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Arthur Heymans, Benjamin Doron, Felix Held, Martin L Roth, Patrick Rudolph, Sergii Dmytruk. Krystian Hebel has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83425?usp=email ) Change subject: drivers/smmstore: add logic to disable capsule update handling code ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dc175ea313aae1edae304520595b82db7206cbb Gerrit-Change-Number: 83425 Gerrit-PatchSet: 14 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:55:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/ovis/var/deku: Update retimer tcss port number
by Paul Menzel (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Kapil Porwal, Tarun, Tony Huang. Paul Menzel has posted comments on this change by Tony Huang. ( https://review.coreboot.org/c/coreboot/+/86603?usp=email ) Change subject: mb/google/ovis/var/deku: Update retimer tcss port number ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I763d11c5caae28c49514745d47fda0d6ca200faf Gerrit-Change-Number: 86603 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:47:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/ovis/var/deku: Update retimer tcss port number
by Paul Menzel (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Kapil Porwal, Tarun, Tony Huang. Paul Menzel has posted comments on this change by Tony Huang. ( https://review.coreboot.org/c/coreboot/+/86603?usp=email ) Change subject: mb/google/ovis/var/deku: Update retimer tcss port number ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86603/comment/1df2da44_8c2e1587?us… : PS2, Line 7: number number*s*? https://review.coreboot.org/c/coreboot/+/86603/comment/8ff91bd6_deaa2ec4?us… : PS2, Line 9: use uses https://review.coreboot.org/c/coreboot/+/86603/comment/f7cb27e5_c10414cd?us… : PS2, Line 23: Thank you for adding the commands to test this. It’d still be great if you mentioned also the schematic version you used. -- To view, visit https://review.coreboot.org/c/coreboot/+/86603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I763d11c5caae28c49514745d47fda0d6ca200faf Gerrit-Change-Number: 86603 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:46:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: cpu/x86/64bit: Allow to map more of the address space
by Patrick Rudolph (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Jérémy Compostella, Maximilian Brune. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86580?usp=email ) Change subject: cpu/x86/64bit: Allow to map more of the address space ...................................................................... Patch Set 2: (2 comments) File src/cpu/x86/64bit/pt1G.S: https://review.coreboot.org/c/coreboot/+/86580/comment/b9d76cc2_581bc72a?us… : PS1, Line 23: .rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 > Thats what I was trying to say. We agree on that. […] Done File src/cpu/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/86580/comment/50a020b1_6559fe67?us… : PS1, Line 165: default 512 if !NEED_SMALL_2MB_PAGE_TABLES > Is it necessary to specify `if !NEED_SMALL_2MB_PAGE_TABLES` considering this is the opposite of the […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Gerrit-Change-Number: 86580 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:42:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Maximilian Brune, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > I don't really grasp yet why we need this code. […] `CPU_PT_ROM_MAP_GB` affects all stages. That would increase the size of every stage, but it's only needed in ramstage after resources have been enabled -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:41:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust thermal trip point parameters
by Zhaoqing Jiu (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Zhaoqing Jiu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86552?usp=email ) Change subject: soc/mediatek/mt8196: Adjust thermal trip point parameters ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86552/comment/09354ec9_1bb98bc8?us… : PS3, Line 10: > Why are the new values correct? the new values are tuned by HW team, and were verified that interrupt could be triggered at expected trip point -- To view, visit https://review.coreboot.org/c/coreboot/+/86552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Gerrit-Change-Number: 86552 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 11:33:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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