coreboot-gerrit February 2025

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[S] Change in coreboot[main]: include/endian.h: Add 'always aligned access' support
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Maximilian Brune. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86609?usp=email to look at the new patch set (#3). Change subject: include/endian.h: Add 'always aligned access' support ...................................................................... include/endian.h: Add 'always aligned access' support RISC-V doesn't support unaligned access, so check for that before decoding and encoding. It is not perfectly performant, but still much better then invoking the misaligned exception handler every time there is a misaligned access. We can't modify our whole codebase to always do aligned access, because it is neither feasible in long term nor is fair to add that performance penalty onto other architectures that do support unaligned access. So this is the next best thing. On architectures that do support unaligned access the compiler will just optimize the RISCV_ENV part out and should result in the exact same binary. tested: identical binary on QEMU-aarch64 and QEMU-q35. Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/include/endian.h 1 file changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/86609/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Gerrit-Change-Number: 86609 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: commonlib/device_tree: fix 64-bit misaligned member access
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Joel Bueno, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change by Joel Bueno. ( https://review.coreboot.org/c/coreboot/+/85800?usp=email ) Change subject: commonlib/device_tree: fix 64-bit misaligned member access ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > I was under the impression that the decode functions are all common code only? […] CB:86609 -- To view, visit https://review.coreboot.org/c/coreboot/+/85800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Gerrit-Change-Number: 85800 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 16:24:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: drivers/lenovo/hybrid_graphics/chip: Use boolean when appropriate
by Elyes Haouas (Code Review) 26 Feb '25

26 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86610?usp=email ) Change subject: drivers/lenovo/hybrid_graphics/chip: Use boolean when appropriate ...................................................................... drivers/lenovo/hybrid_graphics/chip: Use boolean when appropriate Change-Id: I1f456765eb60b8ad1e680255b50abad5dea8252c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/lenovo/hybrid_graphics/chip.h M src/mainboard/lenovo/t400/variants/t400/overridetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb 8 files changed, 45 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/86610/1 diff --git a/src/drivers/lenovo/hybrid_graphics/chip.h b/src/drivers/lenovo/hybrid_graphics/chip.h index b3ea2b6..4a17138 100644 --- a/src/drivers/lenovo/hybrid_graphics/chip.h +++ b/src/drivers/lenovo/hybrid_graphics/chip.h @@ -23,19 +23,19 @@ struct drivers_lenovo_hybrid_graphics_config { unsigned int detect_gpio; - unsigned int has_panel_hybrid_gpio; + bool has_panel_hybrid_gpio; unsigned int panel_hybrid_gpio; - unsigned int panel_integrated_lvl; + bool panel_integrated_lvl; - unsigned int has_backlight_gpio; + bool has_backlight_gpio; unsigned int backlight_gpio; - unsigned int backlight_integrated_lvl; + bool backlight_integrated_lvl; - unsigned int has_dgpu_power_gpio; + bool has_dgpu_power_gpio; unsigned int dgpu_power_gpio; - unsigned int dgpu_power_off_lvl; + bool dgpu_power_off_lvl; - unsigned int has_thinker1; + bool has_thinker1; }; #endif /* _LENOVO_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb index a1b4f9d..c3c3b08 100644 --- a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb +++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb @@ -8,17 +8,17 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "22" - register "panel_integrated_lvl" = "0" + register "panel_integrated_lvl" = "false" - register "has_backlight_gpio" = "1" + register "has_backlight_gpio" = "true" register "backlight_gpio" = "19" - register "backlight_integrated_lvl" = "0" + register "backlight_integrated_lvl" = "false" - register "has_dgpu_power_gpio" = "1" + register "has_dgpu_power_gpio" = "true" register "dgpu_power_gpio" = "49" - register "dgpu_power_off_lvl" = "0" + register "dgpu_power_off_lvl" = "false" register "has_thinker1" = "0" end diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 1ef7075..9ba70d7 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -138,19 +138,19 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" + register "panel_integrated_lvl" = "true" - register "has_backlight_gpio" = "1" + register "has_backlight_gpio" = "true" register "backlight_gpio" = "50" - register "backlight_integrated_lvl" = "0" + register "backlight_integrated_lvl" = "false" - register "has_dgpu_power_gpio" = "1" + register "has_dgpu_power_gpio" = "true" register "dgpu_power_gpio" = "49" - register "dgpu_power_off_lvl" = "0" + register "dgpu_power_off_lvl" = "false" - register "has_thinker1" = "1" + register "has_thinker1" = "true" end end device pci 1f.2 on # IDE/SATA diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 65891f0..f5272fc 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -158,14 +158,14 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" + register "panel_integrated_lvl" = "true" - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" + register "has_backlight_gpio" = "false" + register "has_dgpu_power_gpio" = "false" - register "has_thinker1" = "1" + register "has_thinker1" = "true" end end # LPC Controller device ref sata1 on end # 6 port SATA AHCI Controller diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b358885..840e520 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -150,14 +150,14 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" + register "panel_integrated_lvl" = "true" - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" + register "has_backlight_gpio" = "false" + register "has_dgpu_power_gpio" = "false" - register "has_thinker1" = "1" + register "has_thinker1" = "true" end end # LPC Controller device ref sata1 on end # 6 port SATA AHCI Controller diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 89dcf97..9a0db4d 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -131,14 +131,14 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" + register "panel_integrated_lvl" = "true" - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" + register "has_backlight_gpio" = "false" + register "has_dgpu_power_gpio" = "false" - register "has_thinker1" = "1" + register "has_thinker1" = "true" end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index c404df2..7102df0 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -146,14 +146,14 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" + register "panel_integrated_lvl" = "true" - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" + register "has_backlight_gpio" = "false" + register "has_dgpu_power_gpio" = "false" - register "has_thinker1" = "1" + register "has_thinker1" = "true" end end device ref sata1 on end diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 305a47e..362e0a6 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -126,14 +126,14 @@ register "detect_gpio" = "21" - register "has_panel_hybrid_gpio" = "1" + register "has_panel_hybrid_gpio" = "true" register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" + register "panel_integrated_lvl" = "true" - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" + register "has_backlight_gpio" = "false" + register "has_dgpu_power_gpio" = "false" - register "has_thinker1" = "1" + register "has_thinker1" = "true" end end device ref sata1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/86610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f456765eb60b8ad1e680255b50abad5dea8252c Gerrit-Change-Number: 86610 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: include/endian.h: Add 'always aligned access' support
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Maximilian Brune. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86609?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: include/endian.h: Add 'always aligned access' support ...................................................................... include/endian.h: Add 'always aligned access' support RISC-V doesn't support unaligned access, so check for that before decoding and encoding. It is not perfectly performant, but still much better then invoking the misaligned exception handler every time there is a misaligned access. We can't modify our whole codebase to always do aligned access, because it is neither feasable in long term nor is fair to add that perfomance penalty onto other architectures that do support unaligned access. So this is the next best thing. On architectures that do support unaligned access the compiler will just optimize the RISCV_ENV part out and should result in the exact same binary. tested: identical binary on QEMU-aarch64 and QEMU-q35. Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/include/endian.h 1 file changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/86609/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Gerrit-Change-Number: 86609 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>

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[L] Change in coreboot[main]: util/cbmem: Extract memory mapping to common functions
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Konrad Adamczyk, Paul Menzel. Jakub "Kuba" Czapiga has posted comments on this change by Jakub "Kuba" Czapiga. ( https://review.coreboot.org/c/coreboot/+/86487?usp=email ) Change subject: util/cbmem: Extract memory mapping to common functions ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86487/comment/5defb1a7_aa8ff26b?us… : PS3, Line 7: util/cbmem: Extract memory mapping to common functions. > Please remove the dot/period at the end. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f8790842a932c4cf7717298ef43c8110dfa878 Gerrit-Change-Number: 86487 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 26 Feb 2025 16:16:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: util/cbmem: Extract devmem and common code to separate files
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Jakub "Kuba" Czapiga has posted comments on this change by Jakub "Kuba" Czapiga. ( https://review.coreboot.org/c/coreboot/+/86557?usp=email ) Change subject: util/cbmem: Extract devmem and common code to separate files ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic11f0659833e03324f6909fa3c1d62c36988b7b7 Gerrit-Change-Number: 86557 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Feb 2025 16:16:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/cbmem: Remove global variables in favor of function calls
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Konrad Adamczyk. Jakub "Kuba" Czapiga has posted comments on this change by Jakub "Kuba" Czapiga. ( https://review.coreboot.org/c/coreboot/+/86488?usp=email ) Change subject: util/cbmem: Remove global variables in favor of function calls ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86488?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa6e38b600c06ba72348250e865a4e8f30a31b8e Gerrit-Change-Number: 86488 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 16:16:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: util/cbmem: Extract memory mapping to common functions
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Jakub "Kuba" Czapiga, Konrad Adamczyk. Jakub "Kuba" Czapiga has posted comments on this change by Jakub "Kuba" Czapiga. ( https://review.coreboot.org/c/coreboot/+/86487?usp=email ) Change subject: util/cbmem: Extract memory mapping to common functions ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f8790842a932c4cf7717298ef43c8110dfa878 Gerrit-Change-Number: 86487 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 16:16:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: util/cbmem: Add support for CBMEM in sysfs
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Jakub "Kuba" Czapiga has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/86606?usp=email ) Change subject: util/cbmem: Add support for CBMEM in sysfs ...................................................................... util/cbmem: Add support for CBMEM in sysfs This commit adds support for CBMEM in sysfs. Useful for systems without access to /dev/mem e.g. Android. BUG=b:391874512 TEST=(devmem) cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200 TEST=modprobe cbmem; cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200 Change-Id: I527889509ffc84203be42d0160e5363c60eafd02 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> --- M util/cbmem/Makefile M util/cbmem/cbmem.c A util/cbmem/cbmem_drv.c M util/cbmem/cbmem_util.h M util/cbmem/common.c M util/cbmem/devmem_drv.c A util/cbmem/sysfs_drv.c 7 files changed, 595 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/86606/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527889509ffc84203be42d0160e5363c60eafd02 Gerrit-Change-Number: 86606 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: include/endian.h: Add 'always aligned access' support
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86609?usp=email ) Change subject: include/endian.h: Add 'always aligned access' support ...................................................................... include/endian.h: Add 'always aligned access' support RISC-V doesn't support unaligned access, so check for that before decoding and encoding. It is not perfectly performant, but still much better then invoking the misaligned exception handler every time there is a misaligned access. We can't modify our whole codebase to always do aligned access, because it is neither feasable in long term nor is fair to add that perfomance penalty onto other architectures that do support unaligned access. So this is the next best thing. On architectures that do support unaligned access the compiler will just optimize the RISCV_ENV part out and should result in the exact same binary. tested: identical binary on QEMU-aarch64 and QEMU-q35. Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d --- M .gitignore M 3rdparty/arm-trusted-firmware M src/include/endian.h 3 files changed, 27 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/86609/1 diff --git a/.gitignore b/.gitignore index e813493..de29581 100644 --- a/.gitignore +++ b/.gitignore @@ -44,3 +44,4 @@ *~ *.kate-swp *.kdev4 +.aider* diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 15e5c6c..8fb9178 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 15e5c6c91d483aa52908154cc80e48956e234232 +Subproject commit 8fb91783ffa96343dd8ebad9773d7c2055ea4496 diff --git a/src/include/endian.h b/src/include/endian.h index 552ce002..c9df74d 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -5,7 +5,9 @@ #include <arch/byteorder.h> #include <stdint.h> +#include <string.h> #include <swab.h> +#include <rules.h> #if defined(__LITTLE_ENDIAN) #define cpu_to_le64(x) ((uint64_t)(x)) @@ -67,12 +69,22 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) -/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ +/* + * be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. + * RISC-V doesn't support misaligned access so decode it byte by byte. + */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ { \ - return endian##width##_to_cpu(*(uint##width##_t *)p); \ + if (ENV_RISCV) { \ + uint##width##_t val; \ + memcpy(&val, p, sizeof(val)); \ + return endian##width##_to_cpu(val); \ + } else { \ + return endian##width##_to_cpu(*(uint##width##_t *)p); \ + } \ } + DEFINE_ENDIAN_DEC(be, 16) DEFINE_ENDIAN_DEC(be, 32) DEFINE_ENDIAN_DEC(be, 64) @@ -80,12 +92,21 @@ DEFINE_ENDIAN_DEC(le, 32) DEFINE_ENDIAN_DEC(le, 64) -/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */ +/* + * be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. + * RISC-V doesn't support misaligned access so encode it byte by byte. + */ #define DEFINE_ENDIAN_ENC(endian, width) \ static inline void endian##width##enc(void *p, uint##width##_t u) \ { \ - *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + if (ENV_RISCV) { \ + uint##width##_t val = cpu_to_##endian##width(u); \ + memcpy(p, &val, sizeof(val)); \ + } else { \ + *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + } \ } + DEFINE_ENDIAN_ENC(be, 16) DEFINE_ENDIAN_ENC(be, 32) DEFINE_ENDIAN_ENC(be, 64) -- To view, visit https://review.coreboot.org/c/coreboot/+/86609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Gerrit-Change-Number: 86609 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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coreboot-gerrit February 2025