coreboot-gerrit February 2025

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[S] Change in coreboot[main]: include/endian.h: Add 'always aligned access' support
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86609?usp=email ) Change subject: include/endian.h: Add 'always aligned access' support ...................................................................... include/endian.h: Add 'always aligned access' support RISC-V doesn't support unaligned access, so check for that before decoding and encoding. It is not perfectly performant, but still much better then invoking the misaligned exception handler every time there is a misaligned access. We can't modify our whole codebase to always do aligned access, because it is neither feasable in long term nor is fair to add that perfomance penalty onto other architectures that do support unaligned access. So this is the next best thing. On architectures that do support unaligned access the compiler will just optimize the RISCV_ENV part out and should result in the exact same binary. tested: identical binary on QEMU-aarch64 and QEMU-q35. Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d --- M .gitignore M 3rdparty/arm-trusted-firmware M src/include/endian.h 3 files changed, 27 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/86609/1 diff --git a/.gitignore b/.gitignore index e813493..de29581 100644 --- a/.gitignore +++ b/.gitignore @@ -44,3 +44,4 @@ *~ *.kate-swp *.kdev4 +.aider* diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 15e5c6c..8fb9178 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 15e5c6c91d483aa52908154cc80e48956e234232 +Subproject commit 8fb91783ffa96343dd8ebad9773d7c2055ea4496 diff --git a/src/include/endian.h b/src/include/endian.h index 552ce002..c9df74d 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -5,7 +5,9 @@ #include <arch/byteorder.h> #include <stdint.h> +#include <string.h> #include <swab.h> +#include <rules.h> #if defined(__LITTLE_ENDIAN) #define cpu_to_le64(x) ((uint64_t)(x)) @@ -67,12 +69,22 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) -/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ +/* + * be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. + * RISC-V doesn't support misaligned access so decode it byte by byte. + */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ { \ - return endian##width##_to_cpu(*(uint##width##_t *)p); \ + if (ENV_RISCV) { \ + uint##width##_t val; \ + memcpy(&val, p, sizeof(val)); \ + return endian##width##_to_cpu(val); \ + } else { \ + return endian##width##_to_cpu(*(uint##width##_t *)p); \ + } \ } + DEFINE_ENDIAN_DEC(be, 16) DEFINE_ENDIAN_DEC(be, 32) DEFINE_ENDIAN_DEC(be, 64) @@ -80,12 +92,21 @@ DEFINE_ENDIAN_DEC(le, 32) DEFINE_ENDIAN_DEC(le, 64) -/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */ +/* + * be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. + * RISC-V doesn't support misaligned access so encode it byte by byte. + */ #define DEFINE_ENDIAN_ENC(endian, width) \ static inline void endian##width##enc(void *p, uint##width##_t u) \ { \ - *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + if (ENV_RISCV) { \ + uint##width##_t val = cpu_to_##endian##width(u); \ + memcpy(p, &val, sizeof(val)); \ + } else { \ + *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + } \ } + DEFINE_ENDIAN_ENC(be, 16) DEFINE_ENDIAN_ENC(be, 32) DEFINE_ENDIAN_ENC(be, 64) -- To view, visit https://review.coreboot.org/c/coreboot/+/86609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Gerrit-Change-Number: 86609 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: mb/{google/zork,novacustom/mtl-h}: Use true/false for boolean
by Elyes Haouas (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Jason Nien, Martin Roth. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86608?usp=email ) Change subject: mb/{google/zork,novacustom/mtl-h}: Use true/false for boolean ...................................................................... mb/{google/zork,novacustom/mtl-h}: Use true/false for boolean enable_power_saving is a boolean so use "true" "false". Change-Id: I0f62fc2b0db3abd3f204951f15081b89e02a0754 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/mainboard/novacustom/mtl-h/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/86608/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index b1d0c0f..8740611 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -154,7 +154,7 @@ subsystemid 0x1022 0x1510 inherit device ref gpp_bridge_2 on chip drivers/generic/bayhub_lv2 - register "enable_power_saving" = "1" + register "enable_power_saving" = "true" device pci 00.0 on end end end # SD diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb index 663d694..2e5934b 100644 --- a/src/mainboard/novacustom/mtl-h/devicetree.cb +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -250,7 +250,7 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip drivers/generic/bayhub_lv2 - register "enable_power_saving" = "1" + register "enable_power_saving" = "true" device pci 00.0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f62fc2b0db3abd3f204951f15081b89e02a0754 Gerrit-Change-Number: 86608 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/generic/bayhub: Use boolean for power_saving
by Elyes Haouas (Code Review) 26 Feb '25

26 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86607?usp=email ) Change subject: drivers/generic/bayhub: Use boolean for power_saving ...................................................................... drivers/generic/bayhub: Use boolean for power_saving Change-Id: I7cc89989296b48e20b41e6ff06570a9d30bfc114 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/generic/bayhub/chip.h M src/mainboard/google/kahlee/variants/baseboard/devicetree.cb M src/mainboard/google/kahlee/variants/nuwani/overridetree.cb M src/mainboard/google/kahlee/variants/treeya/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 6 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/86607/1 diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h index 82fe670..e43bf5f0 100644 --- a/src/drivers/generic/bayhub/chip.h +++ b/src/drivers/generic/bayhub/chip.h @@ -9,8 +9,8 @@ * Bayhub BG720 PCI to eMMC bridge */ struct drivers_generic_bayhub_config { - /* 1 to enable power-saving mode, 0 to disable */ - int power_saving; + /* enable/disable power-saving mode */ + bool power_saving; /* When set, disables programming HS200 mode */ bool disable_hs200_mode; diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 4deac2b..6176b69 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -20,7 +20,7 @@ device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_3 on chip drivers/generic/bayhub - register "power_saving" = "1" + register "power_saving" = "true" device pci 00.0 on end end end diff --git a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb index f53a672..c618542 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb @@ -40,7 +40,7 @@ device domain 0 on device ref gpp_bridge_3 on chip drivers/generic/bayhub - register "power_saving" = "1" + register "power_saving" = "true" register "vih_tuning_value" = "0x35" device pci 00.0 on end end diff --git a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb index 011b3a1..fe9e6ac 100644 --- a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb @@ -40,7 +40,7 @@ device domain 0 on device ref gpp_bridge_3 on chip drivers/generic/bayhub - register "power_saving" = "1" + register "power_saving" = "true" register "vih_tuning_value" = "0x35" device pci 00.0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b521763..75e4896 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -350,7 +350,7 @@ device ref pcie_rp13 on # x4 lanes chip drivers/generic/bayhub - register "power_saving" = "1" + register "power_saving" = "true" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d47e183..8f66c40 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -370,7 +370,7 @@ end device ref pcie_rp9 on chip drivers/generic/bayhub - register "power_saving" = "1" + register "power_saving" = "true" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" @@ -382,7 +382,7 @@ device ref pcie_rp13 on # x4 lanes chip drivers/generic/bayhub - register "power_saving" = "1" + register "power_saving" = "true" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" -- To view, visit https://review.coreboot.org/c/coreboot/+/86607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cc89989296b48e20b41e6ff06570a9d30bfc114 Gerrit-Change-Number: 86607 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: util/cbmem: Add support for CBMEM in sysfs
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Jakub "Kuba" Czapiga has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/86606?usp=email ) Change subject: util/cbmem: Add support for CBMEM in sysfs ...................................................................... util/cbmem: Add support for CBMEM in sysfs This commit adds support for CBMEM in sysfs. Useful for systems without access to /dev/mem e.g. Android. BUG=b:391874512 TEST=(devmem) cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200 TEST=modprobe cbmem; cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200 Change-Id: I527889509ffc84203be42d0160e5363c60eafd02 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> --- M util/cbmem/Makefile M util/cbmem/cbmem.c A util/cbmem/cbmem_drv.c M util/cbmem/cbmem_util.h M util/cbmem/common.c M util/cbmem/devmem_drv.c A util/cbmem/sysfs_drv.c 7 files changed, 592 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/86606/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527889509ffc84203be42d0160e5363c60eafd02 Gerrit-Change-Number: 86606 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: util/cbmem: Add support for CBMEM in sysfs
by Jakub "Kuba" Czapiga (Code Review) 26 Feb '25

26 Feb '25

Jakub "Kuba" Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86606?usp=email ) Change subject: util/cbmem: Add support for CBMEM in sysfs ...................................................................... util/cbmem: Add support for CBMEM in sysfs This commit adds support for CBMEM in sysfs. Useful for systems without access to /dev/mem e.g. Android. BUG=b:391874512 TEST=(devmem) cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200 TEST=modprobe cbmem; cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200 Change-Id: I527889509ffc84203be42d0160e5363c60eafd02 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> --- M util/cbmem/cbmem.c A util/cbmem/cbmem_drv.c M util/cbmem/cbmem_util.h M util/cbmem/common.c M util/cbmem/devmem_drv.c A util/cbmem/sysfs_drv.c 6 files changed, 591 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/86606/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1d8c9ac..6a4bb44 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -144,13 +144,13 @@ struct lb_tsc_info *tsc_info; size_t size; - if (cbmem_devmem_get_lb_table_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size)) { + if (cbmem_drv_get_lb_table_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size)) { fprintf(stderr, "Failed to get coreboot table TSC INFO entry.\n"); goto end; } tsc_freq_khz = tsc_info->freq_khz; - cbmem_devmem_free_entry((uint8_t *)tsc_info); + cbmem_drv_free_entry((uint8_t *)tsc_info); end: already_checked = true; return tsc_freq_khz; @@ -316,7 +316,7 @@ uint8_t *tst_buf; size_t tst_buf_size; - if (cbmem_devmem_get_lb_table_entry(LB_TAG_TIMESTAMPS, &tst_buf, &tst_buf_size)) + if (cbmem_drv_get_lb_table_entry(LB_TAG_TIMESTAMPS, &tst_buf, &tst_buf_size)) return; tst_p = (const struct timestamp_table *)tst_buf; @@ -329,7 +329,7 @@ sorted_tst_p = malloc(size + sizeof(struct timestamp_entry)); if (!sorted_tst_p) { - cbmem_devmem_free_entry(tst_buf); + cbmem_drv_free_entry(tst_buf); die("Failed to allocate memory"); } memcpy(sorted_tst_p, tst_p, size); @@ -410,18 +410,18 @@ } free(sorted_tst_p); - cbmem_devmem_free_entry(tst_buf); + cbmem_drv_free_entry(tst_buf); } /* add a timestamp entry */ static void timestamp_add_now(uint32_t timestamp_id) { struct timestamp_table *tst_p; - struct mapping timestamp_mapping; + struct cbmem_drv_data drv_data; uint8_t *tst_buf; size_t tst_buf_size; - if (cbmem_devmem_map_lb_table_entry_rw(LB_TAG_TIMESTAMPS, &timestamp_mapping, &tst_buf, + if (cbmem_drv_map_cbmem_entry_rw(CBMEM_ID_TIMESTAMP, &drv_data, &tst_buf, &tst_buf_size)) return; @@ -441,7 +441,7 @@ tst_p->num_entries += 1; } - cbmem_devmem_unmap_entry(&timestamp_mapping); + cbmem_drv_unmap_entry(&drv_data, tst_buf, tst_buf_size); } static bool can_print(const uint8_t *data, size_t len) @@ -662,7 +662,7 @@ uint8_t *tclt_buf; size_t tclt_buf_size; - if (cbmem_devmem_get_lb_table_entry(LB_TAG_TPM_CB_LOG, &tclt_buf, &tclt_buf_size)) + if (cbmem_drv_get_lb_table_entry(LB_TAG_TPM_CB_LOG, &tclt_buf, &tclt_buf_size)) return; tclt_p = (const struct tpm_cb_log_table *)tclt_buf; @@ -677,7 +677,7 @@ printf(" %s [%s]\n", tce->digest_type, tce->name); } - cbmem_devmem_free_entry(tclt_buf); + cbmem_drv_free_entry(tclt_buf); } static void dump_tpm_log(void) @@ -685,10 +685,10 @@ uint8_t *buf; size_t size; - if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size) || - !cbmem_devmem_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size)) { + if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size) || + !cbmem_drv_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size)) { dump_tpm_std_log(buf, size); - cbmem_devmem_free_entry(buf); + cbmem_drv_free_entry(buf); } else dump_tpm_cb_log(); } @@ -731,7 +731,7 @@ uint8_t *console_buf; size_t console_buf_size; - if (cbmem_devmem_get_lb_table_entry(LB_TAG_CBMEM_CONSOLE, &console_buf, + if (cbmem_drv_get_lb_table_entry(LB_TAG_CBMEM_CONSOLE, &console_buf, &console_buf_size)) return; @@ -746,7 +746,7 @@ console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); - cbmem_devmem_free_entry(console_buf); + cbmem_drv_free_entry(console_buf); exit(1); } console_c[size] = '\0'; @@ -835,12 +835,12 @@ printf(BIOS_LOG_ESCAPE_RESET); free(console_c); - cbmem_devmem_free_entry(console_buf); + cbmem_drv_free_entry(console_buf); } static void dump_cbmem_hex(void) { - cbmem_devmem_hexdump_cbmem(); + cbmem_drv_hexdump_cbmem(); } static void rawdump(uint8_t *buf, size_t size) @@ -854,19 +854,19 @@ uint8_t *buf; size_t size; - if (cbmem_devmem_get_cbmem_entry(id, &buf, &size)) { + if (cbmem_drv_get_cbmem_entry(id, &buf, &size)) { fprintf(stderr, "cbmem entry id: %#x not found.\n", id); return; } rawdump(buf, size); - cbmem_devmem_free_entry(buf); + cbmem_drv_free_entry(buf); } static void dump_cbmem_toc(void) { - cbmem_devmem_toc(); + cbmem_drv_toc(); } #define COVERAGE_MAGIC 0x584d4153 @@ -905,7 +905,7 @@ ptrdiff_t phys_offset; #define phys_to_virt(x) ((void *)((uintptr_t)(x) + phys_offset)) - if (cbmem_devmem_get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, &size)) { + if (cbmem_drv_get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, &size)) { fprintf(stderr, "No coverage information found\n"); return; } @@ -916,7 +916,7 @@ fprintf(stderr, "Incorrect starting coverage magic header. Expected: %#x, Got: %#x.", COVERAGE_MAGIC, file->magic); - cbmem_devmem_free_entry(coverage); + cbmem_drv_free_entry(coverage); return; } @@ -956,7 +956,7 @@ else file = NULL; } - cbmem_devmem_free_entry(coverage); + cbmem_drv_free_entry(coverage); #undef phys_to_virt } @@ -1116,7 +1116,7 @@ print_usage(argv[0], 1); } - if (cbmem_devmem_init(!!timestamp_id)) + if (cbmem_drv_init(!!timestamp_id)) return -1; if (print_console) @@ -1146,7 +1146,7 @@ if (print_tcpa_log) dump_tpm_log(); - cbmem_devmem_terminate(); + cbmem_drv_terminate(); return 0; } diff --git a/util/cbmem/cbmem_drv.c b/util/cbmem/cbmem_drv.c new file mode 100644 index 0000000..8e882b9 --- /dev/null +++ b/util/cbmem/cbmem_drv.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <inttypes.h> +#include <stdbool.h> + +#include "cbmem_util.h" +#include "commonlib/bsd/cbmem_id.h" +#include "commonlib/coreboot_tables.h" + +enum cbmem_drv_type { + CBMEM_DRV_UNKNOWN = 0, + CBMEM_DRV_DEVMEM = 1, + CBMEM_DRV_SYSFS = 2, +} drv_type; + +int cbmem_drv_init(bool writeable) +{ + if (cbmem_sysfs_probe(cbmem_util_verbose) == 0) { + debug("Selected driver: sysfs\n"); + drv_type = CBMEM_DRV_SYSFS; + return 0; + } + + const int ret = cbmem_devmem_init(writeable); + if (ret == 0) { + debug("Selected driver: devmem\n"); + drv_type = CBMEM_DRV_DEVMEM; + } else { + fprintf(stderr, + "No suitable access methods found. /dev/mem and /systs entries missing or inaccessible.\n"); + drv_type = CBMEM_DRV_UNKNOWN; + } + return ret; +} + +void cbmem_drv_terminate(void) +{ + if (drv_type == CBMEM_DRV_DEVMEM) + cbmem_devmem_terminate(); + drv_type = CBMEM_DRV_UNKNOWN; +} + +int cbmem_drv_get_cbmem_entry(uint32_t id,uint8_t **buf_out, size_t *size_out) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + return -1; + case CBMEM_DRV_DEVMEM: + return cbmem_devmem_get_cbmem_entry(id, buf_out, size_out); + case CBMEM_DRV_SYSFS: + return cbmem_sysfs_get_cbmem_entry(id, buf_out, size_out); + } + + return -1; +} + +int cbmem_drv_get_lb_table_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + return -1; + case CBMEM_DRV_DEVMEM: + return cbmem_devmem_get_lb_table_entry(tag, buf_out, size_out); + case CBMEM_DRV_SYSFS: + return cbmem_sysfs_get_lb_table_entry(tag, buf_out, size_out); + } + + return -1; +} + +void cbmem_drv_free_entry(uint8_t *buf) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + break; + case CBMEM_DRV_DEVMEM: + cbmem_devmem_free_entry(buf); + break; + case CBMEM_DRV_SYSFS: + cbmem_sysfs_free_entry(buf); + break; + } +} + +int cbmem_drv_map_cbmem_entry_rw(uint32_t id, struct cbmem_drv_data *data, uint8_t **buf_out, size_t *size_out) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + return -1; + case CBMEM_DRV_DEVMEM: + if (id == CBMEM_ID_TIMESTAMP) + return cbmem_devmem_map_lb_table_entry_rw(LB_TAG_TIMESTAMPS, &data->mapping, buf_out, size_out); + fprintf(stderr, "/dev/mem driver does not support mapping anything except CBMEM_ID_TIMESTAMP.\n"); + return -1; + case CBMEM_DRV_SYSFS: + return cbmem_sysfs_map_cbmem_entry_rw(id, &data->file, buf_out, size_out); + } +} + +void cbmem_drv_unmap_entry(struct cbmem_drv_data *data, uint8_t *buf, size_t size) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + break; + case CBMEM_DRV_DEVMEM: + cbmem_devmem_unmap_entry(&data->mapping); + break; + case CBMEM_DRV_SYSFS: + cbmem_sysfs_unmap_entry(data->file, buf, size); + break; + } +} + +void cbmem_drv_hexdump_cbmem(void) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + break; + case CBMEM_DRV_DEVMEM: + cbmem_devmem_hexdump_cbmem(); + break; + case CBMEM_DRV_SYSFS: + cbmem_sysfs_hexdump_cbmem(); + break; + } +} + +void cbmem_drv_toc(void) +{ + switch (drv_type) { + case CBMEM_DRV_UNKNOWN: + debug("%s() called but no suitable driver found.\n", __func__); + break; + case CBMEM_DRV_DEVMEM: + cbmem_devmem_toc(); + break; + case CBMEM_DRV_SYSFS: + cbmem_sysfs_toc(); + break; + } +} diff --git a/util/cbmem/cbmem_util.h b/util/cbmem/cbmem_util.h index f82b10b..b3c9124e 100644 --- a/util/cbmem/cbmem_util.h +++ b/util/cbmem/cbmem_util.h @@ -26,7 +26,14 @@ /* Returns 0 on success, < 0 on error. mapping is cleared if successful. */ int unmap_memory(struct mapping *mapping); -void hexdump(const struct mapping *mapping, const uint8_t *buf, const int length); +/** + * Hexdump buffer. + * + * @param start_addr starting address for hexdump during printf. Does not affect buffer. + * @param buf input buffer. + * @param length buffer size. + */ +void hexdump(const unsigned long long start_addr, const uint8_t *buf, const int length); struct cbmem_id_to_name { uint32_t id; @@ -57,6 +64,84 @@ */ uint32_t lb_tag_to_cbmem_id(uint32_t tag, bool *ok_out); +/* Common driver API. Use this instead of using specific drivers manually. */ + +struct cbmem_drv_data { + union { + struct mapping mapping; /// cbmem_devmem driver + FILE *file; /// cbmem_sysfs driver + }; +}; + +/** + * Find and initialize CBMEM driver. First sysfs driver is tested. devmem driver is used as a fallback. + * + * @param writeable request a write access to CBMEM sections. + * + * @returns zero on success. + */ +int cbmem_drv_init(bool writeable); + +/** + * Terminate and cleanup the driver. **MUST** be used if cbmem_drv_init() succeeded. + */ +void cbmem_drv_terminate(void); + +/** + * Get CBMEM entry as an allocated buffer. + * + * @param id CBMEM_ID_* value. + * @param buf_out pointer to obtain allocated entry buffer. + * @param size_out size of returned buffer. + * + * @returns zero on success. + */ +int cbmem_drv_get_cbmem_entry(uint32_t id,uint8_t **buf_out, size_t *size_out); + +/** + * Get lb_table/cb_table entry as an allocated buffer. + * + * @param tag LB_TAG_* value. + * @param buf_out pointer to obtain allocated entry buffer. + * @param size_out size of returned buffer. + * + * @returns zero on success. + */ +int cbmem_drv_get_lb_table_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out); + +/** + * Free buffer allocated by cbmem_drv_get*_entry(). + */ +void cbmem_drv_free_entry(uint8_t *buf); + +/** + * Map CBMEM entry in RW mode. + * + * @param id CBMEM_ID_* value. + * @param data the driver call context data. A separate structure is needed for every new call if not unmapped first. + * @param buf_out output pointer to the mapped cbmem entry. + * @param size_out output buffer size. + * + * @returns zero on success. + */ +int cbmem_drv_map_cbmem_entry_rw(uint32_t id, struct cbmem_drv_data *data, uint8_t **buf_out, size_t *size_out); + +/** + * Unmap entry mapped by cbmem_drv_map_cbmem_entry_rw(). + * **MUST** be called if cbmem_drv_map_cbmem_entry_rw() succeeded. + * + * @param data the driver call context data. + * @param buf the mapped buffer. + * @param size size of the mapped buffer. + */ +void cbmem_drv_unmap_entry(struct cbmem_drv_data *data, uint8_t *buf, size_t size); + +/* Hexdump all cbmem entries. */ +void cbmem_drv_hexdump_cbmem(void); + +/* Print CBMEM Table of Contents */ +void cbmem_drv_toc(void); + /* API for accessing CBMEM via /dev/mem */ /** @@ -125,3 +210,34 @@ /* Print CBMEM Table of Contents */ void cbmem_devmem_toc(void); + +/* API for accessing CBMEM via sysfs entries */ + +/** + * Check if cbmem in sysfs is supported on the device. + * No driver initialization is required. + * + * @returns zero on success. + */ +int cbmem_sysfs_probe(bool verbose); + +/* @see cbmem_devmem_get_cbmem_entry() */ +int cbmem_sysfs_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t* size_out); + +/* @see cbmem_devmem_get_lb_table_entry() */ +int cbmem_sysfs_get_lb_table_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out); + +/* Free buffer returned by cbmem_sysfs_get_*_entry() */ +void cbmem_sysfs_free_entry(uint8_t *buf); + +/* @see cbmem_devmem_map_cbmem_entry_rw() */ +int cbmem_sysfs_map_cbmem_entry_rw(uint32_t id, FILE **file_out, uint8_t **buf_out, + size_t *size_out); + +void cbmem_sysfs_unmap_entry(FILE *file, uint8_t *buf, size_t size); + +/* Hexdump all cbmem entries. */ +void cbmem_sysfs_hexdump_cbmem(void); + +/* Print CBMEM Table of Contents */ +void cbmem_sysfs_toc(void); diff --git a/util/cbmem/common.c b/util/cbmem/common.c index 46d96b5..55bc156 100644 --- a/util/cbmem/common.c +++ b/util/cbmem/common.c @@ -12,7 +12,7 @@ int cbmem_util_verbose; -void hexdump(const struct mapping *mapping, const uint8_t *buf, const int length) +void hexdump(const unsigned long long start_addr, const uint8_t *buf, const int length) { int i; int all_zero = 0; @@ -29,7 +29,7 @@ } if (all_zero < 2) { - printf("%08llx:", mapping->phys + i); + printf("%08llx:", start_addr + i); for (j = 0; j < 16; j++) printf(" %02x", buf[i + j]); printf(" "); diff --git a/util/cbmem/devmem_drv.c b/util/cbmem/devmem_drv.c index 25b9154..0e2734a 100644 --- a/util/cbmem/devmem_drv.c +++ b/util/cbmem/devmem_drv.c @@ -564,7 +564,7 @@ const uint32_t id = lb_tag_to_cbmem_id(tag, &id_found); if (id_found) { - debug("lbtable/cbtable tag: %d. Found CBMEM ID equivalent: %#x\n.", tag, id); + debug("lbtable/cbtable tag: %d. Found CBMEM ID equivalent: %#x.\n", tag, id); return cbmem_devmem_get_cbmem_entry(id, buf_out, size_out); } @@ -699,7 +699,7 @@ fprintf(stderr, "Unable to map cbmem memory for hexdump.\n"); return -1; } - hexdump(&cbmem_mapping, buf, size); + hexdump(cbmem_mapping.phys, buf, size); unmap_memory(&cbmem_mapping); return 0; } diff --git a/util/cbmem/sysfs_drv.c b/util/cbmem/sysfs_drv.c new file mode 100644 index 0000000..4a025d9 --- /dev/null +++ b/util/cbmem/sysfs_drv.c @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <errno.h> +#include <stdbool.h> +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <fcntl.h> +#include <unistd.h> +#include <sys/mman.h> +#include <sys/stat.h> +#include <sys/types.h> + +#if defined(__linux__) || defined(__ANDROID__) +#include <linux/fs.h> +#include <sys/ioctl.h> +#endif + +#include <commonlib/bsd/cbmem_id.h> +#include <commonlib/bsd/ipchksum.h> +#include <commonlib/coreboot_tables.h> +#include <commonlib/helpers.h> +#include <commonlib/timestamp_serialized.h> +#include <commonlib/tpm_log_serialized.h> + +#include "cbmem_util.h" + +#define CBMEM_SYSFS_ENTRY_DIR_PATH_FMT "/sys/bus/coreboot/devices/cbmem-%x" +#define CBMEM_SYSFS_ENTRY_MEM_PATH_FMT CBMEM_SYSFS_ENTRY_DIR_PATH_FMT "/mem" +#define CBMEM_SYSFS_ENTRY_SIZE_PATH_FMT CBMEM_SYSFS_ENTRY_DIR_PATH_FMT "/size" + +static int new_cbmem_paths(uint32_t id, char **mem_path_out, char **size_path_out) +{ + if (asprintf(mem_path_out, CBMEM_SYSFS_ENTRY_MEM_PATH_FMT, id) <= 0) { + *mem_path_out = NULL; + return -1; + } + if (asprintf(size_path_out, CBMEM_SYSFS_ENTRY_SIZE_PATH_FMT, id) <= 0) { + if (*mem_path_out) { + free(*mem_path_out); + *mem_path_out = NULL; + } + *size_path_out = NULL; + return -1; + } + return 0; +} + +static int check_path(const char *path, bool verbose) +{ + struct stat st; + + if (stat(path, &st)) { + if (verbose) + fprintf(stderr, "Failed to stat file: %s. Error: %s\n", path, + strerror(errno)); + return -1; + } + + if (S_ISDIR(st.st_mode)) { + if (verbose) + fprintf(stderr, + "CBMEM sysfs structure is incorrect. Path %s expected to be a readable file.\n", + path); + return -1; + } + + if (access(path, R_OK)) { + if (verbose) + fprintf(stderr, "No read permissions for file: %s. Error: %s\n", path, + strerror(errno)); + return -1; + } + + return 0; +} + +static int check_paths(const char *mem_path, const char *size_path, bool verbose) +{ + const int ret = check_path(mem_path, verbose); + if (check_path(size_path, verbose)) + return -1; + return ret; +} + +int cbmem_sysfs_probe(bool verbose) +{ + int ret = 0; + char *cbtable_mem_path = NULL; + char *cbtable_size_path = NULL; + + /* cbtable/lbtable should always exist */ + if (new_cbmem_paths(CBMEM_ID_CBTABLE, &cbtable_mem_path, &cbtable_size_path)) { + if (verbose) + fprintf(stderr, "Failed to allocate cbmem paths.\n"); + return -1; + } + + if (check_paths(cbtable_mem_path, cbtable_size_path, verbose)) + ret = -1; + + free(cbtable_size_path); + free(cbtable_mem_path); + return ret; +} + +static int read_cbmem_entry(uint32_t id, FILE **file_out, uint8_t **buf_out, size_t *size_out) +{ + int ret = -1; + char *mem_path = NULL; + char *size_path = NULL; + + if (new_cbmem_paths(id, &mem_path, &size_path)) { + fprintf(stderr, "Failed to allocate cbmem paths.\n"); + return -1; + } + + if (check_paths(mem_path, size_path, true)) { + goto end; + } + + FILE *size_file = fopen(size_path, "r"); + if (!size_file) { + fprintf(stderr, "Unable to open CBMEM entry size file: %s\n", size_path); + goto end; + } + + uint32_t entry_size = 0; + if (fscanf(size_file, "%i", &entry_size) != 1) { + fprintf(stderr, "Failed to parse cbmem entry size from path: %s\n", size_path); + fclose(size_file); + goto end; + } + fclose(size_file); + + *file_out = fopen(mem_path, "rb+"); + if (!file_out) { + fprintf(stderr, "Unable to open CBMEM entry mem file: %s\n", mem_path); + goto end; + } + + *buf_out = calloc(1, entry_size); + if (!*buf_out) { + fprintf(stderr, "Failed to allocate buffer for CBMEM entry %#x.\n", id); + goto end; + } + + fread(*buf_out, entry_size, 1, *file_out); + + if (ferror(*file_out)) { + fprintf(stderr, "Failed to read CBMEM entry %#x contents from %s.\n", id, + mem_path); + fclose(*file_out); + free(*buf_out); + *buf_out = NULL; + goto end; + } + + *size_out = entry_size; + ret = 0; +end: + free(mem_path); + free(size_path); + return ret; +} + +int cbmem_sysfs_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out) +{ + FILE *f = NULL; + + if (read_cbmem_entry(id, &f, buf_out, size_out)) + return -1; + + fclose(f); + return 0; +} + +int cbmem_sysfs_get_lb_table_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out) +{ + uint8_t *cbtable; + size_t size; + bool id_found = false; + const uint32_t id = lb_tag_to_cbmem_id(tag, &id_found); + + if (id_found) { + debug("lbtable/cbtable tag: %d. Found CBMEM ID equivalent: %#x.\n", tag, id); + return cbmem_sysfs_get_cbmem_entry(id, buf_out, size_out); + } + + if (cbmem_sysfs_get_cbmem_entry(CBMEM_ID_CBTABLE, &cbtable, &size)) { + fprintf(stderr, "Unable to find coreboot table CBMEM entry.\n"); + return -1; + } + + const struct lb_record *lbr_p; + bool tag_found = false; + for (size_t i = 0; i < size; i += lbr_p->size) { + lbr_p = (const struct lb_record *)(&cbtable[i]); + if (lbr_p->tag == tag) { + tag_found = true; + break; + } + } + + if (!tag_found) { + fprintf(stderr, "coreboot table entry %#x not found.\n", tag); + return -1; + } + + debug("coreboot table entry %#x found.\n", tag); + + *buf_out = malloc(lbr_p->size); + if (!*buf_out) { + fprintf(stderr, "Unable to allocate memory for coreboot table entry %#x", tag); + return -1; + } + *size_out = lbr_p->size; + memcpy(*buf_out, lbr_p, lbr_p->size); + cbmem_sysfs_free_entry(cbtable); + + return 0; +} + +void cbmem_sysfs_free_entry(uint8_t *buf) +{ + free(buf); +} + +int cbmem_sysfs_map_cbmem_entry_rw(uint32_t id, FILE **file_out, uint8_t **buf_out, size_t *size_out) +{ + return read_cbmem_entry(id, file_out, buf_out, size_out); +} + +void cbmem_sysfs_unmap_entry(FILE *file, uint8_t *buf, size_t size) +{ + fseek(file, 0, SEEK_SET); + fwrite(buf, size, 1, file); + if (ferror(file)) + fprintf(stderr, "Failed to write back. Error: %s\n", strerror(errno)); + fclose(file); +} + +static void foreach_cbmem_entry(void (*fn)(const struct lb_cbmem_entry *lbe, int idx)) +{ + uint8_t *cbtable; + size_t size; + if (cbmem_sysfs_get_cbmem_entry(CBMEM_ID_CBTABLE, &cbtable, &size)) { + fprintf(stderr, "Unable to find coreboot table CBMEM entry.\n"); + return; + } + + const struct lb_record *lbr_p; + for (size_t i = 0; i < size; i += lbr_p->size) { + lbr_p = (const struct lb_record *)(&cbtable[i]); + if (lbr_p->tag != LB_TAG_CBMEM_ENTRY) + continue; + + const struct lb_cbmem_entry *lbe = (const struct lb_cbmem_entry *)lbr_p; + fn(lbe, i); + } + + cbmem_sysfs_free_entry(cbtable); +} + +static void hexdump_fn(const struct lb_cbmem_entry *lbe, int idx) +{ + (void)idx; + printf("# CBMEM entry id: %#x\n", lbe->id); + + uint8_t *buf = NULL; + size_t size = 0; + + if (cbmem_sysfs_get_cbmem_entry(lbe->id, &buf, &size)) + return; + + hexdump(0, buf, size); + + cbmem_sysfs_free_entry(buf); +} + +void cbmem_sysfs_hexdump_cbmem(void) +{ + foreach_cbmem_entry(hexdump_fn); +} + +static void toc_fn(const struct lb_cbmem_entry *lbe, int idx) +{ + cbmem_print_entry(idx, lbe->id, lbe->address, lbe->entry_size); +} + +void cbmem_sysfs_toc(void) +{ + printf("CBMEM table of contents:\n"); + printf(" %-20s %-8s %-8s %-8s\n", "NAME", "ID", "START", "LENGTH"); + foreach_cbmem_entry(toc_fn); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527889509ffc84203be42d0160e5363c60eafd02 Gerrit-Change-Number: 86606 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub "Kuba" Czapiga <czapiga(a)google.com>

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[M] Change in coreboot[main]: mb/google/poppy: Use <spd.h>
by Elyes Haouas (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Jeff Daly, Vanessa Eusebio. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82242?usp=email ) Change subject: mb/google/poppy: Use <spd.h> ...................................................................... Patch Set 9: -Code-Review (1 comment) File src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/82242/comment/73a2e878_36ae7760?us… : PS9, Line 28: enum spd_memory_type type; > sounds wrong Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id07a09b1be83682a44d85da15cd2c0787ad9beb1 Gerrit-Change-Number: 82242 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 15:06:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h>
by Elyes Haouas (Code Review) 26 Feb '25

26 Feb '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82315?usp=email ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> ...................................................................... intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h> Use already defined macros in <spd.h> and <dram/ddr3.h>. TEST=Built purism/librem_bdw (Librem 13 v1) with BUILD_TIMELESS=1, no change in output ROM. Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82315 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/broadwell/spd.c 1 file changed, 13 insertions(+), 18 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/broadwell/spd.c b/src/soc/intel/broadwell/spd.c index 1af66f1..419334d 100644 --- a/src/soc/intel/broadwell/spd.c +++ b/src/soc/intel/broadwell/spd.c @@ -2,22 +2,17 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> +#include <spd.h> #include <string.h> #include <types.h> -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 #define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -#define SPD_LEN 256 static void print_spd_info(uint8_t spd[]) { @@ -28,7 +23,7 @@ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; @@ -40,21 +35,21 @@ /* Module type */ printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: + switch (spd[SPD_MEMORY_TYPE]) { + case SPD_MEMORY_TYPE_SDRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_MEMORY_TYPE_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]); break; } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN); + spd_name[SPD_DDR3_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " @@ -79,15 +74,15 @@ if (!spd_file) die("SPD data not found."); - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); - if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spdi->spd_index = 0; } - uint8_t *const spd = spd_file + (spdi->spd_index * SPD_LEN); + uint8_t *const spd = spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3); /* Make sure a valid SPD was found */ if (spd[0] == 0) @@ -97,6 +92,6 @@ for (size_t i = 0; i < ARRAY_SIZE(spdi->addresses); i++) { if (spdi->addresses[i] == SPD_MEMORY_DOWN) - memcpy(pei_data->spd_data[i / 2][i % 2], spd, SPD_LEN); + memcpy(pei_data->spd_data[i / 2][i % 2], spd, SPD_SIZE_MAX_DDR3); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/82315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8 Gerrit-Change-Number: 82315 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Add missing minimum D-state for SMBUS
by Sean Rhodes (Code Review) 26 Feb '25

26 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86605?usp=email ) Change subject: soc/intel/meteorlake: Add missing minimum D-state for SMBUS ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86605?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73f84c09bece297194813202f17666741ad33d3a Gerrit-Change-Number: 86605 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 26 Feb 2025 14:06:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: src/cpu/intel/car/romstage: Refactor stack guard code in romstage
by Name of user not set (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Name of user not set #1005756, Patrick Rudolph, Shuo Liu. Hello Intel coreboot Reviewers, Patrick Rudolph, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86562?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: src/cpu/intel/car/romstage: Refactor stack guard code in romstage ...................................................................... src/cpu/intel/car/romstage: Refactor stack guard code in romstage Factor out stack_guard_set() and stack_guard_check(). It's just for improving readability. :) Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Signed-off-by: melongmelong <knw0507(a)naver.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 28 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86562/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I754e422c0023cd7824dd6109f031239756acff4b Gerrit-Change-Number: 86562 Gerrit-PatchSet: 5 Gerrit-Owner: Name of user not set #1005756 Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Name of user not set #1005756

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Save HW protect temperature to SRAM
by Yidi Lin (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Zhaoqing Jiu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86551?usp=email ) Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/thermal_sram.c: https://review.coreboot.org/c/coreboot/+/86551/comment/daecaa33_62be28db?us… : PS2, Line 68: write32 > there will be compile error if use write32p Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 Gerrit-Change-Number: 86551 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 12:34:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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