coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: brya: Add support to get sku ID
by Subrata Banik (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Aamir Bohra, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Aamir Bohra. ( https://review.coreboot.org/c/coreboot/+/86599?usp=email ) Change subject: brya: Add support to get sku ID ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I am implementing the sku_id defined in https://github.com/coreboot/coreboot/blob/… [View More]4985079b161f425137ee9e07ff86ddad1… > > This gets used in setting the SKUID in coreboot table: https://github.com/coreboot/coreboot/blob/4985079b161f425137ee9e07ff86ddad1… > > https://github.com/coreboot/coreboot/blob/4985079b161f425137ee9e07ff86ddad1… > > Some of ARM based boards rely on the ADC pins for SKU ID information, the sku_id function allows to define underlying mechanism for reading SKU ID across different mainboards. in that case, can you implement sku_id() inside cros_ec file itself so you don't need to implement per board basic ? and use some smart method to call into ADC PIN when CONFIG_SKUID_VIA_CHROMEEC vs CONFIG_SKUID_VIA_ADC_PIN. In any case, you need a better commit msg, the current code doesn't convey what you are trying to achieve -- To view, visit https://review.coreboot.org/c/coreboot/+/86599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie55a9d83871f41e191574e554fe7d287c1ee60bd Gerrit-Change-Number: 86599 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Comment-Date: Wed, 26 Feb 2025 17:34:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Aamir Bohra <aamirbohra(a)google.com> [View Less]

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[XS] Change in coreboot[main]: soc/amd/common/cpu: Don't assume endianness of host
by Fred Reitberger (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Arthur Heymans, Elyes Haouas, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Raul Rangel. Fred Reitberger has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/75441?usp=email ) Change subject: soc/amd/common/cpu: Don't assume endianness of host ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Would using `od` with the `--endian … [View More]

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[S] Change in coreboot[main]: brya: Add support to get sku ID
by Aamir Bohra (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Aamir Bohra, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Aamir Bohra has posted comments on this change by Aamir Bohra. ( https://review.coreboot.org/c/coreboot/+/86599?usp=email ) Change subject: brya: Add support to get sku ID ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > sorry, unable to follow why can't we call into `google_chromeec_xxx` API directly and … [View More]

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Maximilian Brune (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Tim Chu. Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > It's not about DRAM,… [View More]

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[XS] Change in coreboot[main]: soc/amd/glinda: Enable x86_64 support
by Matt DeVillier (Code Review) 26 Feb '25

26 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86581?usp=email ) Change subject: soc/amd/glinda: Enable x86_64 support ...................................................................... soc/amd/glinda: Enable x86_64 support The code compiles and works fine in x86_64. Thus allow the user to use x86_64. TEST: Booted on amd/birman+ to OS using EDK2 as payload. Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6 Signed-off-by: Patrick Rudolph <… [View More]

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[S] Change in coreboot[main]: cpu/x86/64bit: Allow to map more of the address space
by Matt DeVillier (Code Review) 26 Feb '25

26 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86580?usp=email ) Change subject: cpu/x86/64bit: Allow to map more of the address space ...................................................................... cpu/x86/64bit: Allow to map more of the address space On AMD platforms the SPI flash can be accessed using the ROM3 mapping in upper MMIO space. To reach the MMIO window the default page tables must be extended to cover the address by default. Add … [View More]support for a SoC specific default address space being used on x86_64, where the default of 4GiB/512GiB remains. The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option. Used in the following patch to use ROM3 mapping on AMD platforms. TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64 TEST: x86_64 still works on qemu/q35. Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86580 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/Kconfig 3 files changed, 31 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 1297296..5b10b10 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -20,16 +20,21 @@ .global PML4E .align 4096 PML4E: -.quad _GEN_DIR(PDPT) - -.align 4096 -PDT: /* identity map 2MiB pages */ -.rept 2048 -.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) +/* For every 512GiB generate a pointer to the corresponding PDPT */ +.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 +.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */ .endr .align 4096 -PDPT: /* Point to PDT */ -.rept 4 -.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) +PDT: +/* For every 2MiB generate a page entry. In one GiB there are 512 pages. */ +.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB +.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) /* identity map 2MiB page */ +.endr + +.align 4096 +PDPT: +/* For every 1GiB generate a pointer to the corresponding PDT */ +.rept CONFIG_CPU_PT_ROM_MAP_GB +.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) /* Point to PDT */ .endr diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 42cdfb1..b1f4433 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -20,10 +20,14 @@ .global PML4E .align 4096 PML4E: -.quad _GEN_DIR(PDPT) +/* For every 512GiB generate a pointer to the corresponding PDPT */ +.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 +.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */ +.endr .align 4096 -PDPT: /* identity map 1GiB pages * 512 */ -.rept 512 -.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) +PDPT: +/* For every 1GiB generate a page entry */ +.rept CONFIG_CPU_PT_ROM_MAP_GB +.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) /* identity map 1GiB page */ .endr diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 828c0f9..15c884e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -159,6 +159,15 @@ Select this option from boards/SoCs that do not support the Page1GB CPUID feature (CPUID.80000001H:EDX.bit26). +config CPU_PT_ROM_MAP_GB + int + default 4 if NEED_SMALL_2MB_PAGE_TABLES + default 512 + help + GiB of the lower address space to identity map when using x86_64 + page tables in ROM. Higher values require more space in SPI flash. + SoC can overwrite the value if necessary. + config SMM_ASEG bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/86580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Gerrit-Change-Number: 86580 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[S] Change in coreboot[main]: soc/riscv/ucb: Switch to FDT parsing to get memory size
by Matt DeVillier (Code Review) 26 Feb '25

26 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86588?usp=email ) Change subject: soc/riscv/ucb: Switch to FDT parsing to get memory size ...................................................................... soc/riscv/ucb: Switch to FDT parsing to get memory size Currently, coreboot tries to manually probe the memory for the Spike target as part of the SOC_UCB_RISCV target. However, Spike already passes a pointer to the device tree, so use it instead to … [View More]get the memory size (like qemu-riscv does). TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf) Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43 Signed-off-by: joel.bueno <joel.bueno(a)openchip.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86588 Reviewed-by: Carlos López <carlos.lopezr4096(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/ucb/riscv/Kconfig M src/soc/ucb/riscv/cbmem.c 2 files changed, 10 insertions(+), 1 deletion(-) Approvals: Maximilian Brune: Looks good to me, approved Carlos López: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index bd0945e..e8a8d37 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -9,6 +9,7 @@ select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select RISCV_USE_ARCH_TIMER + select FLATTENED_DEVICE_TREE bool default n diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 5c423a0..ff3f5db 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <commonlib/device_tree.h> +#include <mcall.h> uintptr_t cbmem_top_chipset(void) { - return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + uint64_t top; + + top = fdt_get_memory_top((void *)HLS()->fdt); + ASSERT_MSG(top, "Failed reading memory range from FDT"); + + return MIN(top, (uint64_t)4 * GiB - 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43 Gerrit-Change-Number: 86588 Gerrit-PatchSet: 4 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> [View Less]

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[XS] Change in coreboot[main]: mb/google/brya/var/agah: Remove the AGAH DPTF OEM variant
by Matt DeVillier (Code Review) 26 Feb '25

26 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86493?usp=email ) Change subject: mb/google/brya/var/agah: Remove the AGAH DPTF OEM variant ...................................................................... mb/google/brya/var/agah: Remove the AGAH DPTF OEM variant Because the AGAH EC code is based on monitoring adapter current to choose the corresponding DPTF OEM variable table, but not every project follows this design. Based on the comment below, … [View More]the AGAH EC code was removed in 2023, so remove the AGAH DPTF OEM variant, allowing each OEM to adjust in EC ASL accordingly. BUG=b:394177292 BRANCH=None TEST=None Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86493 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 436207c..8e241fc 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -379,14 +379,6 @@ Printf ("EC: THROTTLE START") \_TZ.THRT (1) #endif - -#ifdef DPTF_ENABLE_OEM_VARIABLES - Local0 = ToInteger(EOVD) & EC_OEM_VARIABLE_DATA_MASK - \_SB.DPTF.ODUP(0, Local0) - Local0 = \_SB.DPTF.ODGT(0) - \_SB.DPTF.ODVP() - Notify (\_SB.DPTF, INT3400_ODVP_CHANGED) -#endif } // Throttle Stop -- To view, visit https://review.coreboot.org/c/coreboot/+/86493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8 Gerrit-Change-Number: 86493 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> [View Less]

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[M] Change in coreboot[main]: mb/starlabs/starbook/kbl: Update the verb table
by Matt DeVillier (Code Review) 26 Feb '25

26 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86594?usp=email ) Change subject: mb/starlabs/starbook/kbl: Update the verb table ...................................................................... mb/starlabs/starbook/kbl: Update the verb table Use the newer verb for the ALC2669-VB6 from `starbook/mtl`, as the current verb table failed to detect headphones being connected. Change-Id: Iaa50c6622f3ca75fbeff96300e08eb00e071c8b6 Signed-off-by: Sean … [View More]Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86594 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c 1 file changed, 82 insertions(+), 34 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c index 9c02389..7da0991 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c @@ -1,73 +1,121 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/azalia_device.h> +#include <stdint.h> + +#define DMIC 0x12 +#define SPEAKERS 0x14 +#define HEADPHONE 0x15 +#define MONO 0x17 +#define MIC1 0x18 +#define MIC2 0x19 +#define LINE1 0x1a +#define LINE2 0x1b +#define PC_BEEP 0x1d +#define S_PDIF 0x1e const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ - 0x10ec10d0, /* Subsystem ID */ - 18, /* Number of jacks (NID entries) */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x10ec10d0, /* Subsystem ID */ + 18, /* Number of verb entries */ /* Reset Codec First */ AZALIA_RESET(0x1), - /* HDA Codec Subsystem ID Verb-table */ - AZALIA_SUBVENDOR(0, 0x10ec10d0), + /* HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x1e507038), - /* Pin Widget Verb-table */ - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x90a61120), - AZALIA_PIN_CFG(0, 0x14, 0x90171110), - AZALIA_PIN_CFG(0, 0x15, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x17, 0x411111F0), - AZALIA_PIN_CFG(0, 0x18, 0x04AB1020), - AZALIA_PIN_CFG(0, 0x19, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, DMIC, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_TOP, \ + AZALIA_MIC_IN, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 3, \ + 0 \ + )), - /* ALC269 Default 1 */ + AZALIA_PIN_CFG(0, SPEAKERS, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_FRONT, \ + AZALIA_SPEAKER, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 1, \ + 0 \ + )), + AZALIA_PIN_CFG(0, HEADPHONE, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_HP_OUT, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 2, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, MIC1, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_MIC_IN, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 4, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE1, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, S_PDIF, AZALIA_PIN_CFG_NC(0)), + 0x02050018, - 0x02043984, - 0x0205001C, - 0x02040800, + 0x02040184, - /* ALC269 Default 2 */ + 0x0205001C, + 0x02044b00, + 0x02050024, 0x02040000, + 0x02050004, 0x02040080, - /* ALC269 Default 3 */ 0x02050008, - 0x02040300, + 0x02040000, + 0x0205000C, 0x02043F00, - /* ALC269 Default 4 */ - 0x02050015, - 0x02048002, 0x02050015, 0x02048002, - /* ALC269 Default 5 */ + 0x02050015, + 0x02048002, + 0x00C37080, 0x00270610, 0x00D37080, 0x00370610, - 0x8086280b, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ + 0x8086280d, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560010), - AZALIA_PIN_CFG(2, 0x07, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), }; -const u32 pc_beep_verbs[] = {}; +const u32 pc_beep_verbs[] = { +}; AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/86594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa50c6622f3ca75fbeff96300e08eb00e071c8b6 Gerrit-Change-Number: 86594 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Use default turbo ratio
by Jérémy Compostella (Code Review) 26 Feb '25

26 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86604?usp=email ) Change subject: soc/intel/xeon_sp/spr: Use default turbo ratio ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/… [View More]

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coreboot-gerrit February 2025