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Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses
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Patch Set 6:
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Change subject: cpu/x86/64bit: Install extended page tables in BSS
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85806/comment/8de8d37c_bc122cb9?us… :
PS6, Line 9: On Intel 14nm Xeon-SP every processor supports 1TiB of DRAM. Since
Maybe more accurate - Starting from Intel 14nm
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Change subject: cpu/x86/64bit: Install extended page tables in BSS
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Patch Set 6:
(1 comment)
File src/cpu/x86/64bit/mmu.c:
https://review.coreboot.org/c/coreboot/+/85806/comment/c9a4c802_430945f3?us… :
PS6, Line 19: #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (uintptr_t)(a))
these definitions are used multiple places in the code base, maybe another patch could be created to merge the definitions into one later.
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