coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email ) Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 3: Code-Review+2 (2 comments) File src/soc/amd/cezanne/chipset.cb: https://review.coreboot.org/c/coreboot/+/86272/comment/8060ee02_1455f999?us… : PS2, Line 90: xgbe_0 > is xgbe_0 and xgbe_1 always disabled by FSP? the two xgbe controllers can't be used on the silicon this was originally tested with, so i'd guess that they just can't show up showed up in that case. if some out of tree board uses those, it needs to make sure to enable them. this patch is about the bridges though. if we end up adding upds for this, that's something for another patch https://review.coreboot.org/c/coreboot/+/86272/comment/51aa5f73_7d634ca0?us… : PS2, Line 96: i2s_ac97 > is i2s_ac97 always disabled by FSP? uh, that's a good question to which i don't know the answer. i'd say that it'll probably be fine to have it disabled here -- To view, visit https://review.coreboot.org/c/coreboot/+/86272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Gerrit-Change-Number: 86272 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:01:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Enable low-battery indicator support
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86316?usp=email ) Change subject: soc/intel/alderlake: Enable low-battery indicator support ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444 Gerrit-Change-Number: 86316 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:00:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/alderlake: Handle critical low battery early in romstage
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86227?usp=email ) Change subject: soc/intel/alderlake: Handle critical low battery early in romstage ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2 Gerrit-Change-Number: 86227 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:00:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common/reset: Add low battery indicator delay
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86419?usp=email ) Change subject: soc/intel/common/reset: Add low battery indicator delay ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/reset.c: https://review.coreboot.org/c/coreboot/+/86419/comment/fb0cdf94_f1f88bf0?us… : PS1, Line 29: if (CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)) { I don't think this needs to be checked here? This function is only called by code belonging to that feature anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/86419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56bff7af8c9ddd9b34d19d2c0b6a76172eff3f31 Gerrit-Change-Number: 86419 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add low battery indicator screen
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86225?usp=email ) Change subject: drivers/intel/fsp2_0: Add low battery indicator screen ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:58:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common: Add low battery shutdown function
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86361?usp=email ) Change subject: soc/intel/common: Add low battery shutdown function ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/reset.c: https://review.coreboot.org/c/coreboot/+/86361/comment/4e587a56_00dec8b8?us… : PS4, Line 27: poweroff(); > > > Wait, where did the rest of this function go? Who is doing the delay and the elog entry now? (If […] Is there a reason you can't squash those two CLs? It's easier to review the full implementation right away. -- To view, visit https://review.coreboot.org/c/coreboot/+/86361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4 Gerrit-Change-Number: 86361 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:56:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: soc/amd/phoenix/chipset_*: Enable gpp_bridge_[a/b/c] by default
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86271?usp=email ) Change subject: soc/amd/phoenix/chipset_*: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic226fd93b431467c7fa3a53140102ff4fd327f40 Gerrit-Change-Number: 86271 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:56:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Maximilian Brune, Patrick Rudolph. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86270?usp=email ) Change subject: soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44 Gerrit-Change-Number: 86270 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:55:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/google/chromeec: Implement early power off support
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Karthik Ramasubramanian, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86379?usp=email ) Change subject: ec/google/chromeec: Implement early power off support ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/86379/comment/87501547_de0cde9b?us… : PS4, Line 1675: void google_chromeec_do_early_poweroff(void) Just rename this function to `platform_do_early_poweroff()`, it's otherwise unneeded. -- To view, visit https://review.coreboot.org/c/coreboot/+/86379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c634d69de36fe8bdb6a61c121e321d3626ac3ff Gerrit-Change-Number: 86379 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:55:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84500?usp=email ) Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... mb/amd/birman_plus: Update devicetree The devicetree was still a copy of a previous mainboard. This patch updates the devicetree for the birman_plus mainboard. Birman plus is an AMD reference board. sources: - document #58168 Rev 1.01 "Birman+ User Guide" - birman+ schematic Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84500 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/devicetree_glinda.cb 2 files changed, 43 insertions(+), 12 deletions(-) Approvals: Felix Held: Looks good to me, approved Ana Carolina Cabral: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 9794383..91e39bf 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -6,6 +6,7 @@ select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE + select DRIVERS_I2C_GENERIC select MAINBOARD_HAS_CHROMEOS select PCIEXP_ASPM select PCIEXP_CLK_PM diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 5a7fd00..07642aa 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -# TODO: Update for birmanplus - chip soc/amd/glinda register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, @@ -178,20 +176,40 @@ .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, }" - register "gpp_clk_config[0]" = "GPP_CLK_REQ" - register "gpp_clk_config[1]" = "GPP_CLK_REQ" - register "gpp_clk_config[2]" = "GPP_CLK_OFF" - register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1 + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0 + register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN + register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD + register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE device domain 0 on device ref iommu on end - device ref gpp_bridge_2_1 on end # GBE - device ref gpp_bridge_2_2 on end # WIFI - device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # NVME SSD0 + device ref gpp_bridge_2_2 on end # SD + device ref gpp_bridge_2_3 on end # WLAN + device ref gpp_bridge_2_4 on end # GBE + device ref gpp_bridge_2_5 on end # WWAN + device ref gpp_bridge_3_1 on end # PCIe x4/x8 (ENABLE_SSD1_BIRMANPLUS) + device ref gpp_bridge_3_2 on end # NVME SSD1 (ENABLE_SSD1_BIRMANPLUS) + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) device ref crypto on end # Crypto Coprocessor + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port7 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end device ref acp on end # Audio Processor (ACP) end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C @@ -216,9 +234,13 @@ chip drivers/usb/acpi device ref usb2_port5 on end end + chip drivers/usb/acpi + device ref usb2_port6 on end + end end end end + device ref usb4_xhci_0 on chip drivers/usb/acpi device ref usb4_xhci_0_root_hub on @@ -232,7 +254,6 @@ end end device ref usb4_xhci_1 on - ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device ref usb4_xhci_1_root_hub on @@ -250,8 +271,17 @@ device ref i2c_0 on end device ref i2c_1 on end - device ref i2c_2 on end + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "desc" = ""TMP420 3 channel temperature sensor"" + register "uid" = "1" + register "compat_string" = ""ti,tmp432"" + device i2c 4d on end + end + end device ref i2c_3 on end device ref uart_0 on end # UART0 - + device ref uart_2 on end # UART2 + device ref uart_4 on end # UART4 end -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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