coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brya: Do not select HAVE_ACPI_RESUME
by Dinesh Gehlot (Code Review) 14 Feb '25

14 Feb '25

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86422?usp=email ) Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME ...................................................................... mb/google/brya: Do not select HAVE_ACPI_RESUME Brya mainboard does not reliably support S3 entry/exit. Hence do no select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board reset if the system resumes from S3. BUG=b:337274309 TEST=Boot verfied google/trulo. TEST=Veified that the _S3 name variable is not present in the DSDT asl. Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/bootblock.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/86422/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 8d09f2e..073319f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -28,7 +28,6 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select I2C_TPM diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index 0d0662b..782231e 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> #include <bootblock_common.h> +#include <bootmode.h> +#include <reset.h> #include <security/tpm/tss.h> +#include <security/vboot/vboot_common.h> void bootblock_mainboard_early_init(void) { @@ -18,6 +22,13 @@ void bootblock_mainboard_init(void) { + if (platform_is_resuming()) { + printk(BIOS_EMERG, "ACPI S3 resume is not supported on this platform\n"); + /* Prepare for reboot to clear the sleep state such that the board + is not stuck in reboot loop. */ + vboot_platform_prepare_reboot(); + board_reset(); + } variant_update_descriptor(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Gerrit-Change-Number: 86422 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>

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[XS] Change in coreboot[main]: soc/amd/glinda: Fix pci int defs
by Maximilian Brune (Code Review) 14 Feb '25

14 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86421?usp=email ) Change subject: soc/amd/glinda: Fix pci int defs ...................................................................... soc/amd/glinda: Fix pci int defs commit 540d605f4849 ("soc/amd/glinda: Update pci int defs") forgot to update the offset after adding GEventSmi and GEventSci. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I702f16e681d57c5e44f91c805a9aeb71eb160bd3 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/acpi/pci_int_defs.asl 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/86421/1 diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl index 61ecd44..53ced22 100644 --- a/src/soc/amd/glinda/acpi/pci_int_defs.asl +++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) Field(PRQM, ByteAcc, NoLock, Preserve) { @@ -51,7 +49,7 @@ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ - Offset (0xE2), + Offset (0xE0), IGSC, 0x00000008, /* Index 0xE0: GEventSci */ IGSM, 0x00000008, /* Index 0xE1: GEventSmi */ IGPI, 0x00000008, /* Index 0xE2: GPIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I702f16e681d57c5e44f91c805a9aeb71eb160bd3 Gerrit-Change-Number: 86421 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable Thunderbolt authentication
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86420?usp=email ) Change subject: soc/intel/pantherlake: Enable Thunderbolt authentication ...................................................................... soc/intel/pantherlake: Enable Thunderbolt authentication This commit enables Thunderbolt authentication for Panther Lake by assigning tcss_valid_tbt_auth to the valid_tbt_auth field in `soc_tcss_ops`. For the SoC's integrated PD solution, AUX BIAS PAD programming is not required and has been removed. TEST=Verified all USB-C ports are functional. With this patch, \_SB.PCI0.TDM0._DSD exists in the SSDT, containing: ``` Scope (\_SB.PCI0.TDM0) { Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("c44d002f-69f9-4e7d-a904-a7baabdf43f7"), Package (0x01) { Package (0x02) { "IMR_VALID", One } }, ToUUID ("6c501103-c189-4296-ba72-9bf5a26ebe5d"), Package (0x01) { Package (0x02) { "WAKE_SUPPORTED", One } } } ``` Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/tcss.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/86420/1 diff --git a/src/soc/intel/pantherlake/tcss.c b/src/soc/intel/pantherlake/tcss.c index 99cbdd2..c37031c 100644 --- a/src/soc/intel/pantherlake/tcss.c +++ b/src/soc/intel/pantherlake/tcss.c @@ -4,7 +4,6 @@ #include <soc/soc_chip.h> const struct soc_tcss_ops tcss_ops = { -/* TODO: Implement AUX BIAS PAD Programming if required */ .configure_aux_bias_pads = NULL, - .valid_tbt_auth = NULL, + .valid_tbt_auth = tcss_valid_tbt_auth, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17 Gerrit-Change-Number: 86420 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Configure the finger print pins
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Ian Feng, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86413?usp=email ) Change subject: mb/google/fatcat/var/francka: Configure the finger print pins ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/fatcat/variants/francka/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86413/comment/609ddd59_745a7fab?us… : PS1, Line 66: PchSerialIoDisabled > I disable GSPI0 PCI mode and fingerprint(GSPI1) functions still work well. > Do I need to enable PCI mode of GPIO0? please ignore my comments, GSPI0 is not the first device in the PCI bus so, my recommendation is not valid -- To view, visit https://review.coreboot.org/c/coreboot/+/86413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c Gerrit-Change-Number: 86413 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 13:33:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Configure the finger print pins
by Ian Feng (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Ian Feng has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86413?usp=email ) Change subject: mb/google/fatcat/var/francka: Configure the finger print pins ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/francka/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86413/comment/d95aad59_0cdac625?us… : PS1, Line 66: PchSerialIoDisabled > I guess GPI0 might needs to be in PCI mode to make sure GSPI1 is working as they share the same bus I disable GSPI0 PCI mode and fingerprint(GSPI1) functions still work well. Do I need to enable PCI mode of GPIO0? -- To view, visit https://review.coreboot.org/c/coreboot/+/86413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c Gerrit-Change-Number: 86413 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 13:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common: Add low battery shutdown function
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86361?usp=email ) Change subject: soc/intel/common: Add low battery shutdown function ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/reset.c: https://review.coreboot.org/c/coreboot/+/86361/comment/cfcb31c5_4325e2a6?us… : PS4, Line 27: poweroff(); > > Wait, where did the rest of this function go? Who is doing the delay and the elog entry now? (If this function does nothing more than `poweroff()`, it doesn't need to exist, the caller could just call `poweroff()` directly.) > > > I will add delay and elog in this same function alongwith CL that introduces PLATFORM_HAS_LOW_BATTERY_INDICATOR Kconfig, therefore, this function will grow to support platform with PLATFORM_HAS_LOW_BATTERY_INDICATOR Kconfig enabled. This is just a skeleton for now CB:86419 for review -- To view, visit https://review.coreboot.org/c/coreboot/+/86361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4 Gerrit-Change-Number: 86361 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 12:27:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: soc/intel/common/reset: Add low battery indicator delay
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Intel coreboot Reviewers. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86419?usp=email ) Change subject: soc/intel/common/reset: Add low battery indicator delay ...................................................................... soc/intel/common/reset: Add low battery indicator delay This commit adds a delay to the `do_low_battery_poweroff()` function, allowing time for the low battery indicator to be displayed before powering off. The delay is configurable through the `PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC` Kconfig option. Additionally, a low battery indicator event is logged using `elog` before the delay. This functionality is enabled when the `PLATFORM_HAS_LOW_BATTERY_INDICATOR` Kconfig option is selected. BUG=b:339673254 TEST=Able to build and boot google/brox. Change-Id: I56bff7af8c9ddd9b34d19d2c0b6a76172eff3f31 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/reset.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/86419/1 diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 4cbf996..3fefa57 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -3,6 +3,8 @@ #include <arch/cache.h> #include <cf9_reset.h> #include <console/console.h> +#include <delay.h> +#include <elog.h> #include <halt.h> #include <reset.h> @@ -24,5 +26,10 @@ void do_low_battery_poweroff(void) { + if (CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)) { + elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN); + delay(CONFIG_PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC); + } + poweroff(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56bff7af8c9ddd9b34d19d2c0b6a76172eff3f31 Gerrit-Change-Number: 86419 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add low battery indicator screen
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar. Hello Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86225?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Code-Review+2 by Julius Werner, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: drivers/intel/fsp2_0: Add low battery indicator screen ...................................................................... drivers/intel/fsp2_0: Add low battery indicator screen This commit adds low battery indicator bitmap into CBFS. This screen is displayed when the system detects a critically low battery condition. The screen displays a logo and can be configured with a custom path. An option to display an early low battery indicator in text mode is also included. This early indicator can defer the firmware update. This feature is controlled by the PLATFORM_HAS_LOW_BATTERY_INDICATOR Kconfig option. BUG=b:339673254 TEST=Able to see low-battery user notification in text mode before memory init. Verified low-battery boot event listed in the eventlog. Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/lib/Makefile.mk 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/86225/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Enable low-battery indicator support
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86316?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake: Enable low-battery indicator support ...................................................................... soc/intel/alderlake: Enable low-battery indicator support This patch enables the `HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR` Kconfig option for Alder Lake SoC platform. This allows the eSOL feature (using libgfxinit) to display a low-battery indicator. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86316/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444 Gerrit-Change-Number: 86316 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Handle critical low battery early in romstage
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86227?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+2 by Julius Werner, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/alderlake: Handle critical low battery early in romstage ...................................................................... soc/intel/alderlake: Handle critical low battery early in romstage This commit implements early handling of critical low battery conditions in the romstage for Alder Lake platforms. A message is displayed to the user via ux_inform_user_of_poweroff_operation. A short delay is introduced to allow the user to see the message. A low battery event is logged. The system is shut down via the Chrome EC. This early handling prevents the system from proceeding with boot (while performing firmware update) if the battery is critically low and ensures a clean shutdown. This is particularly important for ChromeOS devices. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86227/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/86227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2 Gerrit-Change-Number: 86227 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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coreboot-gerrit February 2025