coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: mb/siemens/fa_ehl/variants/fa_ehl: Remove I210 driver
by Johannes Hahn (Code Review) 14 Feb '25

14 Feb '25

Johannes Hahn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86425?usp=email ) Change subject: mb/siemens/fa_ehl/variants/fa_ehl: Remove I210 driver ...................................................................... mb/siemens/fa_ehl/variants/fa_ehl: Remove I210 driver Intel I210 Ethernet Transceiver is not used on platform. Change-Id: I413cb334ee06e3fc7183dc2621b6091f0d0b602b Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/86425/1 diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig index 0f3544c..76096a4 100644 --- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select DRIVER_INTEL_I210 select EHL_TSN_DRIVER select DRIVERS_ETH_PHY_M88E1512 -- To view, visit https://review.coreboot.org/c/coreboot/+/86425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I413cb334ee06e3fc7183dc2621b6091f0d0b602b Gerrit-Change-Number: 86425 Gerrit-PatchSet: 1 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com>

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[S] Change in coreboot[main]: soc/amd/common/block/graphics: Support non VGA IGDs
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86300?usp=email ) Change subject: soc/amd/common/block/graphics: Support non VGA IGDs ...................................................................... soc/amd/common/block/graphics: Support non VGA IGDs On glinda the IGD is no longer VGA compatible. It doesn't advertise itself as a VGA compatible devices and doesn't decode the legacy VGA ranges 0x3C0-0x3CF, 0x3D4. Introduce a new Kconfig and select it where necessary to keep existing behaviour on older SoC while fixing FSP GOP init on glinda. The VBIOS will get loaded into the D-segment instead the C-segment, which is typically used by VGA. TEST: FSP GOP on amd/birman+ is able to find the VBIOS. amdgpu driver still doesn't work as the VFCT table isn't generated on amd/glinda. Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86300 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/graphics/Kconfig M src/soc/amd/common/block/graphics/graphics.c M src/soc/amd/glinda/Kconfig 3 files changed, 16 insertions(+), 4 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified Ana Carolina Cabral: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/graphics/Kconfig b/src/soc/amd/common/block/graphics/Kconfig index 3b2eaed..b7401fb 100644 --- a/src/soc/amd/common/block/graphics/Kconfig +++ b/src/soc/amd/common/block/graphics/Kconfig @@ -35,3 +35,11 @@ help Select this option to provide Audio CoProcessor ACPI device for pre-Ryzen APUs for use by custom Windows drivers. + +config SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA + bool + depends on SOC_AMD_COMMON_BLOCK_GRAPHICS + help + Select this option when the IGD is not VGA compatible. On newer platforms the IGD + advertises itself as a Display device, but not as a VGA Display controller. + The IGD does not decode the legacy I/O ranges 0x3C0-0x3CF, 0x3D4. diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index f80484d..369fd85 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -148,10 +148,13 @@ void *vbt_get(void) { - if (CONFIG(RUN_FSP_GOP)) - return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + if (!CONFIG(RUN_FSP_GOP)) + return NULL; - return NULL; + if (CONFIG(SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA)) + return (void *)(uintptr_t)PCI_RAM_IMAGE_START; + + return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; } static void graphics_set_resources(struct device *const dev) diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index aa8c85e..39fb785 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -47,7 +47,8 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GPP_CLK - select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GRAPHICS + select SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/86300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Gerrit-Change-Number: 86300 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization
by Johannes Hahn (Code Review) 14 Feb '25

14 Feb '25

Johannes Hahn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86424?usp=email ) Change subject: src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization ...................................................................... src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization Process the single SPD data file which resides in cbfs. Add KConfig switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex into the build by adding a correspondig Makefile.mk in the spd folder. Additional to load the memory confiugration FSP-M parameters for the romstage are set. Besides Kconfig switch USE_SIEMENS_HWILIB was removed. Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/mainboard/siemens/fa_ehl/Kconfig M src/mainboard/siemens/fa_ehl/romstage_fsp_params.c M src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c A src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Makefile.mk A src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/spd.h 5 files changed, 26 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/86424/1 diff --git a/src/mainboard/siemens/fa_ehl/Kconfig b/src/mainboard/siemens/fa_ehl/Kconfig index d15bda1..7240e11 100644 --- a/src/mainboard/siemens/fa_ehl/Kconfig +++ b/src/mainboard/siemens/fa_ehl/Kconfig @@ -6,7 +6,7 @@ select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select HAVE_ACPI_TABLES - select USE_SIEMENS_HWILIB + select HAVE_SPD_IN_CBFS select SOC_INTEL_DISABLE_POWER_LIMITS config BOARD_SIEMENS_FA_EHL diff --git a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c index 506bcc6..ed62414 100644 --- a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <device/dram/common.h> #include <device/mmio.h> -#include <hwilib.h> #include <soc/meminit.h> #include <soc/romstage.h> #include <string.h> @@ -14,24 +12,16 @@ { static struct spd_info spd_info; const struct mb_cfg *board_cfg = variant_memcfg_config(); - static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE]; - const char *cbfs_hwi_name = "hwinfo.hex"; - /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to - spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ - memset(spd_data, 0, sizeof(spd_data)); - if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && - (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { - spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; - spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; - spd_info.read_type = READ_SPD_MEMPTR; - } else { - die("SPD in HW-Info not valid!\n"); - } - /* Initialize variant specific configurations */ - memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false); + bool half_populated = false; + spd_info.read_type = READ_SPD_CBFS; + spd_info.spd_spec.spd_index = 0x00; + + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); /* Enable Row-Hammer prevention */ memupd->FspmConfig.RhPrevention = 1; + + /* Disable VT-d */ + memupd->FspmConfig.VtdDisable = 1; } diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c index 8088857..31d0a08 100644 --- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Makefile.mk b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Makefile.mk new file mode 100644 index 0000000..36f6226 --- /dev/null +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = Nanya_NT6AP512T32BV-J1I.spd # 0b000 \ No newline at end of file diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/spd.h b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/spd.h new file mode 100644 index 0000000..e2fe0f3 --- /dev/null +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/spd.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <stdint.h> + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b Gerrit-Change-Number: 86424 Gerrit-PatchSet: 1 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com>

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[S] Change in coreboot[main]: mb/siemens/fa_ehl/variants/fa_ehl/spd: Add Nanya remove Micron SPD data
by Johannes Hahn (Code Review) 14 Feb '25

14 Feb '25

Johannes Hahn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86423?usp=email ) Change subject: mb/siemens/fa_ehl/variants/fa_ehl/spd: Add Nanya remove Micron SPD data ...................................................................... mb/siemens/fa_ehl/variants/fa_ehl/spd: Add Nanya remove Micron SPD data Micron SPD file was removed and Nanya-NT6AP512T32BV-J1I.spd was added as it will be used for the final product. Change-Id: Icbfb3a51fcb7c09bad9b70861fa58f5c957ce1ae Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- R src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/86423/1 diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Micron_MT53E512M32D1NP-046WTB.spd.hex b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex similarity index 84% rename from src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Micron_MT53E512M32D1NP-046WTB.spd.hex rename to src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex index 79548b6..6f29d35 100644 --- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Micron_MT53E512M32D1NP-046WTB.spd.hex +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex @@ -1,11 +1,11 @@ -23 11 11 0E 16 21 04 08 00 40 00 00 02 22 00 00 -00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 05 0A 80 5D 01 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 4F AC +00 00 00 00 00 00 00 00 00 00 00 00 00 00 B7 F4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 4D 54 35 33 45 35 31 -32 4D 33 32 44 31 4E 50 2D 30 34 36 20 00 00 00 +83 0B 00 00 00 00 00 00 00 4E 54 36 41 50 35 31 +32 54 33 32 42 56 2D 4A 31 49 20 20 20 00 83 0B FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/86423?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbfb3a51fcb7c09bad9b70861fa58f5c957ce1ae Gerrit-Change-Number: 86423 Gerrit-PatchSet: 1 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com>

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[M] Change in coreboot[main]: soc/amd/common/block/graphics: Use vbt_get()
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86299?usp=email ) Change subject: soc/amd/common/block/graphics: Use vbt_get() ...................................................................... soc/amd/common/block/graphics: Use vbt_get() Implement vbt_get() on AMD and return the VBIOS location. This allows to drop the hardcoded addresses used in various places and return an address in DRAM that is reserved for FSP use. TEST: amd/birman+ still gets passed the correct VBIOS address. Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/amd/cezanne/fsp_s_params.c M src/soc/amd/common/block/graphics/graphics.c A src/soc/amd/common/block/include/amdblocks/vbt.h M src/soc/amd/glinda/fsp_s_params.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/amd/phoenix/fsp_s_params.c M src/soc/amd/picasso/fsp_s_params.c 8 files changed, 46 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved Ana Carolina Cabral: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 1caf00f..fdac9f5 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -14,7 +14,12 @@ #include <mrc_cache.h> #include <program_loading.h> #include <soc/intel/common/reset.h> +#if CONFIG(SOC_AMD_COMMON) +#include <amdblocks/vbt.h> +#endif +#if CONFIG(SOC_INTEL_COMMON) #include <soc/intel/common/vbt.h> +#endif #include <stage_cache.h> #include <string.h> #include <timestamp.h> diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index b9770f3..391461e 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> @@ -13,7 +14,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 77420ae..f80484d 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -4,6 +4,7 @@ #include <acpi/acpigen.h> #include <amdblocks/graphics.h> #include <amdblocks/vbios_cache.h> +#include <amdblocks/vbt.h> #include <boot/coreboot_tables.h> #include <bootmode.h> #include <bootstate.h> @@ -12,7 +13,6 @@ #include <device/pci.h> #include <fmap.h> #include <security/vboot/vbios_cache_hash_tpm.h> -#include <soc/intel/common/vbt.h> #include <timestamp.h> static bool vbios_loaded_from_cache = false; @@ -146,17 +146,11 @@ return "IGFX"; } -/* - * On AMD platforms the VBT is called ATOMBIOS and is always part of the - * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are - * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP - * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but - * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM - * notify is called. FSP expects a pointer to the PCI option rom instead - * a pointer to the ATOMBIOS table directly. - */ void *vbt_get(void) { + if (CONFIG(RUN_FSP_GOP)) + return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + return NULL; } @@ -259,12 +253,12 @@ } /* copy from PCI_VGA_RAM_IMAGE_START to rdev */ - if (rdev_writeat(&rw_vbios_cache, (void *)PCI_VGA_RAM_IMAGE_START, 0, + if (rdev_writeat(&rw_vbios_cache, vbt_get(), 0, VBIOS_CACHE_FMAP_SIZE) != VBIOS_CACHE_FMAP_SIZE) printk(BIOS_ERR, "Failed to save vbios data to flash; rdev_writeat() failed.\n"); - /* copy modified vbios data from PCI_VGA_RAM_IMAGE_START to buffer before hashing */ - memcpy(vbios_data, (void *)PCI_VGA_RAM_IMAGE_START, VBIOS_CACHE_FMAP_SIZE); + /* copy modified vbios data to buffer before hashing */ + memcpy(vbios_data, vbt_get(), VBIOS_CACHE_FMAP_SIZE); /* save data hash to TPM NVRAM for validation on subsequent boots */ vbios_cache_update_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE); @@ -279,8 +273,8 @@ */ void vbios_load_from_cache(void) { - /* copy cached vbios data from buffer to PCI_VGA_RAM_IMAGE_START */ - memcpy((void *)PCI_VGA_RAM_IMAGE_START, vbios_data, VBIOS_CACHE_FMAP_SIZE); + /* copy cached vbios data from buffer to address used by FSP */ + memcpy(vbt_get(), vbios_data, VBIOS_CACHE_FMAP_SIZE); /* mark cache as used so we know not to write it later */ vbios_loaded_from_cache = true; diff --git a/src/soc/amd/common/block/include/amdblocks/vbt.h b/src/soc/amd/common/block/include/amdblocks/vbt.h new file mode 100644 index 0000000..05fc5e3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/vbt.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_BLOCK_VBT_H_ +#define _AMD_BLOCK_VBT_H_ + +/* + * On AMD platforms the VBT is called ATOMBIOS and is always part of the + * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are + * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP + * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but + * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM + * notify is called. FSP expects a pointer to the PCI Option Rom instead of + * a pointer to the ATOMBIOS table directly. + * + * Returns a pointer to the VGA Option ROM in DRAM after checking + * prerequisites for Pre OS Graphics initialization. When returning + * non NULL the Option ROM might not be loaded at this address yet, + * but is guaranteed to be present at end of BS_DEV_RESOURCES phase. + */ +void *vbt_get(void); + +#endif diff --git a/src/soc/amd/glinda/fsp_s_params.c b/src/soc/amd/glinda/fsp_s_params.c index e037957..980eea8 100644 --- a/src/soc/amd/glinda/fsp_s_params.c +++ b/src/soc/amd/glinda/fsp_s_params.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> @@ -15,7 +16,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 5c37334..5393eba 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -5,6 +5,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> #include <amdblocks/vbios_cache.h> +#include <amdblocks/vbt.h> #include <bootmode.h> #include <bootsplash.h> #include <console/console.h> @@ -26,7 +27,7 @@ * before FSP notify AFTER_PCI_ENUM. */ printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__); - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/phoenix/fsp_s_params.c b/src/soc/amd/phoenix/fsp_s_params.c index 883cde0..9ce09f8 100644 --- a/src/soc/amd/phoenix/fsp_s_params.c +++ b/src/soc/amd/phoenix/fsp_s_params.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> @@ -15,7 +16,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index d4cfa27..fd6f817 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -2,6 +2,7 @@ #include <assert.h> #include <amdblocks/ioapic.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -190,7 +191,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer_addr = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -- To view, visit https://review.coreboot.org/c/coreboot/+/86299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Gerrit-Change-Number: 86299 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: device/pci_rom: Keep track of VBIOS
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Patrick Rudolph, Paul Menzel. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86385?usp=email ) Change subject: device/pci_rom: Keep track of VBIOS ...................................................................... Patch Set 3: (3 comments) Patchset: PS3: only had a very brief look at this one File src/device/pci_rom.c: https://review.coreboot.org/c/coreboot/+/86385/comment/d0ff6dbe_0ad88253?us… : PS3, Line 172: #if CONFIG(HAVE_ACPI_TABLES) when removing the guard in the header file, those guards can be dropped too, since this will still build and behave as expected in the !CONFIG(HAVE_ACPI_TABLES) case. same in line 181 File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/86385/comment/6968e74b_bbae3060?us… : PS3, Line 131: #if CONFIG(HAVE_ACPI_TABLES) hmm, i don't see the need to put this in a #if CONFIG(HAVE_ACPI_TABLES) block and iirc i removed some #if CONFIG(HAVE_ACPI_TABLES) instances in this file some time ago -- To view, visit https://review.coreboot.org/c/coreboot/+/86385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib27d30e3b07740d6098d4f7a5c4f5d8bce976f00 Gerrit-Change-Number: 86385 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: device/pci_rom: Move VBIOS checksum fix
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86384?usp=email ) Change subject: device/pci_rom: Move VBIOS checksum fix ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86384?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63aaaefaf01ea456e2ed39cd0891e552a7fb5135 Gerrit-Change-Number: 86384 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:27:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/common/block/graphics: Support non VGA IGDs
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86300?usp=email ) Change subject: soc/amd/common/block/graphics: Support non VGA IGDs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Gerrit-Change-Number: 86300 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:25:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/common/block/graphics: Use vbt_get()
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Andrey Petrov, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier, Patrick Rudolph, Ronak Kanabar. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86299?usp=email ) Change subject: soc/amd/common/block/graphics: Use vbt_get() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Gerrit-Change-Number: 86299 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:25:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable Thunderbolt authentication
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86420?usp=email ) Change subject: soc/intel/pantherlake: Enable Thunderbolt authentication ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: let me get back with more testing -- To view, visit https://review.coreboot.org/c/coreboot/+/86420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17 Gerrit-Change-Number: 86420 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 15:47:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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