coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[M] Change in coreboot[main]: Documentation: Improve x86_64
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79160?usp=email ) Change subject: Documentation: Improve x86_64 ...................................................................... Documentation: Improve x86_64 * Move x86_64 documentation to dedicated page * Update with better description of current implementation * Update TODOs Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79160 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M Documentation/arch/x86/index.md A Documentation/arch/x86/x86_64.md 2 files changed, 110 insertions(+), 87 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index f2597ac..1c5edb3 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -6,91 +6,5 @@ :maxdepth: 1 x86 PAE support <pae.md> +x86_64 support <x86_64.md> ``` - -## State of x86_64 support -Some SOCs now support 64bit mode. Search for HAVE_X86_64_SUPPORT in Kconfig. - -In order to add support for x86_64 the following assumptions were made: -* The CPU supports long mode -* All memory returned by malloc must be below 4GiB in physical memory -* All code that is to be run must be below 4GiB in physical memory -* The high dword of pointers is always zero -* The reference implementation is qemu -* x86 payloads are loaded below 4GiB in physical memory and are jumped - to in *protected mode* - -## Assumptions for all stages using the reference implementation -* 0-4GiB are identity mapped using 2MiB-pages as WB -* Memory above 4GiB isn't accessible -* page tables reside in memory mapped ROM -* A stage can install new page tables in RAM - -## Page tables -A `pagetables` cbfs file is generated based on an assembly file. - -To generate the static page tables it must know the physical address where to -place the file. - -The page tables contains the following structure: -* PML4E pointing to PDPE -* PDPE with *$n* entries each pointing to PDE -* *$n* PDEs with 512 entries each - -At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. - -## Basic x86_64 support -Basic support for x86_64 has been implemented for QEMU mainboard target. - -## Reference implementation -The reference implementation is -```{toctree} -:maxdepth: 1 - -QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md> -QEMU Q35 <../../mainboard/emulation/qemu-q35.md> -``` - -## TODO -* Identity map memory above 4GiB in ramstage - -## Future work - -1. Fine grained page tables for SMM: - * Must not have execute and write permissions for the same page. - * Must allow only that TSEG pages can be marked executable -2. Support 64bit PCI BARs above 4GiB -3. Place and run code above 4GiB - -## Porting other boards -* Fix compilation errors -* Test how well CAR works with x86_64 and paging -* Improve mode switches - -## Known problems on real hardware - -Running VGA rom directly fails. Yabel works fine though. - -## Known bugs on KVM enabled qemu - -The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues -when using KVM mode on some machines. The workaround is to *not* place -page-tables in ROM, as done in -[CB:49228](https://review.coreboot.org/c/coreboot/+/49228). - -Here's a list of known issues: - -* After entering long mode, the FPU doesn't work anymore, including accessing - MMX registers. It works fine before entering long mode. It works fine when - switching back to protected mode. Other registers, like SSE registers, are - working fine. -* Reading from virtual memory, when the page tables are stored in ROM, causes - the MMU to abort the "page table walking" mechanism when the lower address - bits of the virtual address to be translated have a specific pattern. - Instead of loading the correct physical page, the one containing the - page tables in ROM will be loaded and used, which breaks code and data as - the page table doesn't contain the expected data. This in turn leads to - undefined behaviour whenever the 'wrong' address is being read. -* Disabling paging in compatibility mode crashes the CPU. -* Returning from long mode to compatibility mode crashes the CPU. -* Entering long mode crashes on AMD host platforms. diff --git a/Documentation/arch/x86/x86_64.md b/Documentation/arch/x86/x86_64.md new file mode 100644 index 0000000..b9aebd0 --- /dev/null +++ b/Documentation/arch/x86/x86_64.md @@ -0,0 +1,109 @@ +# x86_64 architecture documentation + +This section documents coreboot's x86_64 support. When enabled, +every coreboot stage is built for x86_64, contrary to UEFI's implementation +that only runs some stages in x86_64. +On UEFI the PEI phase, which is x86_32, brings up DRAM and installs +page tables for the x86_64 DXE and BDS phases. + +## Toolchain requirements for x86_64 support +* The compiler must support generating code for the *large memory model* + (-mcmodel=large). It's supported since GCC 4.4. + + Page tables can be used to provide security benefits, such as by marking + memory as non-executable or removing it entirely. This could be useful + for SMM to mark regular DRAM as NX. + + The large memory model causes the compiler to emit 64bit addressing + instructions, which increases code size. In theory, this is roughly + made up for by the faster execution of the x86_64 code. + +* All x86 coreboot stages and payloads must be loaded below 4GiB in + physical memory. When jumping to the payload coreboot will drop from + long mode back to protected mode to keep compatibility with these payloads. + +## Comparison to UEFI +On UEFI the SEC and PEI phases (similar to coreboot's bootblock and romstage) +are run in x86_32 mode. The following (guessed) reasons are likely: +* There's no need for x86_64 as memory hasn't been trained yet. The whole 4GiB + address space, including CAR, memory mapped SPI flash and PCI BARs, are + accessible in x86_32. +* When the EFI specification was written compilers did not support + *large memory model*, required in CAR when using a 1:1 page mapping +* Code is 20% bigger in x86_64 due to *large memory model* where pointers and + function calls always use 8 byte addressing. However flash size was very + limited, compared to today's flash chips, when the EFI spec was written. + +## Current software constraints for x86_64 support +The following constraints are coreboot limitations as it was intended to run in +protected mode only. The code still assumes 32bit pointers in some places and thus: +* The high dword of pointers must always be zero. +* All memory returned by malloc must be below 4GiB in physical memory. +* All code that is to be run must be below 4GiB in physical memory. +* CBMEM must reside below 4GiB in physical memory. + +Any software within coreboot must not access memory resources above 4GiB until +end of BS_DEV_RESOURCES in ramstage. Only at that point the full memory map is +known and identity mapped. + +## Supported boards +On the supported boards you can enable x86_64 compilation by setting the +Kconfig `USE_X86_64_SUPPORT`. This config option is enabled if the SOC/CPU +selects `HAVE_X86_64_SUPPORT`. + +## Protected mode wrappers +On some platforms binary blobs are run to initialize parts of the hardware. +When these binary blobs have been compiled for x86_32, then coreboot must +switch to protected mode in order to call and run the blobs. Once the invoked +blobs finish running, coreboot needs to switch back to long mode. + +Since every BLOB is different a SoC must be enabled to support x86_64 mode +by providing the correct wrapper around the x86_32 BLOBs. + +## TODO +* Support more platforms +* Fix running VGA Option ROMs +* Fix running MRC.bin (Sandy Bridge / Haswell boards) +* Identity map memory above 4GiB in ramstage +* Fine grained page tables for SMM: + * Must not have execute and write permissions for the same page. + * Must only allow TSEG pages to be marked as executable. + * Must reside in SMRAM. + * Must be placed together with SMM rmodule. +* Support 64bit PCI BARs above 4GiB +* Jump to compatible payloads in long mode + +## Porting other boards +* Fix compilation errors +* Test how well CAR works with x86_64 and paging +* Improve mode switches +* Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +According to Intel x86_64 mode hasn't been validated in CAR environments. +However, coreboot developers working on x86_64 support have tried this on +various Intel platforms, and so far haven't found any issues with CAR when +running in x86_64 mode. + +## Known bugs on KVM enabled QEMU + +The `x86_64` reference code runs fine in QEMU's soft-cpu, but has serious issues +when using KVM mode on some machines. This is due to various mechanisms trying +to accelerate the code execution. + +Known issues in QEMU: +* After entering long mode, the FPU doesn't work anymore, including accessing + MMX registers. It works fine before entering long mode. It works fine when + switching back to protected mode. Other registers, like SSE registers, are + working fine. +* Reading from virtual memory, when the page tables are stored in ROM, causes + the MMU to abort the "page table walking" mechanism when the lower address + bits of the virtual address to be translated have a specific pattern. + Instead of loading the correct physical page, the one containing the + page tables in ROM will be loaded and used, which breaks code and data as + the page table doesn't contain the expected data. This in turn leads to + undefined behaviour whenever the 'wrong' address is being read. +* Disabling paging in compatibility mode crashes the CPU. +* Returning from long mode to compatibility mode crashes the CPU. +* Entering long mode crashes on AMD host platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/79160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 79160 Gerrit-PatchSet: 12 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XS] Change in coreboot[main]: board_status/getrevision.sh: Ignore non-annotated tags
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79837?usp=email ) Change subject: board_status/getrevision.sh: Ignore non-annotated tags ...................................................................... board_status/getrevision.sh: Ignore non-annotated tags Local tags (e.g. to keep track of builds) should not be used to describe a board status report. This has happened in some cases, e.g. [1]. According to the Git 2.41.0 manual for git-describe, the '--tagged' parameter is a way to also use any "lightweight (non-annotated) tag" in addition to annotated tags, which are always used even without this parameter. All coreboot release tags seem to be annotated, so this option should be safe to drop. [1] https://review.coreboot.org/plugins/gitiles/board-status/+/b8c47429bad5afc5… Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: I54b302415e569a3385559cc85323ce34462042ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/79837 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/board_status/getrevision.sh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/util/board_status/getrevision.sh b/util/board_status/getrevision.sh index ced20fc..a982f8d 100755 --- a/util/board_status/getrevision.sh +++ b/util/board_status/getrevision.sh @@ -112,7 +112,7 @@ local r if git_is_file_tracked "$1" ; then - r=$(git describe --tags --dirty) + r=$(git describe --dirty) else return ${EXIT_FAILURE} fi -- To view, visit https://review.coreboot.org/c/coreboot/+/79837?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54b302415e569a3385559cc85323ce34462042ad Gerrit-Change-Number: 79837 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: drivers/qemu/bochs: Use arch-independent data port
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82061?usp=email ) Change subject: drivers/qemu/bochs: Use arch-independent data port ...................................................................... drivers/qemu/bochs: Use arch-independent data port The QEMU Bochs display driver uses 0x1CF as its VBE DISPI data port, but this is only present on x86. Instead, use the port at 0x1D0 [1] which is available on both x86 and non-x86 architectures. The data port is also calculated inline based on the VBE DISPI index port while reading and writing, update those expressions as well. [1] https://web.archive.org/web/20240404032816/https://www.qemu.org/docs/master… Change-Id: I899beb742d42c26f3e57023f05ff459094fce5f1 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82061 Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/emulation/qemu/bochs.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 2e0526f..70d17cb 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -14,7 +14,7 @@ /* VGA init. We use the Bochs VESA VBE extensions */ #define VBE_DISPI_IOPORT_INDEX 0x01CE -#define VBE_DISPI_IOPORT_DATA 0x01CF +#define VBE_DISPI_IOPORT_DATA 0x01D0 #define VBE_DISPI_INDEX_ID 0x0 #define VBE_DISPI_INDEX_XRES 0x1 @@ -46,7 +46,7 @@ { if (res->flags & IORESOURCE_IO) { outw(index, res->base); - outw(val, res->base + 1); + outw(val, res->base + 2); } else { write16(res2mmio(res, 0x500 + index * 2, 0), val); } @@ -56,7 +56,7 @@ { if (res->flags & IORESOURCE_IO) { outw(index, res->base); - return inw(res->base + 1); + return inw(res->base + 2); } else { return read16(res2mmio(res, 0x500 + index * 2, 0)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/82061?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I899beb742d42c26f3e57023f05ff459094fce5f1 Gerrit-Change-Number: 82061 Gerrit-PatchSet: 3 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80411?usp=email ) ( 24 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M710s Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80411 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m710s.md A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg 3 files changed, 82 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Alicja Michalska: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index f9f9048..518c02a 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -184,6 +184,7 @@ Mainboard codenames <lenovo/codenames.md> Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md> R60 <lenovo/r60.md> +ThinkCentre M710s <lenovo/thinkcentre_m710s.md> T4xx common <lenovo/t4xx_series.md> X2xx common <lenovo/x2xx_series.md> M920 Tiny <lenovo/m920q.md> diff --git a/Documentation/mainboard/lenovo/thinkcentre_m710s.md b/Documentation/mainboard/lenovo/thinkcentre_m710s.md new file mode 100644 index 0000000..0f9adff --- /dev/null +++ b/Documentation/mainboard/lenovo/thinkcentre_m710s.md @@ -0,0 +1,81 @@ +# Lenovo ThinkCentre M710s + +This page provides technical documentation on [Lenovo ThinkCentre M710s]. + +## Flash chip + +```{eval-rst} ++----------+-------------+ +| Type | Value | ++==========+=============+ +| Socketed | yes | ++----------+-------------+ +| Model | W25Q64JV-.Q | ++----------+-------------+ +| Size | 8MiB | ++----------+-------------+ +| Package | SOIC-8 | ++----------+-------------+ +``` + +The flash chip is divided into the following regions. + + 00000000:00000fff fd + 00200000:007fffff bios + 00003000:001fffff me + 00001000:00002fff gbe + +## Flashing + +The flash chip cannot be flashed internally when running vendor firmware, and must +be flashed externally using a programmer of your choice. + +Steps on how to open the chassis and get access to the mainboard are described +in the [hardware maintenance manual]. Follow the steps shown from +"[Removing the computer cover]" until step 1 of "[Replacing the storage drive]". + +The SPI flash should be easy to identify and the location is shown in the image +below. See the [datasheet] and [flashing firmware tutorial] for more information. + +![](thinkcentre_m710s_spi_location.jpg) + +## Status + +### Working + * Ubuntu 22.04.1 (Linux 6.5.0) using payloads: + * SeaBIOS + * MrChromebox's EDK 2 fork + * Tianocore's EDK 2 + * Internal flashing (from coreboot) + * PEG (PCIe Graphics) + * PCIe + * SATA + * M.2 SSD + * M.2 WLAN (+ Bluetooth) + * LAN + * USB + * Memory card reader + * CPU fan + * VGA + * Display ports + * Audio (output) + * COM1 + * TPM + +### Not working + * Super I/O not well supported (there may be some minor issues) + * Power button LED + * ME cleaner + +### Untested + * Audio (input) + * COM2 header + * LPT header + * PS/2 keyboard and mouse + +[Lenovo ThinkCentre M710s]: https://www.lenovo.com/us/en/p/desktops/thinkcentre/m-series-sff/thinkcentr… +[hardware maintenance manual]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf +[Removing the computer cover]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf#page… +[Replacing the storage drive]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf#page… +[datasheet]: https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fla… +[flashing firmware tutorial]: ../../tutorial/flashing_firmware/index.md diff --git a/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg b/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg new file mode 100644 index 0000000..024c5b7 --- /dev/null +++ b/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 26 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/craask: Modify eMMC DLL tuning value
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86395?usp=email ) Change subject: mb/google/nissa/var/craask: Modify eMMC DLL tuning value ...................................................................... mb/google/nissa/var/craask: Modify eMMC DLL tuning value Craask cannot boot into OS from 2nd source eMMC. Update eMMC DLL tuning value to improve initialization reliability BUG=b:375497774 TEST=Cold reboot stress test over 2500 cycles Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86395 Reviewed-by: Simon Yang <simon1.yang(a)intel.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Simon Yang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 069deb3..ee8a63d 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -70,7 +70,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. -- To view, visit https://review.coreboot.org/c/coreboot/+/86395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d Gerrit-Change-Number: 86395 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/kanix: Update LAN clock request setting
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86397?usp=email ) Change subject: mb/google/rex/var/kanix: Update LAN clock request setting ...................................................................... mb/google/rex/var/kanix: Update LAN clock request setting According to the EVT's circuit(kanix_250116.pdf) change, update LAN clock request to GPP_C11. BUG=b:386025819 BRANCH=firmware-rex-15709.B TEST=emerge-rex coreboot chromeos-bootimage; test LAN function on kanix Change-Id: I5d27585717897203d6ac81ca47551be5771918c3 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86397 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/kanix/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Ren Kuo: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c index 401a083..4b757a1 100644 --- a/src/mainboard/google/rex/variants/kanix/gpio.c +++ b/src/mainboard/google/rex/variants/kanix/gpio.c @@ -117,8 +117,8 @@ PAD_NC(GPP_C09, NONE), /* GPP_C10 : net NC is not present in the given design */ PAD_NC(GPP_C10, NONE), - /* GPP_C11 : Not Connected */ - PAD_NC(GPP_C11, NONE), + /* GPP_C11 : [] ==> LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* GPP_C12 : NC pad. */ PAD_NC(GPP_C12, NONE), /* GPP_C13 : Not connected */ @@ -174,8 +174,8 @@ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), - /* GPP_D18 : [] ==> LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D18 : Not Connected */ + PAD_NC(GPP_D18, NONE), /* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */ PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG), /* GPP_D20 : [] ==> SSD_CLKREQ_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d27585717897203d6ac81ca47551be5771918c3 Gerrit-Change-Number: 86397 Gerrit-PatchSet: 6 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: soc/amd/common/block/pci: Ignore disabled bridges
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86216?usp=email ) Change subject: soc/amd/common/block/pci: Ignore disabled bridges ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/pci/pcie_gpp.c: https://review.coreboot.org/c/coreboot/+/86216/comment/ed9eb745_211f2126?us… : PS1, Line 58: static void pcie_internal_gpp_enable(struct device *dev) : { : assert(dev->enabled); : if (!dev->enabled) { : /* : * Cannot hide PPB devices! Must keep them enabled to : * make sure PCI enumeration runs and avoids resource conflicts. : */ : dev->enabled = true; : dev->hidden = true; : dev->ops = &amd_pcie_disabled_gpp_ops; : } : } > iirc @felix-coreboot@felixheld.de said that they are mandatory. […] there are ways to hide the devices behind the bridges which fsp does; not 100% sure if it's the same for the bridge device functions. if that functionality exists, it's not exposed via UPDs though -- To view, visit https://review.coreboot.org/c/coreboot/+/86216?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia97098c860aa6cd6b0b59aa7b1c6f7c239e41983 Gerrit-Change-Number: 86216 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:08:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email ) Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: the change for picasso is still missing in this series; would be good to create a patch for that soc too. probably same for genoa -- To view, visit https://review.coreboot.org/c/coreboot/+/86272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Gerrit-Change-Number: 86272 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:04:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: soc/amd/mendocino/chipset_*: Enable gpp_bridge_[a/b/c] by default
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86273?usp=email ) Change subject: soc/amd/mendocino/chipset_*: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358 Gerrit-Change-Number: 86273 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:03:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add platform callback for critical shutdown
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Karthik Ramasubramanian, Ronak Kanabar, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86226?usp=email ) Change subject: drivers/intel/fsp2_0: Add platform callback for critical shutdown ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0 Gerrit-Change-Number: 86226 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:01:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025