coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization
by Johannes Hahn (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Johannes Hahn, Mario Scheithauer, Uwe Poeche, Werner Zeh. Hello Mario Scheithauer, Uwe Poeche, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86424?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization ...................................................................... src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization Process the single SPD data file which resides in cbfs. Add KConfig switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex into the build by adding a correspondig Makefile.mk in the spd folder. Additional to load the memory confiugration FSP-M parameters for the romstage are set. Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/mainboard/siemens/fa_ehl/Kconfig M src/mainboard/siemens/fa_ehl/Makefile.mk M src/mainboard/siemens/fa_ehl/romstage_fsp_params.c A src/mainboard/siemens/fa_ehl/spd/Makefile.mk R src/mainboard/siemens/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex A src/mainboard/siemens/fa_ehl/spd/spd.h M src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig M src/mainboard/siemens/fa_ehl/variants/fa_ehl/Makefile.mk M src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c 9 files changed, 32 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/86424/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b Gerrit-Change-Number: 86424 Gerrit-PatchSet: 2 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[S] Change in coreboot[main]: drivers/smmstore: add logic to disable capsule update handling code
by Sergii Dmytruk (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Arthur Heymans, Benjamin Doron, Felix Held, Martin L Roth, Patrick Rudolph. Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83425?usp=email ) Change subject: drivers/smmstore: add logic to disable capsule update handling code ...................................................................... Patch Set 14: (1 comment) Patchset: PS10: > Thanks for the explanation! So, if I'm understanding this right, coreboot only has to gather and coa […] Correct. It takes at least 2 reboots (assuming ME is disabled and doesn't need to be re-enabled): warm reset to let the firmware perform an update and reset of any kind to boot with updated firmware. Changing state of ME takes a hard reset, which can result in 4 resets in total. That seems to be in line with how proprietary firmware is being updated (boot followed by a reset to toggle ME state is quite fast and might not be very obvious for the end user that it even occurs). By the way, you resolved the comment but left -1, was that intentional? -- To view, visit https://review.coreboot.org/c/coreboot/+/83425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dc175ea313aae1edae304520595b82db7206cbb Gerrit-Change-Number: 83425 Gerrit-PatchSet: 14 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:33:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[S] Change in coreboot[main]: drivers/smmstore: add ability to write to whole flash
by Sergii Dmytruk (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Arthur Heymans, Benjamin Doron, Felix Held, Krystian Hebel, Martin L Roth, Patrick Rudolph, Paul Menzel. Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83424?usp=email ) Change subject: drivers/smmstore: add ability to write to whole flash ...................................................................... Patch Set 13: (1 comment) File src/drivers/smmstore/store.c: https://review.coreboot.org/c/coreboot/+/83424/comment/3604c2c2_dcd6cfbe?us… : PS9, Line 63: const struct region_device *rdev = boot_device_rw(); > Okay, thanks. […] All details like FD unlocking are considered outside of the scope of this option as it's not of generic utility and shouldn't be enabled without due consideration. But yes, they are handled by the "update mode" which affects both coreboot and EDK working together to perform an upgrade. We have enabled capsule updates for MSI PRO Z690-A/Z790-P, although it will take another release to use them for a firmware upgrade. At least as of now the whole BIOS is being written, which allows updating ME and changing FD if needed (e.g., to give BIOS region more space). I think it was successfully tested on NovaCustom laptops (also Intel), I used it on some PC Engines APU board with AMD. AMD didn't require any extra steps, although that might depend on CPU family. Somewhat unfortunate, ME needs to be disabled prior to trying to do a capsule update as disabling ME takes a hard reset which in-RAM capsules can't survive. On-disk capsules might help with that but EDK handles them by loading in RAM and doing a warm reset, so at least without changing implementation much in-RAM capsules are also needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/83424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972 Gerrit-Change-Number: 83424 Gerrit-PatchSet: 13 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:33:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[XS] Change in coreboot[main]: soc/intel/common/reset: Add low battery indicator delay
by Subrata Banik (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86419?usp=email ) Change subject: soc/intel/common/reset: Add low battery indicator delay ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/reset.c: https://review.coreboot.org/c/coreboot/+/86419/comment/443195b0_59a629d2?us… : PS1, Line 29: if (CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)) { > I don't think this needs to be checked here? This function is only called by code belonging to that feature anyway. This function can be called by others in future (in case) so just intended to avoid a case when `do_low_battery_poweroff` might end up logging elog event and add delay. WDYT ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56bff7af8c9ddd9b34d19d2c0b6a76172eff3f31 Gerrit-Change-Number: 86419 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 17:25:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mb/emulation/spike-riscv/uart.c: Update UART address
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85852?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/emulation/spike-riscv/uart.c: Update UART address ...................................................................... mb/emulation/spike-riscv/uart.c: Update UART address Spike Simulator commit 191634d2854d implemented a ns16550 serial device which puts the base address at 0x10000000. Tested: Start Spike Simulator and see that coreboot prints onto the UART. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85852 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/spike-riscv/uart.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 4ea2466..e93594c 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -5,5 +5,5 @@ uintptr_t uart_platform_base(unsigned int idx) { - return (uintptr_t)0x02100000; + return (uintptr_t)0x10000000; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83 Gerrit-Change-Number: 85852 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/dirks: Use a separate ec.h for dirks
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86354?usp=email ) Change subject: mb/google/nissa/var/dirks: Use a separate ec.h for dirks ...................................................................... mb/google/nissa/var/dirks: Use a separate ec.h for dirks Dirks are chromebox, so they need different settings in ec.h. Add a new dirks baseboard ec.h and use it for dirks.Remove everything related to: - Lid - Battery - Built-in keyboard - AC connect/disconnect - Mode changes BUG=b:389391653 TEST=emerge-nissa coreboot Change-Id: I8089a2aff3032a4271212765f65881a09f42c1ae Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86354 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- A src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h M src/mainboard/google/brya/variants/dirks/include/variant/ec.h 2 files changed, 45 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h new file mode 100644 index 0000000..d9697d7 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) +#define MAINBOARD_EC_SMI_EVENTS 0 +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* + * ACPI related definitions for ASL code. + */ +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp support */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/dirks/include/variant/ec.h b/src/mainboard/google/brya/variants/dirks/include/variant/ec.h index 7a2a6ff..469e75c 100644 --- a/src/mainboard/google/brya/variants/dirks/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/dirks/include/variant/ec.h @@ -3,6 +3,6 @@ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ -#include <baseboard/ec.h> +#include <baseboard/dirks/ec.h> #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8089a2aff3032a4271212765f65881a09f42c1ae Gerrit-Change-Number: 86354 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: Update GPIO table
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86351?usp=email ) Change subject: mb/google/nissa/var/dirks: Update GPIO table ...................................................................... mb/google/nissa/var/dirks: Update GPIO table Configure buzzer to GPP_D2 based on schematic change. BUG=b:389391653 TEST=emerge-nissa coreboot Change-Id: Iefc6aefeae0a3a05ba04fb2718c6c3a3058de5f8 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86351 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/dirks/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c index 94eaff5..209ca04 100644 --- a/src/mainboard/google/brya/variants/dirks/gpio.c +++ b/src/mainboard/google/brya/variants/dirks/gpio.c @@ -19,8 +19,6 @@ /* B4 : LAN_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, PLTRST), - /* B14 : SPKR ==> PWM_PP3300_BUZZER */ - PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG), /* B16 : I2C5_SDA ==> NC */ PAD_NC(GPP_B16, NONE), /* B17 : I2C5_SCL ==> NC */ @@ -37,6 +35,8 @@ /* C7 : SML1DATA ==> NC */ PAD_NC(GPP_C7, NONE), + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), /* D3 : ISH_GP3 ==> NC */ PAD_NC(GPP_D3, NONE), /* D6 : SRCCLKREQ1# ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86351?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefc6aefeae0a3a05ba04fb2718c6c3a3058de5f8 Gerrit-Change-Number: 86351 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: payloads/external/Makefile.mk: Update linuxboot warning
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85957?usp=email ) Change subject: payloads/external/Makefile.mk: Update linuxboot warning ...................................................................... payloads/external/Makefile.mk: Update linuxboot warning Only print the warning if Linuxboot payload is actually selected, because we don't care otherwise. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I5008d685c52c1d4e0d7eba44c964c51a2a6f99c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85957 Reviewed-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> --- M payloads/external/Makefile.mk 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Alicja Michalska: Looks good to me, but someone else must approve Ana Carolina Cabral: Looks good to me, but someone else must approve diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 299f1ee..c279121 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -396,7 +396,10 @@ CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y)) endif # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH else # CONFIG_LINUXBOOT_CROSS_COMPILE +ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y) + # only print warning when Linuxboot payload is actually selected $(warning "Using host toolchain to build Linuxboot") +endif # CONFIG_PAYLOAD_LINUXBOOT endif # CONFIG_LINUXBOOT_CROSS_COMPILE .PHONY: linuxboot payloads/external/LinuxBoot/build/Image payloads/external/LinuxBoot/build/initramfs linuxboot: -- To view, visit https://review.coreboot.org/c/coreboot/+/85957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5008d685c52c1d4e0d7eba44c964c51a2a6f99c3 Gerrit-Change-Number: 85957 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: util/riscv: Add starfive Image building tool
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83849?usp=email ) Change subject: util/riscv: Add starfive Image building tool ...................................................................... util/riscv: Add starfive Image building tool Add the tooling necessary to build an Image that can be found and started by ROM code of the JH7110 SOC. source: https://github.com/starfive-tech/Tools Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83849 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/lint/lint-extended-015-final-newlines M util/lint/lint-stable-009-old-licenses A util/riscv/starfive-jh7110-spl-tool/.gitignore A util/riscv/starfive-jh7110-spl-tool/LICENSE A util/riscv/starfive-jh7110-spl-tool/Makefile A util/riscv/starfive-jh7110-spl-tool/README.md A util/riscv/starfive-jh7110-spl-tool/crc32.c A util/riscv/starfive-jh7110-spl-tool/spl_tool.c 8 files changed, 727 insertions(+), 1 deletion(-) Approvals: Alicja Michalska: Looks good to me, but someone else must approve build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines index 18ca75b..7324213 100755 --- a/util/lint/lint-extended-015-final-newlines +++ b/util/lint/lint-extended-015-final-newlines @@ -24,7 +24,8 @@ \.git/\|\ coreboot-builds/\|\ util/nvidia/cbootimage/\|\ -^util/goswid/vendor" +^util/goswid/vendor\|\ +^util/riscv/starfive-jh7110-spl-tool" EXCLUDED_FILES='\.gif$\|\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$\|\.apcb$' HAVE_FILE=$(command -v file 1>/dev/null 2>&1; echo $?) diff --git a/util/lint/lint-stable-009-old-licenses b/util/lint/lint-stable-009-old-licenses index 45c01c7..202a1a9 100755 --- a/util/lint/lint-stable-009-old-licenses +++ b/util/lint/lint-stable-009-old-licenses @@ -31,6 +31,7 @@ ^util/lint/lint-000-license-headers|\ ^util/lint/lint-stable-009-old-licenses|\ ^util/nvidia/cbootimage|\ +^util/riscv/starfive-jh7110-spl-tool|\ ^3rdparty|\ __pycache__|\ ^payloads/external\ diff --git a/util/riscv/starfive-jh7110-spl-tool/.gitignore b/util/riscv/starfive-jh7110-spl-tool/.gitignore new file mode 100644 index 0000000..26c8888 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/.gitignore @@ -0,0 +1,10 @@ +_* +*.swp +*.o +*.out +*.key +*.diff +*.patch +*.out +tags +spl_tool diff --git a/util/riscv/starfive-jh7110-spl-tool/LICENSE b/util/riscv/starfive-jh7110-spl-tool/LICENSE new file mode 100644 index 0000000..36cc8c3 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/LICENSE @@ -0,0 +1,365 @@ +================================================================ + * Copyright 2018-2023 Shanghai StarFive Technology Co., Ltd. +================================================================ + +spl_tool license: + +Valid-License-Identifier: GPL-2.0 +Valid-License-Identifier: GPL-2.0-only +Valid-License-Identifier: GPL-2.0+ +Valid-License-Identifier: GPL-2.0-or-later +SPDX-URL: https://spdx.org/licenses/GPL-2.0.html +Usage-Guide: + To use this license in source code, put one of the following SPDX + tag/value pairs into a comment according to the placement + guidelines in the licensing rules documentation. + For 'GNU General Public License (GPL) version 2 only' use: + SPDX-License-Identifier: GPL-2.0 + or + SPDX-License-Identifier: GPL-2.0-only + For 'GNU General Public License (GPL) version 2 or any later version' use: + SPDX-License-Identifier: GPL-2.0+ + or + SPDX-License-Identifier: GPL-2.0-or-later +License-Text: + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/util/riscv/starfive-jh7110-spl-tool/Makefile b/util/riscv/starfive-jh7110-spl-tool/Makefile new file mode 100644 index 0000000..c6b4d9b --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +override CFLAGS=-Wall -Wno-unused-result -Wno-format-truncation -O2 + +SRCS = $(wildcard *.c) +OBJS = $(SRCS:.c=.o) + +all: spl_tool + +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +spl_tool: $(OBJS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@ + +clean: + rm -f *.o spl_tool diff --git a/util/riscv/starfive-jh7110-spl-tool/README.md b/util/riscv/starfive-jh7110-spl-tool/README.md new file mode 100644 index 0000000..e9f61e7 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/README.md @@ -0,0 +1,54 @@ +## DESCRIPTION + +spl_tool is a jh7110 signature tool used to generate spl header information and generate u-boot-spl.bin.normal.out. + +spl_tool can also fix the issue of emmc booting. + +## Prerequisites + +Install required additional packages: + +```bash +$ sudo apt-get install gcc make git +``` + +## Build + +just run `make` + +```bash +$ make +``` + +## Run + +usage + +```bash +$ ./spl_tool -h + + StarFive spl tool + +usage: +-c, --creat-splhdr creat spl hdr +-i, --fix-imghdr fixed img hdr for emmc boot. +-a, --spl-bak-addr set backup SPL addr(default: 0x200000) +-v, --version set version (default: 0x01010101) +-f, --file input file name(spl/img) +-h, --help show this information +``` + +Generate uboot-spl.bin.normal.out + +```bash +$./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin +ubsplhdr.sofs:0x240, ubsplhdr.bofs:0x200000, ubsplhdr.vers:0x1010101 name:$(Uboot_PATH)/spl/u-boot-spl.bin +SPL written to $(Uboot_PATH)/spl/u-boot-spl.bin.normal.out successfully. +``` + +Fix the emmc boot issue + +```bash +$ ./spl_tool -i -f sdcard.img +IMG sdcard.img fixed hdr successfully. +``` \ No newline at end of file diff --git a/util/riscv/starfive-jh7110-spl-tool/crc32.c b/util/riscv/starfive-jh7110-spl-tool/crc32.c new file mode 100644 index 0000000..1394f97 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/crc32.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <sys/types.h> +#include <stdlib.h> +#include <stdint.h> + +static uint32_t crc32_reverse(uint32_t x) +{ + x = ((x & 0x55555555) << 1) | ((x >> 1) & 0x55555555); + x = ((x & 0x33333333) << 2) | ((x >> 2) & 0x33333333); + x = ((x & 0x0F0F0F0F) << 4) | ((x >> 4) & 0x0F0F0F0F); + x = (x << 24) | ((x & 0xFF00) << 8) | ((x >> 8) & 0xFF00) | (x >> 24); + return x; +} + +uint32_t crc32(uint32_t iv, uint32_t sv, const void *data, size_t n) +{ + const unsigned char *ptr; + unsigned x; + uint32_t byte, crc; + + crc = iv; + ptr = data; + while (n--) { + byte = *ptr++; + byte = crc32_reverse(byte); + for (x = 0; x < 8; x++, byte <<= 1) crc = ((crc ^ byte) & 0x80000000U) ? (crc << 1) ^ sv : (crc << 1); + } + + return crc; +} + +uint32_t crc32_final(uint32_t iv) +{ + return crc32_reverse(iv ^ ~0U); +} diff --git a/util/riscv/starfive-jh7110-spl-tool/spl_tool.c b/util/riscv/starfive-jh7110-spl-tool/spl_tool.c new file mode 100644 index 0000000..039e520 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/spl_tool.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +#define _GNU_SOURCE +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <getopt.h> +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <stdbool.h> +#include <unistd.h> +#include <endian.h> +#include <errno.h> +#include <limits.h> + +#define NOSIZE ((size_t)-1) + +extern uint32_t crc32(uint32_t iv, uint32_t sv, const void *data, size_t n); +extern uint32_t crc32_final(uint32_t iv); + +/* all uint32_t ends up little endian in output header */ +struct __attribute__((__packed__)) ubootsplhdr { + uint32_t sofs; /* offset of spl header: 64+256+256 = 0x240 */ + uint32_t bofs; /* SBL_BAK_OFFSET: Offset of backup SBL from Flash info start (from input_sbl_normal.cfg) */ + uint8_t zro2[636]; + uint32_t vers; /* version: shall be 0x01010101 + * (from https://doc-en.rvspace.org/VisionFive2/SWTRM/VisionFive2_SW_TRM/create_spl.…) */ + uint32_t fsiz; /* u-boot-spl.bin size in bytes */ + uint32_t res1; /* Offset from HDR to SPL_IMAGE, 0x400 (00 04 00 00) currently */ + uint32_t crcs; /* CRC32 of u-boot-spl.bin */ + uint8_t zro3[364]; +}; + +struct hdr_conf_t { + const char name[PATH_MAX]; + uint32_t vers; + uint32_t bofs; + bool creat_hdr_flag; + bool fixed_img_hdr_flag; +}; + +static struct ubootsplhdr ubsplhdr; +static struct ubootsplhdr imghdr; +static struct hdr_conf_t g_hdr_conf; + +static char ubootspl[181072-sizeof(struct ubootsplhdr)+1]; +static char outpath[PATH_MAX]; + +#define DEFVERSID 0x01010101 +#define DEFBACKUP 0x200000U +#define CRCFAILED 0x5A5A5A5A + +static void xerror(int errnoval, const char *s) +{ + if (errnoval) perror(s); + else fprintf(stderr, "%s\n", s); + exit(2); +} + +static void usage(void) +{ + const char help[] = { + "\n StarFive spl tool\n\n" + "usage:\n" + "-c, --creat-splhdr creat spl hdr\n" + "-i, --fix-imghdr fixed img hdr for emmc boot.\n" + "-a, --spl-bak-addr set backup SPL addr(default: 0x200000)\n" + "-v, --version set version (default: 0x01010101)\n" + "-f, --file input file name(spl/img)\n" + "-h, --help show this information\n" + }; + puts(help); +} + +static int parse_args(int argc, char **argv) +{ + uint32_t v; + + enum { + OPTION_CREAD_HDR = 1, + OPTION_FIXED_HDR, + OPTION_SBL_BAK_OFFSET, + OPTION_VERSION, + OPTION_FILENAME, + OPTION_HELP, + }; + + static struct option long_options[] = + { + {"creat-splhdr" , no_argument, NULL, OPTION_CREAD_HDR}, + {"fix-imghdr" , no_argument, NULL, OPTION_FIXED_HDR}, + {"spl-bak-addr" , required_argument, NULL, OPTION_SBL_BAK_OFFSET}, + {"version", required_argument, NULL, OPTION_VERSION}, + {"file", required_argument, NULL, OPTION_FILENAME}, + {"help", no_argument, NULL, OPTION_HELP}, + {0, 0, 0, 0} + }; + + while (1) + { + /* getopt_long stores the option index here. */ + int option_index = 0; + + int c = getopt_long(argc, argv, "cio:v:f:h", long_options, &option_index); + + /* Detect the end of the options. */ + if (c == -1) + break; + + switch (c) { + case 0: + /* If this option set a flag, do nothing else now. */ + if (long_options[option_index].flag != 0) + break; + + case 'c': + case OPTION_CREAD_HDR: + g_hdr_conf.creat_hdr_flag = true; + g_hdr_conf.fixed_img_hdr_flag = false; + break; + + case 'i': + case OPTION_FIXED_HDR: + g_hdr_conf.fixed_img_hdr_flag = true; + g_hdr_conf.creat_hdr_flag = false; + break; + + case 'a': + case OPTION_SBL_BAK_OFFSET: + v = (uint32_t)strtoul(optarg, NULL, 16); + v = htole32(v); + g_hdr_conf.bofs = v; + break; + + case 'v': + case OPTION_VERSION: + v = (uint32_t)strtoul(optarg, NULL, 16); + v = htole32(v); + g_hdr_conf.vers = v; + break; + + case 'f': + case OPTION_FILENAME: + strcpy((char*)g_hdr_conf.name, optarg); + break; + + case 'h': + case OPTION_HELP: + usage(); + break; + + default: + usage(); + break; + } + } + return 0; +} + +int spl_creat_hdr(struct hdr_conf_t *conf) +{ + int fd; + uint32_t v; + size_t sz; + + if (!conf->creat_hdr_flag) + return 0; + + ubsplhdr.sofs = htole32(0x240U); + ubsplhdr.res1 = htole32(0x400U); + ubsplhdr.bofs = conf->bofs ? conf->bofs : htole32(DEFBACKUP); + ubsplhdr.vers = conf->vers ? conf->vers : htole32(DEFVERSID); + + printf("ubsplhdr.sofs:%#x, ubsplhdr.bofs:%#x, ubsplhdr.vers:%#x name:%s\n", + ubsplhdr.sofs, ubsplhdr.bofs, ubsplhdr.vers, conf->name); + + fd = open(conf->name, O_RDONLY); + if (fd == -1) xerror(errno, conf->name); + + sz = (size_t)read(fd, ubootspl, sizeof(ubootspl)); + if (sz == NOSIZE) xerror(errno, conf->name); + if (sz >= (sizeof(ubootspl))) + xerror(0, "File too large! Please rebuild your SPL with -Os. Maximum allowed size is 180048 bytes."); + v = htole32((uint32_t)sz); + ubsplhdr.fsiz = v; + + close(fd); + snprintf(outpath, sizeof(outpath), "%s.normal.out", conf->name); + fd = creat(outpath, 0666); + if (fd == -1) xerror(errno, outpath); + + v = crc32(~0U, 0x04c11db7U, ubootspl, sz); + v = crc32_final(v); + v = htole32(v); + ubsplhdr.crcs = v; + + write(fd, &ubsplhdr, sizeof(struct ubootsplhdr)); + write(fd, ubootspl, sz); + + close(fd); + + printf("SPL written to %s successfully.\n", outpath); + + return 0; +} + +int img_fixed_hdr(struct hdr_conf_t *conf) +{ + int fd; + size_t sz; + + if (!conf->fixed_img_hdr_flag) + return 0; + + fd = open(conf->name, O_RDWR); + if (fd == -1) xerror(errno, conf->name); + + sz = (size_t)read(fd, &imghdr, sizeof(imghdr)); + if (sz == NOSIZE) xerror(errno, conf->name); + + /* When starting with emmc, bootrom will read 0x0 instead of partition 0. (Known issues). + Read GPT PMBR+Header, then write the backup address at 0x4, and write the wrong CRC + check value at 0x290, so that bootrom CRC check fails and jump to the backup address + to load the real spl. */ + + imghdr.bofs = conf->bofs ? conf->bofs : htole32(DEFBACKUP); + imghdr.crcs = htole32(CRCFAILED); + + lseek(fd, 0x0, SEEK_SET); + write(fd, &imghdr, sizeof(imghdr)); + close(fd); + + printf("IMG %s fixed hdr successfully.\n", conf->name); + + return 0; +} + +int main(int argc, char **argv) +{ + parse_args(argc, argv); + spl_creat_hdr(&g_hdr_conf); + img_fixed_hdr(&g_hdr_conf); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286 Gerrit-Change-Number: 83849 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: arch/riscv: Add common FDT build
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83848?usp=email ) Change subject: arch/riscv: Add common FDT build ...................................................................... arch/riscv: Add common FDT build Currently all platforms on RISC-V require a FDT. The inclusion of the FDT is currently done in the platform Makefiles. In order to factor out some common code this patch adds the inclusion in the architecture Makefile. The FDT must be aligned to 8 byte according to device tree spec. It avoids misaligned access. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I3b304a89646fe84c98e9f199f315bebb156de16c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83848 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk 2 files changed, 38 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index b7fc0ca..8fa7854 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -144,4 +144,19 @@ SOC/Mainboards select this option in case the number of harts is not known at build time. In this case the SOC must have a scheme in place to discover all harts. +config RISCV_DTS + bool + default n + help + This option is selected by mainboards that include a devicetree + source file (not to be confused with the coreboot devicetree.cb files). + The devicetree will be preprocessed and compiled into a FDT (flattened devicetree). + Said FDT will be put into a CBFS file for use in runtime. + +config RISCV_DTS_FILE + string + depends on RISCV_DTS + help + Path to the devicetree source file in .dts format. + endif # if ARCH_RISCV diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index bda392a..3efd895 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -67,6 +67,29 @@ $(top)/src/lib/memset.c all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c +## FDT (Flattened Devicetree) inclusion + +ifeq ($(CONFIG_RISCV_DTS),y) + +# at some point dtc may be compiled by our toolchain +DTC ?= dtc +CPPFLAGS_dts += -nostdinc -P -x assembler-with-cpp -I src/arch/riscv/include + +$(obj)/preprocessed.dts: $(call strip_quotes, $(CONFIG_RISCV_DTS_FILE)) + $(CPP_riscv) $(CPPFLAGS_dts) -o $@ $< + +$(obj)/dtb: $(obj)/preprocessed.dts + $(DTC) -I dts -O dtb -o $@ $< + +# This may be optimized in the future by letting cbfstool parse our FDT into a unflattened +# devicetree blob in build time, so that we only need to flatten it in runtime instead of +# unflatten and flatten it in runtime. +cbfs-files-y += DTB +DTB-file := $(obj)/dtb +DTB-type := raw +DTB-align := 8 # according to spec device trees needs to be 8 byte aligned + +endif # CONFIG_RISCV_DTS ################################################################################ ## bootblock -- To view, visit https://review.coreboot.org/c/coreboot/+/83848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b304a89646fe84c98e9f199f315bebb156de16c Gerrit-Change-Number: 83848 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>

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