coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email ) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:53:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: lib: Introduce early power off support Kconfig option
by Julius Werner (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Karthik Ramasubramanian, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86417?usp=email ) Change subject: lib: Introduce early power off support Kconfig option ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86417?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05b9882e100825a4fb733163a65f820c8c943361 Gerrit-Change-Number: 86417 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:53:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: amdfwtool: Set entry address mode based on current table header
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84530?usp=email ) Change subject: amdfwtool: Set entry address mode based on current table header ...................................................................... amdfwtool: Set entry address mode based on current table header The address field of each PSP or BIOS entry defines the location of the entry. For the family newer than Cezanne, the upper 2 bits define the address mode. In table header, the address mode of the table is set. They have the same definition. Address Mode 0: Physical Address Address Mode 1: Relative Address to entire BIOS image Address Mode 2: Relative Address to PSP/BIOS directory Address Mode 3: Relative Address to slot N In common case, the address mode of entry should be the same as its table. In spec, it says, "attribute is ignored if the directory address mode is not 2 or 3", In the old code, if the header defines address mode as relative BIOS(1), the entry address mode is not set. That meets the spec. PSP doesn't use, but amdfwtool can use it to record the address mode and transfer it to table. That can reduce the code complexity. Identidal binary test passes on platforms which are not based on Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne. Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84530 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 8 insertions(+), 3 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 7f17b71..42d13d8 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -382,10 +382,15 @@ #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \ (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) -/* Only set the address mode in entry if the table is mode 2. */ +/* AMD PSP Spec: Only set the address mode in entry if the table is mode 2 or 3. */ +/* For address mode 3, it is not be used in any SOC family yet. + For address mode 1, we can use it to store and transfer the address mode. + It can reduce the complexity. */ #define SET_ADDR_MODE(table, mode) \ - ((table)->header.additional_info_fields.address_mode == \ - AMD_ADDR_REL_TAB ? (mode) : 0) + ((table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_TAB || \ + (table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_BIOS || \ + (table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_SLOT \ + ? (mode) : 0) #define SET_ADDR_MODE_BY_TABLE(table) \ SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode) -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 15 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>

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[S] Change in coreboot[main]: amdfwtool: Set entry address mode based on current table header
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Bao Zheng, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Felix Held has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84530?usp=email ) Change subject: amdfwtool: Set entry address mode based on current table header ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 14 Feb 2025 16:50:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/glinda: Fix pci int defs
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Ana Carolina Cabral, Marshall Dawson, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86421?usp=email ) Change subject: soc/amd/glinda: Fix pci int defs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: good catch -- To view, visit https://review.coreboot.org/c/coreboot/+/86421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I702f16e681d57c5e44f91c805a9aeb71eb160bd3 Gerrit-Change-Number: 86421 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:48:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Alicja Michalska, Matt DeVillier, Maximilian Brune, Paul Menzel. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84500?usp=email ) Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 16:48:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.22.0
by Yidi Lin (Code Review) 14 Feb '25

14 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/blobs/+/86380?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.22.0 ...................................................................... soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.22.0 Update mtk_fsp_ramstage.elf includes: - Disable clock for Crypto hardware. - Add build version info. TEST=Build pass BUG=b:317009620 Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md M soc/mediatek/mt8196/mtk_fsp_ramstage.elf M soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 M soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 4 files changed, 13 insertions(+), 2 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Verified; Looks good to me, approved diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index 1834120..aada670 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -267,6 +267,7 @@ - MMinfra (Multimedia Infrastrucutre) settings. - SMPU (Security Memory Protection Unit) settings. - Advanced CPU frequency control. +- Disable clock for Crypto hardware. ## Who uses it Coreboot loads `mtk_fsp_ramstage.elf` during the first bootup. @@ -280,7 +281,7 @@ 0 on success; non-zero on failure. ## Version -`$ strings mtk_fsp_ramstage.elf | grep "interface version"` +`$ strings mtk_fsp_ramstage.elf | grep "build version"` -------------------------------------------------------------------------------- # libbl31.a introduction diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf index 783eb66..e363b3b 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf Binary files differ diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 index 3e6085f..2fac575 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 @@ -1 +1 @@ -3b4068efe7b6c5aebc2379985c5316e4 *mtk_fsp_ramstage.elf +d003c56a9cb53d8d3e09bf6cc6881520 *mtk_fsp_ramstage.elf diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt b/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt index b63d1e6..579d8cb 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt @@ -1,3 +1,13 @@ +# 16174.22.0 + +1. An official build from ChromeOS version 16174.22.0. + +2. Included changes: + +- CL:*8013108 mtk-fsp: Add build version info +- CL:*8009008 mt8196: Disable clock for Crypto hardware +- CL:*7980492 mt8196/kraken_v3: Call dsb() after writing to CSRAM + # 1.0 1. An official build from ChromeOS version 16180.0.0. -- To view, visit https://review.coreboot.org/c/blobs/+/86380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Gerrit-Change-Number: 86380 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add libbl31.a version 16174.21.0
by Yidi Lin (Code Review) 14 Feb '25

14 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/blobs/+/86382?usp=email ) Change subject: soc/mediatek/mt8196: Add libbl31.a version 16174.21.0 ...................................................................... soc/mediatek/mt8196: Add libbl31.a version 16174.21.0 The libbl31.a is a static library that contains MediaTek proprietary drivers for ARM trusted firmware. The feature includes: - UFS driver - SMPU (Security Memory Protection Unit) driver - SLBC driver - CPU QOS driver - MMinfra driver - SMMU SID driver BRANCH=rauru BUG=b:317009620 TEST=Build pass with static library. Boot ok. Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Signed-off-by: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/libbl31.a A soc/mediatek/mt8196/libbl31.a.md5 A soc/mediatek/mt8196/libbl31_release_note.txt 4 files changed, 27 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Verified; Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index 4f5ee64..1834120 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -9,6 +9,7 @@ - pi_img.img - mtk_fsp_romstage.elf - mtk_fsp_ramstage.elf +- libbl31.a -------------------------------------------------------------------------------- # MCUPM introduction @@ -282,3 +283,19 @@ `$ strings mtk_fsp_ramstage.elf | grep "interface version"` -------------------------------------------------------------------------------- +# libbl31.a introduction +It is a static library that contains MediaTek private drivers in ARM-Trusted-Firmware such as: + +- UFS driver +- SMPU (Security Memory Protection Unit) driver +- SLBC driver +- CPU QOS driver +- MMinfra driver +- SMMU SID driver + +## Who uses it +By specifying the `MTKLIB_PATH=libbl31.a` make variable when building BL31, the library will be +linked with `bl31.elf`. + +## Version +`$ strings libbl31.a | grep "build version"` diff --git a/soc/mediatek/mt8196/libbl31.a b/soc/mediatek/mt8196/libbl31.a new file mode 100644 index 0000000..f758652 --- /dev/null +++ b/soc/mediatek/mt8196/libbl31.a Binary files differ diff --git a/soc/mediatek/mt8196/libbl31.a.md5 b/soc/mediatek/mt8196/libbl31.a.md5 new file mode 100644 index 0000000..7aa5560 --- /dev/null +++ b/soc/mediatek/mt8196/libbl31.a.md5 @@ -0,0 +1 @@ +0316f5be548efda05e915d2cd7d0f179 *libbl31.a diff --git a/soc/mediatek/mt8196/libbl31_release_note.txt b/soc/mediatek/mt8196/libbl31_release_note.txt new file mode 100644 index 0000000..c0f5c9b --- /dev/null +++ b/soc/mediatek/mt8196/libbl31_release_note.txt @@ -0,0 +1,9 @@ +# 16174.21.0 + +1. Included patches: + +- CL:*8020869 CHROMIUM: fix(mt8196): remove duplicate mapping from smmu_sid +- CL:*8004011 feat(mt8196): add mminfra and smmu_sid drivers +- CL:*8004010 feat(mt8196): add MT8196 slbc and cpu_qos drivers +- CL:*8004009 feat(mt8196): add MT8196 SMPU driver +- CL:*8004008 feat(mt8196): add MT8196 UFS driver -- To view, visit https://review.coreboot.org/c/blobs/+/86382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Gerrit-Change-Number: 86382 Gerrit-PatchSet: 6 Gerrit-Owner: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: device/pci_rom: Move VBIOS checksum fix
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86384?usp=email ) Change subject: device/pci_rom: Move VBIOS checksum fix ...................................................................... device/pci_rom: Move VBIOS checksum fix Move the VBIOS checksum code into the soc/amd folder, as it's specific to AMD's FSP. The code now fixes the VBIOS in place instead only fixing it for the VFCT table. TEST: VBIOS has correct checksum after loading in BS_DEV_RESOURCES. VBIOS checksum is invalid entering graphics_dev_init(). VBIOS checksum is correct leaving graphics_dev_init(). Change-Id: I63aaaefaf01ea456e2ed39cd0891e552a7fb5135 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86384 Reviewed-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pci_rom.c M src/soc/amd/common/fsp/fsp_graphics.c 2 files changed, 20 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Ana Carolina Cabral: Looks good to me, but someone else must approve diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 7e19646d..0fe94db 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -242,15 +242,6 @@ vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; - /* Calculate and set checksum for VBIOS data if FSP GOP driver used, - Since GOP driver modifies ATOMBIOS tables at end of VBIOS */ - if (CONFIG(RUN_FSP_GOP)) { - /* Clear existing checksum before recalculating */ - header->VbiosContent[VFCT_VBIOS_CHECKSUM_OFFSET] = 0; - header->VbiosContent[VFCT_VBIOS_CHECKSUM_OFFSET] = - acpi_checksum(header->VbiosContent, header->ImageLength); - } - current += header->ImageLength; return current; } diff --git a/src/soc/amd/common/fsp/fsp_graphics.c b/src/soc/amd/common/fsp/fsp_graphics.c index 3e082e6..776711b 100644 --- a/src/soc/amd/common/fsp/fsp_graphics.c +++ b/src/soc/amd/common/fsp/fsp_graphics.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <amdblocks/graphics.h> +#include <amdblocks/vbt.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -15,4 +16,23 @@ else printk(BIOS_ERR, "%s: Unable to find resource for %s\n", __func__, dev_path(dev)); + + /* + * Calculate and set checksum for VBIOS data if FSP GOP driver used, + * Since GOP driver modifies ATOMBIOS tables at end of BS_DEV_RESOURCES. + * While Linux does not verify the checksum the Windows kernel driver does. + */ + struct rom_header *vbios = (struct rom_header *)vbt_get(); + if (!vbios || !vbios->size) { + printk(BIOS_ERR, "%s: No VGA BIOS loaded for %s\n", + __func__, dev_path(dev)); + return; + } + + uint8_t *data = (uint8_t *)vbios; + + /* Clear existing checksum before recalculating */ + data[VFCT_VBIOS_CHECKSUM_OFFSET] = 0; + data[VFCT_VBIOS_CHECKSUM_OFFSET] = + acpi_checksum(data, vbios->size * 512); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86384?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63aaaefaf01ea456e2ed39cd0891e552a7fb5135 Gerrit-Change-Number: 86384 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: device/pci_rom: Use correct endian conversion
by Felix Held (Code Review) 14 Feb '25

14 Feb '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86383?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device/pci_rom: Use correct endian conversion ...................................................................... device/pci_rom: Use correct endian conversion The Option ROM contains lots of 16bit values that are being used, thus use the 16bit endianness conversion function over the 32bit variant to avoid confusion. TEST: Still works on amd/birman+. Change-Id: I571be97a930ad018e1d1316117cefe5bd1c68f9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86383 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/pci_rom.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: Andy Ebrahiem: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index d60720e..7e19646d 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -93,16 +93,16 @@ printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n", - le32_to_cpu(rom_header->signature), - rom_header->size * 512, le32_to_cpu(rom_header->data)); + le16_to_cpu(rom_header->signature), + rom_header->size * 512, le16_to_cpu(rom_header->data)); - if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) { + if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) { printk(BIOS_ERR, "Incorrect expansion ROM header signature %04x\n", - le32_to_cpu(rom_header->signature)); + le16_to_cpu(rom_header->signature)); return NULL; } - rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data)); + rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data)); printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n", rom_data->vendor, rom_data->device); @@ -144,9 +144,9 @@ + image_size); rom_data = (struct pci_data *)((void *)rom_header - + le32_to_cpu(rom_header->data)); + + le16_to_cpu(rom_header->data)); - image_size = le32_to_cpu(rom_data->ilen) * 512; + image_size = le16_to_cpu(rom_data->ilen) * 512; } while ((rom_data->type != 0) && (rom_data->indicator != 0)); // make sure we got x86 version if (rom_data->type != 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/86383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I571be97a930ad018e1d1316117cefe5bd1c68f9b Gerrit-Change-Number: 86383 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit February 2025