coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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2886 discussions

[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86402?usp=email ) Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... Patch Set 8: (1 comment) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/86402/comment/121a8aee_783fceaf?us… : PS8, Line 1240: #if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI) you can use a single `#if` block here for the whole thing, since `wifi_cnvi_fill_ssdt` is only used/referenced if the Kconfig is selected -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 14 Feb 2025 19:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/usb/acpi: Account for GPIO polarity
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86400?usp=email ) Change subject: drivers/usb/acpi: Account for GPIO polarity ...................................................................... Patch Set 7: (1 comment) File src/drivers/usb/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/86400/comment/9f40ea48_dd89f492?us… : PS7, Line 95: void acpi_device_intel_bt_common(const struct acpi_gpio *reset_gpio, : const struct acpi_gpio *enable_gpio); > You swapped the two variables which technically seems like a good idea as it improves consistency bu […] I'm not seeing any instances which were not properly updated in the patch, is there something I'm not seeing? -- To view, visit https://review.coreboot.org/c/coreboot/+/86400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib481d49d536b702fef149af882209501c61de6da Gerrit-Change-Number: 86400 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 14 Feb 2025 19:44:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/amd/common/acp: Add host bridge interface for CZN
by Matt DeVillier (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/77703?usp=email ) Change subject: soc/amd/common/acp: Add host bridge interface for CZN ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/acp/acp.c: https://review.coreboot.org/c/coreboot/+/77703/comment/feea3e9f_444e71e2?us… : PS2, Line 55: NotSerialized > I agree, not sure why it was originally written this way Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I282f1fa2898f76659700450ee1f4b11f79d2d030 Gerrit-Change-Number: 77703 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Feb 2025 19:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add Touch Controller UPD and SoC config
by Cliff Huang (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik. Hello Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85199?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+1 by Bora Guvendik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Add Touch Controller UPD and SoC config ...................................................................... soc/intel/pantherlake: Add Touch Controller UPD and SoC config Configure ThcAssignment, ThcMode, and ThcWakeOnTouch UPDs according to the SoC chip configuration from the devicetree. This includes: - Implement override functions to deliver SoC-specific configurations for the Touch Controller (THC) - Add SoC-specific THC header - Add MB-specific THC header - build path for devicetree to utilize variant-specific defines BUG=none TEST=This will require MB changes for testing Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e --- M src/soc/intel/pantherlake/Makefile.mk M src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/include/soc/touch.h 5 files changed, 146 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85199/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 15 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add support for VMD device
by Jérémy Compostella (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik. Jérémy Compostella has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/86301?usp=email ) Change subject: soc/intel/pantherlake: Add support for VMD device ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/86301/comment/99629328_c49cf521?us… : PS3, Line 564: const struct soc_intel_pantherlake_config *config) The indentation does not comply with the rest of the file. https://review.coreboot.org/c/coreboot/+/86301/comment/0998d18c_f75ec4d9?us… : PS3, Line 566: /* VMD */ This comment does not serve any purpose. -- To view, visit https://review.coreboot.org/c/coreboot/+/86301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43 Gerrit-Change-Number: 86301 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 18:56:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Jérémy Compostella (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Felix Singer, Filip Lewiński, Intel coreboot Reviewers, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Jérémy Compostella has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... Patch Set 6: (4 comments) File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/83730/comment/147ef20d_96695831?us… : PS6, Line 19: #define MSR_IA32_DEBUG_INTERFACE 0xc80 It seems to be an extra tab It also seems to be places between `MSR_BOOT_GUARD_SACM_INFO` and its bits definition. File src/soc/intel/cannonlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/83730/comment/dc1af6a1_38b8e447?us… : PS6, Line 11: #define MSR_IA32_DEBUG_INTERFACE_EN (1 << 0) : #define MS Shouldn't it be in src/include/cpu/intel/msr.h ? Shouldn't it use the BIT macro ? https://review.coreboot.org/c/coreboot/+/83730/comment/6ff3a860_6f7bb87b?us… : PS6, Line 14: static void cpu_lockdown_cfg(void) Could it be called `lock_debug_interface` instead ? https://review.coreboot.org/c/coreboot/+/83730/comment/4ffb44e5_efcf5298?us… : PS6, Line 18: if (!(msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)) { ``` if (msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK) return; if (CONFIG(INTEL_TXT)) msr.lo &= ~MSR_IA32_DEBUG_INTERFACE_EN; msr.lo |= MSR_IA32_DEBUG_INTERFACE_LOCK; wrmsr(MSR_IA32_DEBUG_INTERFACE, msr); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 18:55:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization
by Johannes Hahn (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86424?usp=email ) Change subject: src/mainboard/siemens/fa_ehl: Configure LPDDR4 initialization ...................................................................... Patch Set 4: (1 comment) File src/mainboard/siemens/fa_ehl/Kconfig: https://review.coreboot.org/c/coreboot/+/86424/comment/591ed8fc_04639f1b?us… : PS2, Line 9: select HAVE_SPD_IN_CBFS > `trailing whitespace` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/86424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b Gerrit-Change-Number: 86424 Gerrit-PatchSet: 4 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 18:13:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: drivers/intel/touch: Add Intel Touch Controller driver
by Cliff Huang (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim, Paul Menzel, Subrata Banik. Hello Bora Guvendik, Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85198?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/touch: Add Intel Touch Controller driver ...................................................................... drivers/intel/touch: Add Intel Touch Controller driver THC is a hardware component that interfaces between a touch sensor and the system's SPI or I2C bus. This driver publishes data into the Secondary System Descriptor Table (SSDT). This driver generates the following ACPI objects: - Device Specific Method (_DSM) - Current Resource Settings (_CRS) - Power resource with Status (_STA), _ON, and _OFF methods - Device Specific Data (_DSD) for THC-I2C - Device Reset (_RST) for THC-SPI Template device configuration for the following supported devices: - Wacom: THC-SPI touchscreen only - Elan: both THC-SPI and THC-I2C touchscreen - Hynitron: THC-I2C touchpad only The configuration is spitted into device, SoC, and MB specific. - SoC-specific: Implement soc_get_thc_hidi2c_info and soc_get_thc_hidspi_info functions for SoC-specific configurations. Theses can be placed in the SoC's chip.c. - device-specific: This driver provides the device-specific configuration for the supported devices; otherwise, require information via the device tree for unsupported/generic devices. - MB-specific: The MB-specific, such as LTR value, needs to be provided in the device tree. BUG=none TEST=Select DRIVERS_INTEL_TOUCH in a MB with the necessary configs, and check if the THC ACPI tables are generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf --- A src/drivers/intel/touch/Kconfig A src/drivers/intel/touch/Makefile.mk A src/drivers/intel/touch/chip.h A src/drivers/intel/touch/elan.h A src/drivers/intel/touch/hynitron.h A src/drivers/intel/touch/touch.c A src/drivers/intel/touch/wacom.h 7 files changed, 966 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85198/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf Gerrit-Change-Number: 85198 Gerrit-PatchSet: 13 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Cliff Huang (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86290/comment/b813a9ab_6e29c861?us… : PS7, Line 53: > > @Subrata, Yes. […] sure. added, -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 18:09:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Cliff Huang (Code Review) 14 Feb '25

14 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86290?usp=email to look at the new patch set (#9). Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... soc/intel/pantherlake: Enable multiple ACPI devices for GPIO In the Panther Lake architecture, each GPIO community functions as a separate pin control entity. Therefore, when specifying a GPIO identifier, one should use the community-specific offset, not the number from the first pad within the GPIO series. This is achieved by selecting the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within the Panther Lake SOC Kconfig file. The numbers within the _CRS GpioInt and GpIo objects in the SSDT should be offsets within the community. The GPIO identifier employed should correspond to the offset from the respective community. Let's take an example. In the fatcat board overridetree.cb, ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad starts at 74. It is inside community 1, which starts at 48. The correct GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal. Here are two notable changes in the fatcat board SSDT introduced by this commit. - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) "\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 + 0x002D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16) "\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, , ) { // Pin list - 0x0050 + 0x003B } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data This change is verified via S0ix in Google Fatcat board with touchscreen/touchpad attached as the wake source. BUG=none TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and ensure that the GPIO number used matches the community offset. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/86290/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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coreboot-gerrit February 2025