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Change subject: [This Must Fail]Upgrade GCC to 15-20250119 Snapshot
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> This must fail to build at least emulation/qemu-i440fx ! […]
Jenkins is not using GCC-15-20250119 otherwise it must fail.
Something is definitely wrong
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Change subject: [LLVM test]: Use compiler-rt
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
"make[2]: Entering directory '/home/coreboot/node-root/workspace/coreboot-gerrit'
Updating git submodules.
payloads/external/Makefile.mk:399: "Using host toolchain to build Linuxboot"
OPTION option_table.h
HOSTCC cbfstool/fmd_parser.o
HOSTCC cbfstool/fmd_scanner.o
HOSTCC /cb-build/coreboot-gerrit.0/emu_clang_allthreads/sharedutils/sconfig/sconfig (link)
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/gdt_init.o
CC romstage/arch/x86/idt.o
GEN build.h
make[2]: *** No rule to make target '/opt/xgcc/lib/clang/18/lib/baremetal/libclang_rt.builtins-i386.a', needed by '/cb-build/coreboot-gerrit.0/emu_clang_allthreads/EMULATION_QEMU_X86_Q35/smm/smm.elf'. Stop.
make[2]: *** Waiting for unfinished jobs....
CC smm/arch/x86/idt.o
make[2]: Leaving directory '/home/coreboot/node-root/workspace/coreboot-gerrit'"
We have a problem using host toolchain, isn't it?
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Change subject: mb/google/nissa/var/telith: Configure Acoustic noise mitigation
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add PI_IMG firmware v1.0
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Note that this PI_IMG still contains unused sections. The concern in b/384392390 has not been addressed.
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Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84530?usp=email
to look at the new patch set (#13).
Change subject: amdfwtool: Set entry address mode based on current table header
......................................................................
amdfwtool: Set entry address mode based on current table header
The address field of each PSP or BIOS entry defines the location of
the entry.
For the family newer than Cezanne, the upper 2 bits define the address
mode. In table header, the address mode of the table is set. They have
the same definition.
Address Mode 0: Physical Address
Address Mode 1: Relative Address to entire BIOS image
Address Mode 2: Relative Address to PSP/BIOS directory
Address Mode 3: Relative Address to slot N
In common case, the address mode of entry should be the same as its
table. In spec, it says, "attribute is ignored if the directory
address mode is not 2 or 3",
In the old code, if the header defines address mode as relative BIOS(1),
the entry address mode is not set. That meets the spec. PSP doesn't
use, but amdfwtool can use it to record the address mode and transfer
it to table. That can reduce the code complexity.
Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.
Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84530/13
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Change subject: mb/google/corsola: fine tune the data lane trail
......................................................................
Patch Set 1:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86101/comment/3be2de75_d9adccf2?us… :
PS1, Line 7: fine tune the data lane trail
More specific:
> Increase ANX7625 data trail time
https://review.coreboot.org/c/coreboot/+/86101/comment/7e686e82_486ef55b?us… :
PS1, Line 8:
Please start by describing the problem, like: Currently, the display flickers.
https://review.coreboot.org/c/coreboot/+/86101/comment/02eaa915_b4368dd0?us… :
PS1, Line 9: ANX7625 requires customized hs_da_trail time
Why? According to the schematics?
https://review.coreboot.org/c/coreboot/+/86101/comment/02aea16e_583bcfe7?us… :
PS1, Line 9: override the
: data trail for ANX7625
What is the current value, and what is the new value? Why is the new value correct?
File src/mainboard/google/corsola/panel_anx7625.c:
https://review.coreboot.org/c/coreboot/+/86101/comment/01d466a0_c0cba690?us… :
PS1, Line 69: timing->da_hs_trail += 9;
Maybe better use the absolute value, or does it always need to be increased by nine?
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Change subject: [This Must Fail]Upgrade GCC to 15-20250119 Snapshot
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This must fail to build at least emulation/qemu-i440fx !
So Jenkins is doing something wrong.
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Change subject: mb/asus: Add Maximus VI Gene (Haswell)
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/asus/maximus_vi_gene/Kconfig:
https://review.coreboot.org/c/coreboot/+/85767/comment/b0b02a5c_88129271?us… :
PS7, Line 8: DRIVERS_ASMEDIA_ASPM_BLACKLIST
> Needs rebase; this was changed to `DRIVERS_ASMEDIA_ASM1061` as of commit fee8bcbcfb55 ("drivers/asme […]
Done
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