coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct USB port configuration for cameras
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86064?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starlite_adl: Correct USB port configuration for cameras ...................................................................... mb/starlabs/starlite_adl: Correct USB port configuration for cameras Both cameras share the same USB 2.0 interface, rather than using their own port. Update the configuration to match this. Change-Id: Ia2d8698394de69af53489e3a08c7fe7b4f2fbc07 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86064 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/cfr.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 4 files changed, 5 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig index 55a66be..51b762b 100644 --- a/src/mainboard/starlabs/starlite_adl/Kconfig +++ b/src/mainboard/starlabs/starlite_adl/Kconfig @@ -41,7 +41,7 @@ config CCD_PORT int - default 4 + default 5 config CONSOLE_SERIAL default n if !EDK2_DEBUG diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c index 4cd31d9..69635bb 100644 --- a/src/mainboard/starlabs/starlite_adl/cfr.c +++ b/src/mainboard/starlabs/starlite_adl/cfr.c @@ -27,13 +27,6 @@ SM_ENUM_VALUE_END }, }); -static const struct sm_object camera = SM_DECLARE_BOOL({ - .opt_name = "camera", - .ui_name = "Camera", - .ui_helptext = "Enable or disable the built-in camera", - .default_value = true, -}); - #if CONFIG(EC_STARLABS_CHARGING_SPEED) static const struct sm_object charging_speed = SM_DECLARE_ENUM({ .opt_name = "charging_speed", @@ -270,7 +263,6 @@ .ui_name = "Devices", .obj_list = (const struct sm_object *[]) { &accelerometer, - &camera, #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) &gna, #endif diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 9abba7e..8c87eff 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -60,12 +60,9 @@ # Detachable Keyboard + SD Card Reader register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" - # Internal Webcam + # Camera + Webcam register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" - # Camera - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" - # Internal Bluetooth register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" @@ -102,14 +99,8 @@ device ref usb2_port3 on end end chip drivers/usb/acpi - register "desc" = ""Internal Webcam"" - register "type" = "UPC_TYPE_INTERNAL" - register "group" = "ACPI_PLD_GROUP(0, 3)" - device ref usb2_port5 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" + register "desc" = ""USB 2.0 Hub"" + register "type" = "UPC_TYPE_HUB" register "group" = "ACPI_PLD_GROUP(0, 4)" device ref usb2_port6 on end end diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c index 4ace9b5..c2a95f7 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c @@ -57,14 +57,10 @@ nic_dev->enabled = 0; } - /* Enable/Disable Webcam based on CMOS settings */ + /* Enable/Disable Webcam/Camera based on CMOS settings */ if (get_uint_option("webcam", 1) == 0) cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0; - /* Enable/Disable Camera based on CMOS settings */ - if (get_uint_option("camera", 1) == 0) - cfg->usb2_ports[5].enable = 0; - /* Enable/Disable Touchscreen based on CMOS settings */ if (get_uint_option("touchscreen", 1) == 0) touchscreen_dev->enabled = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/86064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2d8698394de69af53489e3a08c7fe7b4f2fbc07 Gerrit-Change-Number: 86064 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct USB Port comments
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86063?usp=email ) Change subject: mb/starlabs/starlite_adl: Correct USB Port comments ...................................................................... mb/starlabs/starlite_adl: Correct USB Port comments The comments are the wrong way round. Change-Id: Ifd46cd7e633f37e57213fffee4f70a7262894100 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86063 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 5674b33..9abba7e 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -49,11 +49,11 @@ end device ref gna on end device ref xhci on - # Top USB 3.0 Type-C + # Bottom USB 3.0 Type-C register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" - # Bottom USB 3.0 Type-C + # Top USB 3.0 Type-C register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" @@ -72,25 +72,25 @@ chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""Top USB Type-C"" + register "desc" = ""Bottom USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""Top USB Type-C"" + register "desc" = ""Bottom USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb3_port3 on end end chip drivers/usb/acpi - register "desc" = ""Bottom USB Type-C"" + register "desc" = ""Top USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 1)" device ref usb2_port2 on end end chip drivers/usb/acpi - register "desc" = ""Bottom USB Type-C"" + register "desc" = ""Top USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 1)" device ref usb3_port1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/86063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd46cd7e633f37e57213fffee4f70a7262894100 Gerrit-Change-Number: 86063 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/corsola: fine tune the data lane trail
by Xin Ji (Code Review) 22 Jan '25

22 Jan '25

Xin Ji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86101?usp=email ) Change subject: mb/google/corsola: fine tune the data lane trail ...................................................................... mb/google/corsola: fine tune the data lane trail ANX7625 requires customized hs_da_trail time, override the data trail for ANX7625. BUG= BRANCH=corsola TEST=Display is normal on corsola Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Signed-off-by: Xin Ji <xji(a)analogix.corp-partner.google.com> --- M src/mainboard/google/corsola/panel_anx7625.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86101/1 diff --git a/src/mainboard/google/corsola/panel_anx7625.c b/src/mainboard/google/corsola/panel_anx7625.c index 193a501..048713f 100644 --- a/src/mainboard/google/corsola/panel_anx7625.c +++ b/src/mainboard/google/corsola/panel_anx7625.c @@ -5,6 +5,7 @@ #include <drivers/analogix/anx7625/anx7625.h> #include <edid.h> #include <gpio.h> +#include <soc/dsi.h> #include <soc/i2c.h> #include "gpio.h" @@ -62,3 +63,8 @@ mtk_i2c_bus_init(BRIDGE_I2C, I2C_SPEED_FAST); return &anx7625_bridge; } + +void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) +{ + timing->da_hs_trail += 9; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Gerrit-Change-Number: 86101 Gerrit-PatchSet: 1 Gerrit-Owner: Xin Ji <xji(a)analogix.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/9db2c908_09257ff0?us… : PS10, Line 14: #include <soc/pmif.h> : #include <soc/spmi.h> Do we still need these two headers after using mt6685 API ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 08:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: lib/crc_byte: Parenthesize buffer address in CRC macro
by Angel Pons (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Filip Brozovic, Matt DeVillier, Sean Rhodes. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86099?usp=email ) Change subject: lib/crc_byte: Parenthesize buffer address in CRC macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Gerrit-Change-Number: 86099 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 08:00:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: [This Must Fail]Upgrade GCC to 15-20250119 Snapshot
by Elyes Haouas (Code Review) 22 Jan '25

22 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86100?usp=email ) Change subject: [This Must Fail]Upgrade GCC to 15-20250119 Snapshot ...................................................................... [This Must Fail]Upgrade GCC to 15-20250119 Snapshot Must fail, otherwise there is a problem! Change-Id: I5e6c3745eebeb6ded494c153010283b761498184 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-15-20250119_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20250119_gnat.patch R util/crossgcc/patches/gcc-15-20250119_libcpp.patch R util/crossgcc/patches/gcc-15-20250119_libgcc.patch R util/crossgcc/patches/gcc-15-20250119_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20250119_rv32iafc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20250119.tar.xz.cksum 9 files changed, 48 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86100/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 2d112eb..d6f408a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,7 +38,7 @@ GMP_VERSION=6.3.0 MPFR_VERSION=4.2.1 MPC_VERSION=1.3.1 -GCC_VERSION=14.2.0 +GCC_VERSION=15-20250119 LIBSTDCXX_VERSION="${GCC_VERSION}" BINUTILS_VERSION=2.43.1 IASL_VERSION=20241212 @@ -74,7 +74,7 @@ GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" -GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +GCC_BASE_URL="https://gcc.gnu.org/pub/gcc/snapshots/${GCC_VERSION}" LIBSTDCXX_BASE_URL="${GCC_BASE_URL}" BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" IASL_BASE_URL="https://github.com/acpica/acpica/releases/download/R2024_12_12" diff --git a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-15-20250119_asan_shadow_offset_callback.patch similarity index 74% rename from util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch rename to util/crossgcc/patches/gcc-15-20250119_asan_shadow_offset_callback.patch index d446025..7e99877 100644 --- a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch +++ b/util/crossgcc/patches/gcc-15-20250119_asan_shadow_offset_callback.patch @@ -37,17 +37,27 @@ index 235e21947..713bf994d 100644 --- a/gcc/asan.cc +++ b/gcc/asan.cc -@@ -1389,13 +1389,28 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, - TREE_ASM_WRITTEN (decl) = 1; +@@ -2086,23 +2086,27 @@ TREE_ASM_WRITTEN (id) = 1; + DECL_ALIGN_RAW (decl) = DECL_ALIGN_RAW (current_function_decl); emit_move_insn (mem, expand_normal (build_fold_addr_expr (decl))); - shadow_base = expand_binop (Pmode, lshr_optab, base, - gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), - NULL_RTX, 1, OPTAB_DIRECT); -- shadow_base -- = plus_constant (Pmode, shadow_base, -- asan_shadow_offset () -- + (base_align_bias >> ASAN_SHADOW_SHIFT)); +- if (asan_dynamic_shadow_offset_p ()) +- { +- ret = expand_normal (get_asan_shadow_memory_dynamic_address_decl ()); +- shadow_base +- = expand_simple_binop (Pmode, PLUS, shadow_base, ret, NULL_RTX, +- /* unsignedp = */ 1, OPTAB_WIDEN); +- shadow_base = plus_constant (Pmode, shadow_base, +- (base_align_bias >> ASAN_SHADOW_SHIFT)); +- } +- else +- { +- shadow_base = plus_constant (Pmode, shadow_base, +- asan_shadow_offset () +- + (base_align_bias >> ASAN_SHADOW_SHIFT)); + if (param_asan_use_shadow_offset_callback) { + rtx addr, shadow_offset_rtx; + ret = init_one_libfunc ("__asan_shadow_offset"); @@ -56,25 +66,24 @@ + addr, ptr_mode); + shadow_offset_rtx = convert_memory_address (Pmode, ret); + shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); ++ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), ++ NULL_RTX, 1, OPTAB_DIRECT); + shadow_base = expand_binop (Pmode, add_optab, shadow_base, -+ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); ++ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); + shadow_base = plus_constant (Pmode, shadow_base, -+ (base_align_bias >> ASAN_SHADOW_SHIFT)); ++ (base_align_bias >> ASAN_SHADOW_SHIFT)); + } else { + shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); ++ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), ++ NULL_RTX, 1, OPTAB_DIRECT); + shadow_base = plus_constant (Pmode, shadow_base, -+ asan_shadow_offset () -+ + (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ } ++ asan_shadow_offset () ++ + (base_align_bias >> ASAN_SHADOW_SHIFT)); + } gcc_assert (asan_shadow_set != -1 && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4); - shadow_mem = gen_rtx_MEM (SImode, shadow_base); ---- gcc-11.1.0/gcc/params.opt~ 2021-05-11 09:02:51.897508677 +0200 -+++ gcc-11.1.0/gcc/params.opt 2021-05-11 09:10:43.692610696 +0200 +--- gcc-15-20250112/gcc/params.opt~ ++++ gcc-15-20250112/gcc/params.opt @@ -50,6 +50,10 @@ Common Joined UInteger Var(param_asan_instrumentation_with_call_threshold) Init(7000) Param Optimization Use callbacks instead of inline code if number of accesses in function becomes greater or equal to this number. diff --git a/util/crossgcc/patches/gcc-14.2.0_gnat.patch b/util/crossgcc/patches/gcc-15-20250119_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_gnat.patch rename to util/crossgcc/patches/gcc-15-20250119_gnat.patch diff --git a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch b/util/crossgcc/patches/gcc-15-20250119_libcpp.patch similarity index 85% rename from util/crossgcc/patches/gcc-14.2.0_libcpp.patch rename to util/crossgcc/patches/gcc-15-20250119_libcpp.patch index 2b0c953..ba60732 100644 --- a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch +++ b/util/crossgcc/patches/gcc-15-20250119_libcpp.patch @@ -1,8 +1,8 @@ GCC with `-Wformat-security -Werror=format-security` hardening options enabled by default rejects some codes in libcpp. This patch fixes them. ---- gcc-8.3.0/libcpp/expr.cc.bak 2020-09-11 15:44:45.770000000 +0900 -+++ gcc-8.3.0/libcpp/expr.cc 2020-09-11 15:46:22.370000000 +0900 +--- gcc-15-20250112/libcpp/expr.cc.bak ++++ gcc-15-20250112/libcpp/expr.cc @@ -794,10 +794,10 @@ if (CPP_OPTION (pfile, c99)) @@ -16,8 +16,8 @@ } result |= CPP_N_INTEGER; ---- gcc-8.3.0/libcpp/macro.cc.bak 2020-09-11 16:01:42.550000000 +0900 -+++ gcc-8.3.0/libcpp/macro.cc 2020-09-11 16:03:47.850000000 +0900 +--- gcc-15-20250112/libcpp/macro.cc.bak ++++ gcc-15-20250112/libcpp/macro.cc @@ -160,7 +160,7 @@ if (m_state == 2 && token->type == CPP_PASTE) { diff --git a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch b/util/crossgcc/patches/gcc-15-20250119_libgcc.patch similarity index 89% rename from util/crossgcc/patches/gcc-14.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-15-20250119_libgcc.patch index 2f75c92..8e93fa2 100644 --- a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch +++ b/util/crossgcc/patches/gcc-15-20250119_libgcc.patch @@ -1,9 +1,9 @@ This enables building on Mac OS and FreeBSD by adding support to their variants of the sed utility. -diff -urN gcc-5.2.0.orig/libgcc/config/t-hardfp gcc-5.2.0/libgcc/config/t-hardfp ---- gcc-5.2.0.orig/libgcc/config/t-hardfp 2015-01-05 04:33:28.000000000 -0800 -+++ gcc-8.1.0/libgcc/config/t-hardfp 2016-04-06 12:04:51.000000000 -0700 +diff -urN gcc-15-20250112.orig/libgcc/config/t-hardfp gcc-15-20250112/libgcc/config/t-hardfp +--- gcc-15-20250112.orig/libgcc/config/t-hardfp ++++ gcc-15-20250112/libgcc/config/t-hardfp @@ -59,21 +59,52 @@ hardfp_func_list := $(filter-out $(hardfp_exclusions),$(hardfp_func_list)) diff --git a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-15-20250119_musl_poisoned_calloc.patch similarity index 81% rename from util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch rename to util/crossgcc/patches/gcc-15-20250119_musl_poisoned_calloc.patch index b66380d..dfbc02b 100644 --- a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch +++ b/util/crossgcc/patches/gcc-15-20250119_musl_poisoned_calloc.patch @@ -2,8 +2,8 @@ "system.h". Work around that by making sure that <sched.h> gets included first. ---- gcc-13.2.0/gcc/ada/adaint.c -+++ gcc-13.2.0.musl/gcc/ada/adaint.c +--- gcc-15-20250112/gcc/ada/adaint.c ++++ gcc-15-20250112.musl/gcc/ada/adaint.c @@ -101,6 +101,10 @@ #include <sys/time.h> #endif @@ -23,8 +23,8 @@ /* glibc versions earlier than 2.7 do not define the routines to handle dynamically allocated CPU sets. For these targets, we use the static ---- gcc-14-20240211/gcc/ada/argv.c -+++ gcc-14-20240211.musl/gcc/ada/argv.c +--- gcc-15-20250112/gcc/ada/argv.c ++++ gcc-15-20250112.musl/gcc/ada/argv.c @@ -51,10 +51,6 @@ #include "system.h" #endif @@ -36,8 +36,8 @@ #ifdef __cplusplus extern "C" { #endif ---- gcc-13.2.0/gcc/ada/cio.c -+++ gcc-13.2.0.musl/gcc/ada/cio.c +--- gcc-15-20250112/gcc/ada/cio.c ++++ gcc-15-20250112.musl/gcc/ada/cio.c @@ -29,6 +29,8 @@ * * ****************************************************************************/ @@ -56,8 +56,8 @@ /* We need L_tmpnam definition */ #include <stdio.h> ---- gcc-13.2.0/gcc/ada/cstreams.c -+++ gcc-13.2.0.musl/gcc/ada/cstreams.c +--- gcc-15-20250112/gcc/ada/cstreams.c ++++ gcc-15-20250112.musl/gcc/ada/cstreams.c @@ -58,14 +58,14 @@ #include "vxWorks.h" #endif @@ -75,7 +75,7 @@ #ifdef __cplusplus extern "C" { ---- gcc-13.2.0/gcc/ada/init.c +--- gcc-15-20250112/gcc/ada/init.c +++ gcc-13.2.0.musl/gcc/ada/init.c @@ -53,6 +53,8 @@ #undef __linux__ @@ -94,8 +94,8 @@ #include "raise.h" #ifdef __cplusplus ---- gcc-13.2.0/gcc/ada/raise.c -+++ gcc-13.2.0.musl/gcc/ada/raise.c +--- gcc-15-20250112/gcc/ada/raise.c ++++ gcc-15-20250112.musl/gcc/ada/raise.c @@ -32,6 +32,8 @@ /* Shared routines to support exception handling. __gnat_unhandled_terminate is shared between all exception handling mechanisms. */ diff --git a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-15-20250119_rv32iafc.patch similarity index 100% rename from util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch rename to util/crossgcc/patches/gcc-15-20250119_rv32iafc.patch diff --git a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum deleted file mode 100644 index f81c535..0000000 --- a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d91ecc3d20ce6298bd95f9b09cc51dc6d3c73ae3 tarballs/gcc-14.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-15-20250119.tar.xz.cksum b/util/crossgcc/sum/gcc-15-20250119.tar.xz.cksum new file mode 100644 index 0000000..a4da9ea --- /dev/null +++ b/util/crossgcc/sum/gcc-15-20250119.tar.xz.cksum @@ -0,0 +1 @@ +92bbfdb77572f813133505a8390fc6a51e885d54 tarballs/gcc-15-20250119.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/86100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e6c3745eebeb6ded494c153010283b761498184 Gerrit-Change-Number: 86100 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: lib/crc_byte: Parenthesize buffer address in CRC macro
by Filip Brozovic (Code Review) 22 Jan '25

22 Jan '25

Filip Brozovic has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/86099?usp=email ) Change subject: lib/crc_byte: Parenthesize buffer address in CRC macro ...................................................................... lib/crc_byte: Parenthesize buffer address in CRC macro This change fixes CRC calculations in cases where an expression calculating the address using pointer arithmetic is passed into the macro. Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Signed-off-by: Filip Brozovic <fbrozovic(a)gmail.com> --- M src/include/crc_byte.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86099/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Gerrit-Change-Number: 86099 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com>

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[XS] Change in coreboot[main]: lib/crc_byte: Parenthesize buffer address in CRC macro
by Filip Brozovic (Code Review) 22 Jan '25

22 Jan '25

Filip Brozovic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86099?usp=email ) Change subject: lib/crc_byte: Parenthesize buffer address in CRC macro ...................................................................... lib/crc_byte: Parenthesize buffer address in CRC macro This changes fixes CRC calculations in cases where an expression calculating the address using pointer arithmetic is passed into the macro. Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Signed-off-by: Filip Brozovic <fbrozovic(a)gmail.com> --- M src/include/crc_byte.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86099/1 diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index 85b7221..972b89a 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -35,7 +35,7 @@ uint32_t crc32_byte(uint32_t prev_crc, uint8_t data); #define CRC(buf, size, crc_func) ({ \ - const uint8_t *_crc_local_buf = (const uint8_t *)buf; \ + const uint8_t *_crc_local_buf = (const uint8_t *)(buf); \ size_t _crc_local_size = size; \ __typeof__(crc_func(0, 0)) _crc_local_result = 0; \ while (_crc_local_size--) { \ -- To view, visit https://review.coreboot.org/c/coreboot/+/86099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Gerrit-Change-Number: 86099 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 9: (1 comment) File src/drivers/intel/fsp2_0/debug.c: https://review.coreboot.org/c/coreboot/+/86001/comment/a1d785f8_39c76d44?us… : PS6, Line 185: if (!CONFIG(USE_CBFS_FILE_OPTION_BACKEND)) > > Not really sure which comment you're referring to but it's possible I may have missed something. > > > > I still don't really understand why you need this. As far as I can tell, the previous code in `fsp_control_log_level()` would just always return `fsp_map_console_log_level()`. With the implementation I proposed, an option file could override that behavior, but if the file doesn't exist it will still fall back to `fsp_map_console_log_level()`. So the default behavior doesn't change? > > > > If your concern is that after this change you want to build ChromeOS images that have the debug FSP built-in but don't enable the debug output by default (unless someone manually overwrote the setting), I think the obvious answer is to just have our ebuild add an option file with value 0 by default? > > I guess what you are asking is to inject CBFS option file by default with value 0 to ensure that FSP log-level stays disabled unless someone overrides it. Wondering if we really need to do this (what if someone deleted those option files then the log-level will be again chatty)? In my latest patch set, I have used FSP_DYNAMIC_ Kconfig which will ensure that the default log level is 0 and that might eliminate the need for any ebuild change. WDYT ? Please take a look at crrev/c/6189176 which is meant to address your review comment. marking it resolved and please feel free to open it otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 07:49:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 10: (2 comments) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/e9f6a59a_e688a414?us… : PS10, Line 13: #include <soc/mt6685.h> remove https://review.coreboot.org/c/coreboot/+/85978/comment/2107fac8_f43871b0?us… : PS10, Line 90: config_interface(RG_FQMTR_TCKSEL, FQMTR_DCXO26M_EN | measure_src, : RG_FQMTR_TCKSEL_MASK, RG_FQMTR_TCKSEL_SHIFT); `config_interface(0x546, (1ul << (4)) | measure_src, 0x7, 0);` I expand all the macros. The set value is out of the mask range. Is this expected ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 07:47:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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