coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Nicholas Chin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Riku Viitanen. Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 15: (1 comment) File src/mainboard/asrock/z77_extreme4/Kconfig: https://review.coreboot.org/c/coreboot/+/85772/comment/6d6a4918_6aafcb19?us… : PS15, Line 8: DRIVERS_ASMEDIA_ASPM_BLACKLIST Needs rebase; this was changed to `DRIVERS_ASMEDIA_ASM1061` as of commit fee8bcbcfb55 (drivers/asmedia: Add code to enable AHCI for ASM1061). -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 15 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 04:55:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/nvramtool: Fix spacing issues reported by linter
by Nicholas Chin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: openrc(a)posteo.de. Nicholas Chin has posted comments on this change by openrc(a)posteo.de. ( https://review.coreboot.org/c/coreboot/+/86052?usp=email ) Change subject: util/nvramtool: Fix spacing issues reported by linter ...................................................................... Patch Set 8: (5 comments) File util/nvramtool/cbfs.h: https://review.coreboot.org/c/coreboot/+/86052/comment/4213bfc1_9d2a1318?us… : PS8, Line 129: #define CBFS_SUBHEADER(_p) ((void *) ((((u8 *) (_p)) + ntohl((_p)->offset)))) Arguably the spaces in the original version help with readability due to the multiple levels of nested parenthesis File util/nvramtool/layout.c: https://review.coreboot.org/c/coreboot/+/86052/comment/274ea41c_9d1e8ca1?us… : PS8, Line 91: address = ((unsigned long)p) - offset; I think it would be better if the body of the function was left at a single indent level rather than adding another indent just so that the `(const cmos_entry_t *p)` can be indented. The original formatting isn't that bad and I'd be fine with just leaving it despite checkpatch complaining (though still change `* p` to `*p` for consistency with everything else). If you really want to change it I'd probably either put it on one line (our line length limit is 96: https://doc.coreboot.org/contributing/coding_style.html#breaking-long-lines…): ``` static inline const cmos_entry_item_t *cmos_entry_to_const_item(const cmost_entry_t *p){ ``` or put the function name and arguments on its own line: ``` static inline const cmos_entry_item_t * cmos_entry_to_const_item(const cmost_entry_t *p) { ``` Note that the opening `{` should be on its own line for functions as per the coding style: https://doc.coreboot.org/contributing/coding_style.html#placing-braces-and-… https://review.coreboot.org/c/coreboot/+/86052/comment/c515ca9c_019eab6e?us… : PS8, Line 100: static inline const cmos_enum_item_t *cmos_enum_to_const_item : (const cmos_enum_t *p) { : static const cmos_enum_t *pos = &((cmos_enum_item_t *) 0)->item; : unsigned long offset, address; : : offset = (unsigned long)pos; : address = ((unsigned long)p) - offset; : return (const cmos_enum_item_t *)address; : } Same here, as above. https://review.coreboot.org/c/coreboot/+/86052/comment/4f2e046b_8be6b861?us… : PS8, Line 269: for (item = cmos_enum_list, prev = NULL; : (item != NULL) && (item->item.config_id < e->config_id); : prev = item, item = item->next); This is another one of those loops with no body, where we have been adding a single continue statement so far. You could also consider converting it into a while loop: ``` item = cmos_enum_list; prev = NULL; while ((item != NULL) && (item->item.config_id < e->config_id)) { prev = item; item = item->next; } ``` https://review.coreboot.org/c/coreboot/+/86052/comment/6c9ce1d0_2368bfe7?us… : PS8, Line 508: for (item = cmos_enum_list; : (item != NULL) && (item->item.config_id < config_id); : item = item->next); Same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/86052?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a18a571300c6175ea6c8123e79807afa7a6f084 Gerrit-Change-Number: 86052 Gerrit-PatchSet: 8 Gerrit-Owner: openrc(a)posteo.de Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: openrc(a)posteo.de Gerrit-Comment-Date: Wed, 22 Jan 2025 04:53:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek: Fix register access for EINT
by Yu-Ping Wu (Code Review) 22 Jan '25

22 Jan '25

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86073?usp=email ) Change subject: soc/mediatek: Fix register access for EINT ...................................................................... soc/mediatek: Fix register access for EINT We should be writing to the address of reg[i], instead of the address whose value is reg[i]. Change-Id: I4fb78f974155725a91aad3a5450733d24b57af15 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/eint_event.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/eint_event.c b/src/soc/mediatek/common/eint_event.c index 6e44b37..be13d55 100644 --- a/src/soc/mediatek/common/eint_event.c +++ b/src/soc/mediatek/common/eint_event.c @@ -17,7 +17,7 @@ int i; for (i = 0; i < port; i++) - write32p(reg[i], EINT_VALUE); + write32(&reg[i], EINT_VALUE); } void unmask_eint_event_mask(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/86073?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fb78f974155725a91aad3a5450733d24b57af15 Gerrit-Change-Number: 86073 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Eric Lai (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng. Eric Lai has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 11 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 03:43:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng. Subrata Banik has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 11 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 03:34:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Update LAN settings for EVT
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86072?usp=email ) Change subject: mb/google/rex/var/kanix: Update LAN settings for EVT ...................................................................... mb/google/rex/var/kanix: Update LAN settings for EVT According to the EVT's circuit design changes, update the following LAN settings: 1. set root port to 7 2. set clock source/request to 2 BUG=b:386025819 BRANCH=firmware-rex-15709.B Change-Id: Ia8be74c601a536f1aa932dd6c14ae3f5068d0a7f Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86072 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/kanix/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index a8ca721..4f912d8 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -572,7 +572,7 @@ end end end #PCIE5 WLAN card - device ref pcie_rp6 on + device ref pcie_rp7 on chip drivers/net register "wake" = "GPE0_DW1_04" register "led_feature" = "0xe0" @@ -582,10 +582,10 @@ register "add_acpi_dma_property" = "true" device pci 00.0 on end end - # Enable PCIE 6 using clk 6 - register "pcie_rp[PCH_RP(6)]" = "{ - .clk_src = 6, - .clk_req = 6, + # Enable PCIE 7 using clk 2 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 2, + .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end # RTL8125 Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/86072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8be74c601a536f1aa932dd6c14ae3f5068d0a7f Gerrit-Change-Number: 86072 Gerrit-PatchSet: 4 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in CBFS with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -n option/<option-name> -i <value>`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. This backend is not available in SMM due to CBFS dependencies on vboot functions which are not added to SMM, and thus the fallback will be returned by calls to get_uint_option() in SMM. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85905 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 39 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved Julius Werner: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/Kconfig b/src/Kconfig index 55fad95..320d6db 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -149,6 +149,7 @@ choice prompt "Option backend to use" + default USE_CBFS_FILE_OPTION_BACKEND if CHROMEOS && PLATFORM_USES_FSP2_0 default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \ @@ -164,6 +165,12 @@ Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values. +config USE_CBFS_FILE_OPTION_BACKEND + bool "Use CBFS files for configuration values" + help + Enable this option if coreboot shall read options from files in CBFS. + Options can be set using `cbfstool add-int -n option/<option-name> -i value`. + config USE_UEFI_VARIABLE_STORE bool "Use UEFI variable-store in SPI flash as option backend" depends on DRIVERS_EFI_VARIABLE_STORE diff --git a/src/drivers/option/Makefile.mk b/src/drivers/option/Makefile.mk index 7ca439d..63ac1ba 100644 --- a/src/drivers/option/Makefile.mk +++ b/src/drivers/option/Makefile.mk @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c + +all-$(CONFIG_USE_CBFS_FILE_OPTION_BACKEND) += cbfs_file_option.c diff --git a/src/drivers/option/cbfs_file_option.c b/src/drivers/option/cbfs_file_option.c new file mode 100644 index 0000000..b87bba8 --- /dev/null +++ b/src/drivers/option/cbfs_file_option.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <endian.h> +#include <option.h> + +unsigned int get_uint_option(const char *name, const unsigned int fallback) +{ + size_t size; + uint64_t value; + char full_name[CBFS_METADATA_MAX_SIZE]; + snprintf(full_name, sizeof(full_name), "option/%s", name); + + void *p = cbfs_ro_map(full_name, &size); + if (!p || size < sizeof(value)) { + value = fallback; + } else { + value = le64dec(p); + cbfs_unmap(p); + } + return (unsigned int)value; +} + +enum cb_err set_uint_option(const char *name, unsigned int value) +{ + return CB_ERR_NOT_IMPLEMENTED; +} diff --git a/src/include/option.h b/src/include/option.h index 3a00570..bee761a 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -7,7 +7,9 @@ void sanitize_cmos(void); -#if CONFIG(OPTION_BACKEND_NONE) +/* The CBFS file option backend cannot be used in SMM due to vboot + * dependencies, which are not added to SMM */ +#if CONFIG(OPTION_BACKEND_NONE) || (CONFIG(USE_CBFS_FILE_OPTION_BACKEND) && ENV_SMM) static inline unsigned int get_uint_option(const char *name, const unsigned int fallback) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 17 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 8: (1 comment) File src/drivers/intel/fsp2_0/debug.c: https://review.coreboot.org/c/coreboot/+/86001/comment/971237f6_9ba96726?us… : PS6, Line 185: if (!CONFIG(USE_CBFS_FILE_OPTION_BACKEND)) > Not really sure which comment you're referring to but it's possible I may have missed something. > > I still don't really understand why you need this. As far as I can tell, the previous code in `fsp_control_log_level()` would just always return `fsp_map_console_log_level()`. With the implementation I proposed, an option file could override that behavior, but if the file doesn't exist it will still fall back to `fsp_map_console_log_level()`. So the default behavior doesn't change? > > If your concern is that after this change you want to build ChromeOS images that have the debug FSP built-in but don't enable the debug output by default (unless someone manually overwrote the setting), I think the obvious answer is to just have our ebuild add an option file with value 0 by default? I guess what you are asking is to inject CBFS option file by default with value 0 to ensure that FSP log-level stays disabled unless someone overrides it. Wondering if we really need to do this (what if someone deleted those option files then the log-level will be again chatty)? In my latest patch set, I have used FSP_DYNAMIC_ Kconfig which will ensure that the default log level is 0 and that might eliminate the need for any ebuild change. WDYT ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 03:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add PI_IMG firmware v1.0
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/86095?usp=email ) Change subject: soc/mediatek/mt8196: Add PI_IMG firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add PI_IMG firmware v1.0 Add initial PI_IMG firmware using MTK release branch and align with MCUPM. TEST=Build pass BUG=b:317009620 Change-Id: I4b36c928ad194f155442cf0e4314a826cfd3ef68 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/pi_img.img A soc/mediatek/mt8196/pi_img.img.md5 A soc/mediatek/mt8196/pi_img_release_notes.txt 4 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/95/86095/1 diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index 87c62d9..733ffbc 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -6,6 +6,7 @@ - dram.elf - spm_firmware.bin - gpueb_fw.img +- pi_img.img -------------------------------------------------------------------------------- # MCUPM introduction @@ -216,3 +217,21 @@ `$ strings gpueb_fw.img | grep "gpueb firmware"` -------------------------------------------------------------------------------- +# PI_IMG introduction +The main purpose of the pi_img is to pass various frequency and voltage scaling parameters and +settings to mcupm. + +## Who uses it +Coreboot will load pi_img firmware at ramstage and parse it using mtk_fsp_ramstage. + +## How to load `pi_img` +Use CBFS to load `pi_img.img`. +No need to pass other parameters to pi_img + +## Return values +No return value. + +## Version +`$ strings pi_img.img | grep "pi_img firmware"` + +-------------------------------------------------------------------------------- diff --git a/soc/mediatek/mt8196/pi_img.img b/soc/mediatek/mt8196/pi_img.img new file mode 100644 index 0000000..4ad7ad3 --- /dev/null +++ b/soc/mediatek/mt8196/pi_img.img Binary files differ diff --git a/soc/mediatek/mt8196/pi_img.img.md5 b/soc/mediatek/mt8196/pi_img.img.md5 new file mode 100644 index 0000000..4943795 --- /dev/null +++ b/soc/mediatek/mt8196/pi_img.img.md5 @@ -0,0 +1 @@ +357c892eea80a341201b9493de177362 *pi_img.img diff --git a/soc/mediatek/mt8196/pi_img_release_notes.txt b/soc/mediatek/mt8196/pi_img_release_notes.txt new file mode 100644 index 0000000..50fb8fa --- /dev/null +++ b/soc/mediatek/mt8196/pi_img_release_notes.txt @@ -0,0 +1,5 @@ +** Build from MediaTek Internal ** + +# Version 1.0 +1. Add initial PI_IMG firmware using MTK release branch and align with +MCUPM. -- To view, visit https://review.coreboot.org/c/blobs/+/86095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I4b36c928ad194f155442cf0e4314a826cfd3ef68 Gerrit-Change-Number: 86095 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/common/rtc_osc_init.c: https://review.coreboot.org/c/coreboot/+/85978/comment/b73b0596_7cd32c22?us… : PS8, Line 15: PMIC_RG_FQMTR_CKSEL > `PMIC_RG_FQMTR_CKSEL` is defined as `0x0118` in `include/soc/rtc.h`. […] Please also check the defines used in this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 02:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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