coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: util/crossgcc: Update DESTDIR variable use
by Felix Singer (Code Review) 21 Jan '25

21 Jan '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85718?usp=email ) Change subject: util/crossgcc: Update DESTDIR variable use ...................................................................... util/crossgcc: Update DESTDIR variable use Update DESTDIR variable use to prevent unintended separation and globbing. BUG=None TEST=./util/crossgcc/buildgcc Change-Id: I9eb833b11f20b72db88e4094a3297a1d8891bac2 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85718 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Raul Rangel: Looks good to me, approved build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a751003..2d112eb 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -867,10 +867,10 @@ mkdir -p gcc/$TARGETARCH && \ # shellcheck disable=SC2086 $MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" all-target-libgcc && \ - $MAKE install-target-libgcc DESTDIR=$DESTDIR && \ + $MAKE install-target-libgcc DESTDIR="$DESTDIR" && \ # shellcheck disable=SC2086 $MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" all-target-libstdc++-v3 && \ - $MAKE install-target-libstdc++-v3 DESTDIR=$DESTDIR || touch .failed + $MAKE install-target-libstdc++-v3 DESTDIR="$DESTDIR" || touch .failed } build_GCC() { -- To view, visit https://review.coreboot.org/c/coreboot/+/85718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9eb833b11f20b72db88e4094a3297a1d8891bac2 Gerrit-Change-Number: 85718 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: util/crossgcc: Update DESTDIR variable use
by Felix Singer (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Jon Murphy, Martin L Roth, Paul Menzel. Felix Singer has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/85718?usp=email ) Change subject: util/crossgcc: Update DESTDIR variable use ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9eb833b11f20b72db88e4094a3297a1d8891bac2 Gerrit-Change-Number: 85718 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 20:24:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/crossgcc: Update DESTDIR variable use
by Elyes Haouas (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Felix Singer, Jon Murphy, Martin L Roth, Paul Menzel. Elyes Haouas has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/85718?usp=email ) Change subject: util/crossgcc: Update DESTDIR variable use ...................................................................... Patch Set 4: (1 comment) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/85718/comment/63c566ca_f3179eec?us… : PS2, Line 873: "$DESTDIR" > Sorry, I feel like that wasn't clear. […] Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/85718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9eb833b11f20b72db88e4094a3297a1d8891bac2 Gerrit-Change-Number: 85718 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 19:10:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86002/comment/686fc1bb_d54d8b91?us… : PS7, Line 22: Refer to the Kconfig help text for FSP_DEBUG_LOG_LEVEL_USING_CBFS for > FSP_DYNAMIC_DEBUG Acknowledged, thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 18:42:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86002?usp=email to look at the new patch set (#8). Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... soc/intel/pantherlake: Enable FSP debug log level control using CBFS This commit enables the FSP_DEBUG_LOG_LEVEL_USING_CBFS Kconfig option for Panther Lake ChromeOS devices. This allows controlling the FSP debug log level using CBFS RAW binary files, providing more flexibility in debugging silicon firmware issues with a debug AP FW binary. The following CBFS files are used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. Refer to the Kconfig help text for FSP_DYNAMIC_DEBUG for details on the valid log level values and how to set them using cbfstool. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86002/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Jérémy Compostella (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86002/comment/70112b84_37f86207?us… : PS7, Line 22: Refer to the Kconfig help text for FSP_DEBUG_LOG_LEVEL_USING_CBFS for FSP_DYNAMIC_DEBUG -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 18:30:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Jérémy Compostella (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Julius Werner, Nicholas Chin, Swift Geek (Sebastian Grzywna). Jérémy Compostella has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 16: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 16 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 18:19:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Change the maximum C state to C8
by Jérémy Compostella (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85690?usp=email ) Change subject: soc/intel/meteorlake: Change the maximum C state to C8 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I am a little bit confused because `C_STATE_C7S_LONG_LAT` is also used in S0iX case in acpi.c. Therefore, I decided to look at it on a rex board. I looked at the kernel code: arch/x86/kernel/acpi/cstate.c ``` cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); /* Check whether this particular cx_type (in CST) is supported or not */ cstate_type = (((cx->address >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1) & MWAIT_CSTATE_MASK; edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE); num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK; retval = 0; /* If the HW does not support any sub-states in this C-state */ if (num_cstate_subtype == 0) { pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", cx->address, edx_part); ``` And then did the math based on data collected on the board. ``` cstate_type = ((0x33 >> 4) & 0xf) + 1 = 4 rex-rev2 ~ # iotools cpuid 0 5 0x00000040 0x00000040 0x00000003 0x11112020 edx_part = 0x11112020 >> (4 * 4) = 0x11112020 >> 16 = 0x1111 num_cstate_subtype = 0x1111 & 0xf = 1 ``` So on this Meteor Lake board, `num_cstate_subtype` is 1 and it should not hit the M-wait error. -- To view, visit https://review.coreboot.org/c/coreboot/+/85690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de1220b0e26aa9dcca71e58caf17a0f168e7b24 Gerrit-Change-Number: 85690 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 18:12:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/meteorlake: Move CNVi control out of chipset.cb
by Matt DeVillier (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86088?usp=email ) Change subject: soc/intel/meteorlake: Move CNVi control out of chipset.cb ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb: https://review.coreboot.org/c/coreboot/+/86088/comment/98592559_decad103?us… : PS3, Line 3: option NONE 0 > This should ideally be in a separate CL. I'm guessing the editor auto deleted extraneous whitespace on save -- To view, visit https://review.coreboot.org/c/coreboot/+/86088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1 Gerrit-Change-Number: 86088 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 17:54:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Move CNVi control out of chipset.cb
by Jérémy Compostella (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86088?usp=email ) Change subject: soc/intel/meteorlake: Move CNVi control out of chipset.cb ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb: https://review.coreboot.org/c/coreboot/+/86088/comment/953007b5_12407c9e?us… : PS3, Line 3: option NONE 0 This should ideally be in a separate CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/86088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1 Gerrit-Change-Number: 86088 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 17:50:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit January 2025