coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3270 discussions

[XS] Change in coreboot[main]: mb/google/rauru: Enable RTC
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85979?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/rauru: Enable RTC ...................................................................... mb/google/rauru: Enable RTC Enable RTC so that we can see the correct timestamp and date in ChromeOS. rauru-rev0 ~ # tail /var/log/eventtlog.txt suspend_stress_test -c 5 --suspend_max=30 --suspend_min=30 rauru-rev0 ~ # date Thu Nov 7 14:54:09 CST 2024 TEST=Build pass, check date in ChromeOS BUG=b:355550460 Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/romstage.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/85979/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7 Gerrit-Change-Number: 85979 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd
by Tongtong Pan (Code Review) 22 Jan '25

22 Jan '25

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86098?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd ...................................................................... mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd Modify the overridetree.cb configuration to make the SSD effective. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I5d9219e0964ce1f2c8be6a37f93ead04943421d9 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/felino/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/86098/1 diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 28072d5..d401ed2 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -184,13 +184,13 @@ device ref pcie_rp9 on register "pcie_rp[PCIE_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, + .clk_src = 0, + .clk_req = 0, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "is_storage" = "true" - register "srcclk_pin" = "1" + register "srcclk_pin" = "0" device generic 0 on end end end # Gen5 SSD -- To view, visit https://review.coreboot.org/c/coreboot/+/86098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d9219e0964ce1f2c8be6a37f93ead04943421d9 Gerrit-Change-Number: 86098 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>

1 0

[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Shunxi Zhang, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Shunxi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85978?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Shunxi Zhang, Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... soc/mediatek/mt8196: Add RTC driver Add RTC drivers for MT6685. TEST=build pass. BUG=b:317009620 Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Signed-off-by: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc_osc_init.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/mt6685_hw.h A src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h A src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h A src/soc/mediatek/mt8196/include/soc/rtc.h A src/soc/mediatek/mt8196/mt6685_rtc.c 8 files changed, 2,122 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/85978/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[M] Change in coreboot[main]: mb/dell/haswell_latitude: Add E5440
by Nicholas Chin (Code Review) 22 Jan '25

22 Jan '25

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86097?usp=email ) Change subject: mb/dell/haswell_latitude: Add E5440 ...................................................................... mb/dell/haswell_latitude: Add E5440 Change-Id: I415f8f03a8a7b1cbf8f1eddfd7b508a4eabbf8d7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/haswell_latitude/Kconfig M src/mainboard/dell/haswell_latitude/Kconfig.name A src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt A src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c A src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c A src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb A src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c 7 files changed, 188 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/86097/1 diff --git a/src/mainboard/dell/haswell_latitude/Kconfig b/src/mainboard/dell/haswell_latitude/Kconfig index c01735d..36a4481 100644 --- a/src/mainboard/dell/haswell_latitude/Kconfig +++ b/src/mainboard/dell/haswell_latitude/Kconfig @@ -11,6 +11,13 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP +config BOARD_DELL_LATITUDE_E5440 + select BOARD_DELL_HASWELL_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select INTEL_GMA_HAVE_VBT + select INTEL_LYNXPOINT_LP + select MAINBOARD_USES_IFD_GBE_REGION + config BOARD_DELL_LATITUDE_E7240 select BOARD_DELL_HASWELL_LATITUDE_COMMON select BOARD_ROMSIZE_KB_8192 @@ -23,12 +30,14 @@ default "dell/haswell_latitude" config MAINBOARD_PART_NUMBER + default "Latitude E5440" if BOARD_DELL_LATITUDE_E5440 default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 config DEVICETREE default "devicetree_lp.cb" if INTEL_LYNXPOINT_LP config VARIANT_DIR + default "e5440" if BOARD_DELL_LATITUDE_E5440 default "e7240" if BOARD_DELL_LATITUDE_E7240 config OVERRIDE_DEVICETREE diff --git a/src/mainboard/dell/haswell_latitude/Kconfig.name b/src/mainboard/dell/haswell_latitude/Kconfig.name index 499f783..dbcd427 100644 --- a/src/mainboard/dell/haswell_latitude/Kconfig.name +++ b/src/mainboard/dell/haswell_latitude/Kconfig.name @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_DELL_LATITUDE_E5440 + bool "Latitude E5440" + config BOARD_DELL_LATITUDE_E7240 bool "Latitude E7240" diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt b/src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt new file mode 100644 index 0000000..ebfd3b7 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt Binary files differ diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c b/src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c new file mode 100644 index 0000000..aee5935 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_OUT_LOW, + [5] = LP_GPIO_OUT_LOW, + [6] = LP_GPIO_OUT_LOW, + [7] = LP_GPIO_OUT_LOW, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_HIGH, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = LP_GPIO_OUT_LOW, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_HIGH, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = LP_GPIO_OUT_LOW, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = LP_GPIO_OUT_LOW, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = LP_GPIO_NATIVE, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_LOW, + [85] = LP_GPIO_OUT_LOW, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c b/src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c new file mode 100644 index 0000000..4ae33ac --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805de, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805de), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb b/src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb new file mode 100644 index 0000000..d0c2791 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_d_hotplug" = "0" + + device domain 0 on + subsystemid 0x1028 0x05de inherit + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + end + end +end diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c b/src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c new file mode 100644 index 0000000..a7c462b --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_DOCK }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 1 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/86097?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I415f8f03a8a7b1cbf8f1eddfd7b508a4eabbf8d7 Gerrit-Change-Number: 86097 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[M] Change in coreboot[main]: mb/dell: Convert Latitude E7240 into a variant
by Nicholas Chin (Code Review) 22 Jan '25

22 Jan '25

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86096?usp=email ) Change subject: mb/dell: Convert Latitude E7240 into a variant ...................................................................... mb/dell: Convert Latitude E7240 into a variant In preparation for adding additional Haswell based Dell Latitude laptops, rework the E7240 port to use a variant scheme. Change-Id: I3031910db6d817824320320f137b0f99cdfe1d9a Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- D src/mainboard/dell/e7240/Kconfig D src/mainboard/dell/e7240/Makefile.mk A src/mainboard/dell/haswell_latitude/Kconfig R src/mainboard/dell/haswell_latitude/Kconfig.name A src/mainboard/dell/haswell_latitude/Makefile.mk R src/mainboard/dell/haswell_latitude/acpi/ec.asl R src/mainboard/dell/haswell_latitude/acpi/platform.asl R src/mainboard/dell/haswell_latitude/acpi/superio.asl R src/mainboard/dell/haswell_latitude/board_info.txt R src/mainboard/dell/haswell_latitude/bootblock.c R src/mainboard/dell/haswell_latitude/devicetree_lp.cb R src/mainboard/dell/haswell_latitude/dsdt.asl R src/mainboard/dell/haswell_latitude/gma-mainboard.ads R src/mainboard/dell/haswell_latitude/variants/e7240/gpio.c R src/mainboard/dell/haswell_latitude/variants/e7240/hda_verb.c A src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb R src/mainboard/dell/haswell_latitude/variants/e7240/romstage.c 17 files changed, 57 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/86096/1 diff --git a/src/mainboard/dell/e7240/Kconfig b/src/mainboard/dell/e7240/Kconfig deleted file mode 100644 index 4f24cf9..0000000 --- a/src/mainboard/dell/e7240/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_DELL_LATITUDE_E7240 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_8192 - select EC_DELL_MEC5035 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_LYNXPOINT_LP - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_USES_IFD_GBE_REGION - select NORTHBRIDGE_INTEL_HASWELL - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_LYNXPOINT - select SYSTEM_TYPE_LAPTOP - -config MAINBOARD_DIR - default "dell/e7240" - -config MAINBOARD_PART_NUMBER - default "Latitude E7240" - -config VGA_BIOS_ID - default "8086,0a16" - -config USBDEBUG_HCD_INDEX - default 1 - -endif diff --git a/src/mainboard/dell/e7240/Makefile.mk b/src/mainboard/dell/e7240/Makefile.mk deleted file mode 100644 index c3dd619..0000000 --- a/src/mainboard/dell/e7240/Makefile.mk +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/haswell_latitude/Kconfig b/src/mainboard/dell/haswell_latitude/Kconfig new file mode 100644 index 0000000..c01735d --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/Kconfig @@ -0,0 +1,43 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_HASWELL_LATITUDE_COMMON + def_bool n + select EC_DELL_MEC5035 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config BOARD_DELL_LATITUDE_E7240 + select BOARD_DELL_HASWELL_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_8192 + select INTEL_LYNXPOINT_LP + select MAINBOARD_USES_IFD_GBE_REGION + +if BOARD_DELL_HASWELL_LATITUDE_COMMON + +config MAINBOARD_DIR + default "dell/haswell_latitude" + +config MAINBOARD_PART_NUMBER + default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 + +config DEVICETREE + default "devicetree_lp.cb" if INTEL_LYNXPOINT_LP + +config VARIANT_DIR + default "e7240" if BOARD_DELL_LATITUDE_E7240 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VGA_BIOS_ID + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + default 1 + +endif diff --git a/src/mainboard/dell/e7240/Kconfig.name b/src/mainboard/dell/haswell_latitude/Kconfig.name similarity index 100% rename from src/mainboard/dell/e7240/Kconfig.name rename to src/mainboard/dell/haswell_latitude/Kconfig.name diff --git a/src/mainboard/dell/haswell_latitude/Makefile.mk b/src/mainboard/dell/haswell_latitude/Makefile.mk new file mode 100644 index 0000000..38679ff --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/dell/e7240/acpi/ec.asl b/src/mainboard/dell/haswell_latitude/acpi/ec.asl similarity index 100% rename from src/mainboard/dell/e7240/acpi/ec.asl rename to src/mainboard/dell/haswell_latitude/acpi/ec.asl diff --git a/src/mainboard/dell/e7240/acpi/platform.asl b/src/mainboard/dell/haswell_latitude/acpi/platform.asl similarity index 100% rename from src/mainboard/dell/e7240/acpi/platform.asl rename to src/mainboard/dell/haswell_latitude/acpi/platform.asl diff --git a/src/mainboard/dell/e7240/acpi/superio.asl b/src/mainboard/dell/haswell_latitude/acpi/superio.asl similarity index 100% rename from src/mainboard/dell/e7240/acpi/superio.asl rename to src/mainboard/dell/haswell_latitude/acpi/superio.asl diff --git a/src/mainboard/dell/e7240/board_info.txt b/src/mainboard/dell/haswell_latitude/board_info.txt similarity index 100% rename from src/mainboard/dell/e7240/board_info.txt rename to src/mainboard/dell/haswell_latitude/board_info.txt diff --git a/src/mainboard/dell/e7240/bootblock.c b/src/mainboard/dell/haswell_latitude/bootblock.c similarity index 100% rename from src/mainboard/dell/e7240/bootblock.c rename to src/mainboard/dell/haswell_latitude/bootblock.c diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/haswell_latitude/devicetree_lp.cb similarity index 100% rename from src/mainboard/dell/e7240/devicetree.cb rename to src/mainboard/dell/haswell_latitude/devicetree_lp.cb diff --git a/src/mainboard/dell/e7240/dsdt.asl b/src/mainboard/dell/haswell_latitude/dsdt.asl similarity index 100% rename from src/mainboard/dell/e7240/dsdt.asl rename to src/mainboard/dell/haswell_latitude/dsdt.asl diff --git a/src/mainboard/dell/e7240/gma-mainboard.ads b/src/mainboard/dell/haswell_latitude/gma-mainboard.ads similarity index 100% rename from src/mainboard/dell/e7240/gma-mainboard.ads rename to src/mainboard/dell/haswell_latitude/gma-mainboard.ads diff --git a/src/mainboard/dell/e7240/gpio.c b/src/mainboard/dell/haswell_latitude/variants/e7240/gpio.c similarity index 100% rename from src/mainboard/dell/e7240/gpio.c rename to src/mainboard/dell/haswell_latitude/variants/e7240/gpio.c diff --git a/src/mainboard/dell/e7240/hda_verb.c b/src/mainboard/dell/haswell_latitude/variants/e7240/hda_verb.c similarity index 100% rename from src/mainboard/dell/e7240/hda_verb.c rename to src/mainboard/dell/haswell_latitude/variants/e7240/hda_verb.c diff --git a/src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb b/src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb new file mode 100644 index 0000000..58a8983 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + device domain 0 on + subsystemid 0x1028 0x05ca inherit + end +end diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/haswell_latitude/variants/e7240/romstage.c similarity index 100% rename from src/mainboard/dell/e7240/romstage.c rename to src/mainboard/dell/haswell_latitude/variants/e7240/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/86096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3031910db6d817824320320f137b0f99cdfe1d9a Gerrit-Change-Number: 86096 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: amdfwtool: Set address mode as relative table
by Bao Zheng (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84530?usp=email ) Change subject: amdfwtool: Set address mode as relative table ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84530/comment/8fa5a5ac_4e710f0f?us… : PS8, Line 12: the entry address mode is not set. That is not correct. > Address mode 1, which is relative to BIOS. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 Jan 2025 05:17:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: amdfwtool: Set address mode as relative table
by Bao Zheng (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84530?usp=email to look at the new patch set (#12). Change subject: amdfwtool: Set address mode as relative table ...................................................................... amdfwtool: Set address mode as relative table The address field of each PSP or BIOS entry defines the location of the entry. For the family newer than Cezanne, the upper 2 bits define the address mode. In table header, the address mode of the table is set. They have the same definition. Address Mode 0: Physical Address Address Mode 1: Relative Address to entire BIOS image Address Mode 2: Relative Address to PSP/BIOS directory Address Mode 3: Relative Address to slot N In common case, the address mode of entry should be the same as its table. In spec, it says, "attribute is ignored if the directory address mode is not 2 or 3", In the old code, if the header defines address mode as relative BIOS(1), the entry address mode is not set. That meets the spec. PSP doesn't use, but amdfwtool can use it to record the address mode and transfer it to table. That can reduce the code complexity. Identidal binary test passes on platforms which are not based on Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne. Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84530/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Dinesh Gehlot (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng. Dinesh Gehlot has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 11 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 05:13:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: amdfwtool: Set address mode as relative table
by Bao Zheng (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84530?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set address mode as relative table ...................................................................... amdfwtool: Set address mode as relative table The address field of each PSP or BIOS entry defines the location of the entry. For the family newer than Cezanne, the upper 2 bits define the address mode. In table header, the address mode of the table is set. They have the same definition. Address Mode 0: Physical Address Address Mode 1: Relative Address to entire BIOS image Address Mode 2: Relative Address to PSP/BIOS directory Address Mode 3: Relative Address to slot N In common case, the address mode of entry should be the same as its table. In spec, it says, "attribute is ignored if the directory address mode is not 2 or 3", In the old code, if the header defines address mode as relative BIOS(1), the entry address mode is not set. That meets the spec. PSP doesn't use, but amdfwtool can use it to record the address mode and transfer it to table. That can reduce the code complexity. Identidal binary test passes on platforms which are not based on Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne. Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84530/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Nicholas Chin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß, Máté Kukri. Nicholas Chin has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85767?usp=email ) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... Patch Set 7: (1 comment) File src/mainboard/asus/maximus_vi_gene/Kconfig: https://review.coreboot.org/c/coreboot/+/85767/comment/25f974a0_6419a624?us… : PS7, Line 8: DRIVERS_ASMEDIA_ASPM_BLACKLIST Needs rebase; this was changed to `DRIVERS_ASMEDIA_ASM1061` as of commit fee8bcbcfb55 ("drivers/asmedia: Add code to enable AHCI for ASM1061"). -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 7 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 04:57:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025