coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Hero (Haswell)
by Jan Philipp Groß (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85872?usp=email ) Change subject: mb/asus: Add Maximus VI Hero (Haswell) ...................................................................... Patch Set 5: (1 comment) File src/mainboard/asus/maximus_vi_hero/Kconfig: https://review.coreboot.org/c/coreboot/+/85872/comment/efd86637_3b26ec90?us… : PS4, Line 8: DRIVERS_ASMEDIA_ASPM_BLACKLIST > Needs rebase; this was changed to `DRIVERS_ASMEDIA_ASM1061` as of commit fee8bcbcfb55 ("drivers/asme […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5efa914903170510848668b68d5847f75c9af0eb Gerrit-Change-Number: 85872 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 08:54:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Hero (Haswell)
by Jan Philipp Groß (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß, Máté Kukri. Hello Angel Pons, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85872?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus: Add Maximus VI Hero (Haswell) ...................................................................... mb/asus: Add Maximus VI Hero (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3 DIMM slots - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel USB 3.0 Ports - USB 2.0 Header - USB 3.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0/2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - S3 suspend and resume - Various LED effects (purely cosmetical) Change-Id: I5efa914903170510848668b68d5847f75c9af0eb Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_hero/Kconfig A src/mainboard/asus/maximus_vi_hero/Kconfig.name A src/mainboard/asus/maximus_vi_hero/Makefile.mk A src/mainboard/asus/maximus_vi_hero/acpi/ec.asl A src/mainboard/asus/maximus_vi_hero/acpi/platform.asl A src/mainboard/asus/maximus_vi_hero/acpi/superio.asl A src/mainboard/asus/maximus_vi_hero/board_info.txt A src/mainboard/asus/maximus_vi_hero/bootblock.c A src/mainboard/asus/maximus_vi_hero/data.vbt A src/mainboard/asus/maximus_vi_hero/devicetree.cb A src/mainboard/asus/maximus_vi_hero/dsdt.asl A src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads A src/mainboard/asus/maximus_vi_hero/gpio.c A src/mainboard/asus/maximus_vi_hero/hda_verb.c A src/mainboard/asus/maximus_vi_hero/romstage.c 15 files changed, 561 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85872/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5efa914903170510848668b68d5847f75c9af0eb Gerrit-Change-Number: 85872 Gerrit-PatchSet: 5 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Gene (Haswell)
by Jan Philipp Groß (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß, Máté Kukri. Hello Angel Pons, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85767?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus: Add Maximus VI Gene (Haswell) ...................................................................... mb/asus: Add Maximus VI Gene (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - DIMM_B1 and DIMM_B2 DDR3/DDR3L DIMM slots (DIMM_A1 and DIMM_A2 also not working on vendor firmware, assuming hardware defect) - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel ASMedia USB 3.0 Ports - Both back panel USB 3.0 Ports - USB 3.0 Header - USB 2.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x4 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) - ASUS mPCIe Combo II connector not (yet) tested: - ASUS Extension Board - Optical S/PDIF out not (yet) working: - S3 suspend and resume - Various LEDs (cosmetical) Change-Id: I31029c78cba65cad96718132235c140c3997c815 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_gene/Kconfig A src/mainboard/asus/maximus_vi_gene/Kconfig.name A src/mainboard/asus/maximus_vi_gene/Makefile.mk A src/mainboard/asus/maximus_vi_gene/acpi/ec.asl A src/mainboard/asus/maximus_vi_gene/acpi/platform.asl A src/mainboard/asus/maximus_vi_gene/acpi/superio.asl A src/mainboard/asus/maximus_vi_gene/board_info.txt A src/mainboard/asus/maximus_vi_gene/bootblock.c A src/mainboard/asus/maximus_vi_gene/data.vbt A src/mainboard/asus/maximus_vi_gene/devicetree.cb A src/mainboard/asus/maximus_vi_gene/dsdt.asl A src/mainboard/asus/maximus_vi_gene/gma-mainboard.ads A src/mainboard/asus/maximus_vi_gene/gpio.c A src/mainboard/asus/maximus_vi_gene/hda_verb.c A src/mainboard/asus/maximus_vi_gene/romstage.c 15 files changed, 550 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85767/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31029c78cba65cad96718132235c140c3997c815 Gerrit-Change-Number: 85767 Gerrit-PatchSet: 8 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85690?usp=email to look at the new patch set (#5). Change subject: soc/intel/meteorlake: Change the maximum C state to C8 ...................................................................... soc/intel/meteorlake: Change the maximum C state to C8 The EDS says that Meteor Lake "supports C0, C2, C3, C6, C8, and C10 package states". Update the highest state for non-S0ix boards accordingly. Change-Id: I7de1220b0e26aa9dcca71e58caf17a0f168e7b24 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/meteorlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/85690/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de1220b0e26aa9dcca71e58caf17a0f168e7b24 Gerrit-Change-Number: 85690 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: util/crossgcc: Build compiler-rt using runtimes
by Elyes Haouas (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Arthur Heymans, Martin L Roth. Elyes Haouas has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80737?usp=email ) Change subject: util/crossgcc: Build compiler-rt using runtimes ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/80737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacd9b5f1fc1444b3dd1a785b91510f346e7a2f51 Gerrit-Change-Number: 80737 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 22 Jan 2025 08:33:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: [LLVM test]: Use compiler-rt
by Elyes Haouas (Code Review) 22 Jan '25

22 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86102?usp=email ) Change subject: [LLVM test]: Use compiler-rt ...................................................................... [LLVM test]: Use compiler-rt Change-Id: I7f015bbab530c7595e75279848e09e9edf74d5c5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/xcompile/xcompile 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86102/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3fb0cb7..760080f 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -461,13 +461,7 @@ TABI="linux-gnu" # there is no generic ABI on ppc64 } -# Right now, the clang reference toolchain is not building compiler-rt builtins -# for any of the cross compile architectures. Hence we use libgcc for now, -# because that is available and lets us proceed with getting coreboot clang -# ready. Toggle CLANG_RUNTIME if you want to experiment with compiler-rt. - -CLANG_RUNTIME="libgcc" -# CLANG_RUNTIME="compiler-rt" +CLANG_RUNTIME="compiler-rt" test_architecture() { local architecture=$1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f015bbab530c7595e75279848e09e9edf74d5c5 Gerrit-Change-Number: 86102 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/cmn/cnvi: Fix scope of CFLR ACPI method
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86092?usp=email ) Change subject: soc/intel/cmn/cnvi: Fix scope of CFLR ACPI method ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7065e24626b2f763868909b8f85a8f18b4cc229b Gerrit-Change-Number: 86092 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 08:22:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cmn/cnvi: Drop CNIP ACPI method
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86091?usp=email ) Change subject: soc/intel/cmn/cnvi: Drop CNIP ACPI method ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib60c48852923e965620f4eee6a886c8c0f5c1783 Gerrit-Change-Number: 86091 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 08:21:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/starlabs/merlin/acpi: Move Q Events under EC device
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86087?usp=email ) Change subject: ec/starlabs/merlin/acpi: Move Q Events under EC device ...................................................................... ec/starlabs/merlin/acpi: Move Q Events under EC device For the Q events to be used, they need to sit under the EC device in ACPI. Move them accordingly. Change-Id: I58a41ae660ec466a08d4c290ff820b713b866f4f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86087 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/hid.asl 1 file changed, 9 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/hid.asl b/src/ec/starlabs/merlin/acpi/hid.asl index 4a85f04..f3bfff6 100644 --- a/src/ec/starlabs/merlin/acpi/hid.asl +++ b/src/ec/starlabs/merlin/acpi/hid.asl @@ -1,14 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #if CONFIG(EC_STARLABS_MERLIN) -Method (_Q05, 0, NotSerialized) // Event: Backlight Brightness Down +Scope (\_SB.PCI0.LPCB.EC) { - ^HIDD.HPEM (20) -} + Method (_Q05, 0, NotSerialized) // Event: Backlight Brightness Down + { + ^^^^HIDD.HPEM (20) + } -Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Up -{ - ^HIDD.HPEM (19) + Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Up + { + ^^^^HIDD.HPEM (19) + } } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58a41ae660ec466a08d4c290ff820b713b866f4f Gerrit-Change-Number: 86087 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Remove switch property from back USB port
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86086?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl_n: Remove switch property from back USB port ...................................................................... mb/starlabs/starbook/adl_n: Remove switch property from back USB port The back USB port is a data-only port without switching, so update the ACPI configuration accordingly. Change-Id: Ic6b77f44a2d2607d201a2b097cea41aa361ebbee Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86086 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb index cf52628..2bfe475 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -72,13 +72,13 @@ device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Back USB Type-C"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "type" = "UPC_TYPE_C_USB2_SS" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""Back USB Type-C"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "type" = "UPC_TYPE_C_USB2_SS" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb3_port3 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6b77f44a2d2607d201a2b097cea41aa361ebbee Gerrit-Change-Number: 86086 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit January 2025