coreboot-gerrit January 2025

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Maximilian Brune (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Ana Carolina Cabral, Maximilian Brune. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84500?usp=email ) Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Wed, 22 Jan 2025 12:55:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the region size for mcufw_reserved
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86108?usp=email ) Change subject: soc/mediatek/mt8196: Correct the region size for mcufw_reserved ...................................................................... soc/mediatek/mt8196: Correct the region size for mcufw_reserved Adjust the allocated region size for mcufw_reserved from 52K to 68K. TEST=Build pass. BUG=b:390334489 Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 --- M src/soc/mediatek/mt8196/include/soc/memlayout.ld 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/86108/1 diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 74f1543..158ddb8 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -26,16 +26,16 @@ * MCUPM exchanges data with kernel driver using SRAM 0x00113000 ~ * 0x0011ffff. The address is hardcoded in MCUPM image. */ - REGION(mcufw_reserved, 0x00113000, 52K, 4K) + REGION(mcufw_reserved, 0x00113000, 68K, 4K) /* End of regions that need to stay in SRAM. */ /* Regions can be moved to SRAM_L2C. */ - CBFS_MCACHE(0x00120000, 16k) - VBOOT2_WORK(0x00124000, 12K) - FMAP_CACHE(0x00127000, 2k) - TPM_LOG(0x00127800, 2k) - TIMESTAMP(0x00128000, 1k) + CBFS_MCACHE(0x00124000, 16k) + VBOOT2_WORK(0x00128000, 12K) + FMAP_CACHE(0x0012B000, 2k) + TPM_LOG(0x0012B800, 2k) + TIMESTAMP(0x0012C000, 1k) /* End of regions that can also be moved to SRAM_L2C. */ - /* EMPTY(0x00128400, 95K) */ + /* EMPTY(0x0012C400, 79K) */ SRAM_END(0x00140000) /* -- To view, visit https://review.coreboot.org/c/coreboot/+/86108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 Gerrit-Change-Number: 86108 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/amd/common/spi: Create header for SPI defines
by Maximilian Brune (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Maximilian Brune has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84917?usp=email ) Change subject: soc/amd/common/spi: Create header for SPI defines ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24de8c05a65c915bd4979d91bd1c2bfa6864b752 Gerrit-Change-Number: 84917 Gerrit-PatchSet: 4 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 Jan 2025 12:39:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/corsola: Increase ANX7625 data trail time
by Paul Menzel (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Xin Ji, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Xin Ji. ( https://review.coreboot.org/c/coreboot/+/86101?usp=email ) Change subject: mb/google/corsola: Increase ANX7625 data trail time ...................................................................... Patch Set 3: Code-Review+1 (5 comments) Patchset: PS3: Thank you for the improved commit message. Some more minor comments. Commit Message: https://review.coreboot.org/c/coreboot/+/86101/comment/51860789_11eeb051?us… : PS3, Line 10: caused is caused https://review.coreboot.org/c/coreboot/+/86101/comment/5b93471e_3fab105f?us… : PS3, Line 10: shorter too short https://review.coreboot.org/c/coreboot/+/86101/comment/de76c916_c45bfdb4?us… : PS3, Line 13: enter entering https://review.coreboot.org/c/coreboot/+/86101/comment/d6c485a0_dadc2c1c?us… : PS3, Line 15: So why is +9 correct, and not +11 or +8? -- To view, visit https://review.coreboot.org/c/coreboot/+/86101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Gerrit-Change-Number: 86101 Gerrit-PatchSet: 3 Gerrit-Owner: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 12:25:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Riku Viitanen. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85772?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... mb/asrock: Add Z77 Extreme4 New port based on logs extracted from a board running OEM firmware. VBT extracted from a running system with "intelvbttool --inlegacy". Internal flashing of the entire chip is possible from vendor firmware by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is connected to one of the unused pins of the PCIE1 slot. Tested: - i7-3770K CPU (native raminit) - 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz) - 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz) - libgfxinit txtmode with onboard HDMI, DVI and VGA - Gigabit Ethernet - CPU fan - PS/2 keyboard or mouse (but not at the same time) - SeaBIOS 1.16.3 booting to Devuan and Void Linux - All internal SATA ports - Rear USB ports - Line out - me_cleaner - PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots - PCI slots - Suspend and resume (S3) - Serial port header COM1 (including coreboot output) Untested: - Intel VBIOS - USB headers - Other fans - LED headers - eSATA, Toslink - PCIE1 (x1) slot Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asrock/z77_extreme4/Kconfig A src/mainboard/asrock/z77_extreme4/Kconfig.name A src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/acpi/ec.asl A src/mainboard/asrock/z77_extreme4/acpi/platform.asl A src/mainboard/asrock/z77_extreme4/acpi/superio.asl A src/mainboard/asrock/z77_extreme4/board_info.txt A src/mainboard/asrock/z77_extreme4/cmos.default A src/mainboard/asrock/z77_extreme4/cmos.layout A src/mainboard/asrock/z77_extreme4/data.vbt A src/mainboard/asrock/z77_extreme4/devicetree.cb A src/mainboard/asrock/z77_extreme4/dsdt.asl A src/mainboard/asrock/z77_extreme4/early_init.c A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads A src/mainboard/asrock/z77_extreme4/gpio.c A src/mainboard/asrock/z77_extreme4/hda_verb.c A src/mainboard/asrock/z77_extreme4/mainboard.c 17 files changed, 619 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 16 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/asrock/z77_extreme4: Implement voltage settings
by Riku Viitanen (Code Review) 22 Jan '25

22 Jan '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85795?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock/z77_extreme4: Implement voltage settings ...................................................................... mb/asrock/z77_extreme4: Implement voltage settings This board has two Nuvoton NCT3933U current DAC chips on SMBus, enabling firmware to adjust several voltage rails. The correct registers and constants were reverse engineered by adjusting voltages in vendor firmware and observing what it wrote. DRAM, PCH, VTT, and CPU PLL voltages are fully documented in devicetree. Of VREFDQ and VREFCA, only register addresses are known based on the boardview. DRAM voltage is automatically adjustable by raminit. TEST=With few XMP and non-XMP modules. Monitored DRAM voltage on test point VT10 (located near the SLI logo) with a multimeter. DIMMs tested (matching and also in weird groupings): - Corsair CMY16GX3M2A2400C - G.Skill F3-1600C9-8GAR - Hynix HMT41GU7BFR8C-RD - Kingston 9905403-440.A00L - Kingston KHX1600C10D3/8G - Micron 4JTF12864AZ-1G4D - Samsung M378B5173DB0-CK0 Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asrock/z77_extreme4/Kconfig M src/mainboard/asrock/z77_extreme4/devicetree.cb 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85795/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Gerrit-Change-Number: 85795 Gerrit-PatchSet: 6 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/amd/crater: Add A/B flashmap
by Bao Zheng (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86107?usp=email to review the following change. Change subject: mb/amd/crater: Add A/B flashmap ...................................................................... mb/amd/crater: Add A/B flashmap Change-Id: I4dd3396664590331b832f39dd47a3455c1cfb1ac Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/crater/Kconfig A src/mainboard/amd/crater/board_renoir_ab.fmd 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/86107/1 diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig index 61b8f3e..7e328cd 100644 --- a/src/mainboard/amd/crater/Kconfig +++ b/src/mainboard/amd/crater/Kconfig @@ -26,6 +26,7 @@ config FMDFILE default "src/mainboard/amd/crater/chromeos_renoir.fmd" if CHROMEOS + default "src/mainboard/amd/crater/board_renoir_ab.fmd" if PSP_AB_RECOVERY default "src/mainboard/amd/crater/board_renoir.fmd" config MAINBOARD_DIR diff --git a/src/mainboard/amd/crater/board_renoir_ab.fmd b/src/mainboard/amd/crater/board_renoir_ab.fmd new file mode 100644 index 0000000..234f135 --- /dev/null +++ b/src/mainboard/amd/crater/board_renoir_ab.fmd @@ -0,0 +1,17 @@ +FLASH@0xFF000000 16M { + BIOS { + EC_SIG 4K + FMAP 4K + EFS @128K 4M + PSP_NVRAM(PRESERVE) 128K + PSP_RPMC_NVRAM(PRESERVE) 256K + PARTITIION @6M { + COREBOOT(CBFS) + } + BCOPY @12M { + COREBOOTB(CBFS) + } + EC_BODY@15872K 256K + RW_MRC_CACHE 64K + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dd3396664590331b832f39dd47a3455c1cfb1ac Gerrit-Change-Number: 86107 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

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[M] Change in coreboot[main]: soc/amd: Add A/B recovery support to AMD SOC
by Bao Zheng (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85647?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd: Add A/B recovery support to AMD SOC ...................................................................... soc/amd: Add A/B recovery support to AMD SOC Copy the settings from Cezanne to glinda & phoenix. 1. Add A/B data address to command line. 2. Enable CBFS verificatin if A/B recovery is enabled. 3. Do not compress the bootblock binary. Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.mk M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.mk 4 files changed, 48 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85647/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Gerrit-Change-Number: 85647 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: [UNTESTED] soc/amd/common/psp: add support for early PSP v2 access vi...
by Bao Zheng (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Felix Held. Hello Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86106?usp=email to review the following change. Change subject: [UNTESTED] soc/amd/common/psp: add support for early PSP v2 access via SMN ...................................................................... [UNTESTED] soc/amd/common/psp: add support for early PSP v2 access via SMN copy of https://review.coreboot.org/c/coreboot/+/85242 The MMIO mapping of the PSP mailbox registers can only be accessed once the FSP or in the future openSIL have initialized the PSP MMIO region. Before that, the PSP mailbox registers can only be accessed via their SMN mapping. When using the AMD A/B recovery scheme, which is not to be confused with the VBOOT RO/A/B recovery scheme, we need to detect in bootblock if we're running the A or the B part of the image to then load the correct romstage. To retrieve this info from the PSP, we'll need to use the SMN mapping, since the MMIO mapping hasn't been set up at that point in the boot process. Once the PSP MMIO is set up, we should however still use that one. In order to accomplish this, factor out the actual PSP register access and have separate register access functions that either use SMN or MMIO to access the registers. To add the functions for the early access via SMN in bootblock and romstage to the build, the SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS Kconfig option is introduced. Since the base address of the SMN and the MMIO access is different, an access method specific 'get_psp_mmio_base' is implemented; the register offsets from those SMN and MMIO bases is identical. TEST=TODO Change-Id: I863cc94e882b4558dcdbb18d8d7ad42e3580c878 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.mk M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c A src/soc/amd/common/block/psp/psp_gen2_mmio.c A src/soc/amd/common/block/psp/psp_gen2_smn.c 7 files changed, 177 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/86106/1 diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 17853fa..018e87a 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -20,6 +20,14 @@ help Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. +config SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + bool + depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_SMN + help + Allow PSP mailbox access in bootblock and romstage using the SMN + access method to the mailbox registers. + config SOC_AMD_PSP_SELECTABLE_SMU_FW bool help diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index dc811f90..91d9766 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) -romstage-y += psp.c ramstage-y += psp.c smm-y += psp.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi.c @@ -15,6 +14,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) +romstage-y += psp.c romstage-y += psp_gen1.c ramstage-y += psp_gen1.c @@ -25,12 +25,22 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS),y) +bootblock-y += psp.c +bootblock-y += psp_gen2.c +bootblock-y += psp_gen2_smn.c +romstage-y += psp.c romstage-y += psp_gen2.c +romstage-y += psp_gen2_smn.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + ramstage-y += psp_gen2.c +ramstage-y += psp_gen2_mmio.c ramstage-$(CONFIG_PSP_PLATFORM_SECURE_BOOT) += psb.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c smm-y += psp_gen2.c +smm-y += psp_gen2_mmio.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi_flash_gen2.c smm-y += psp_smm_gen2.c diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c index 5e497a2..71b766b 100644 --- a/src/soc/amd/common/block/psp/psb.c +++ b/src/soc/amd/common/block/psp/psb.c @@ -84,13 +84,13 @@ static enum cb_err get_psb_status(uint32_t *psb_status_value) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = get_psp_base(); - if (!psp_mmio) { + if (!base) { printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); return CB_ERR; } - *psb_status_value = read32p(psp_mmio | PSB_STATUS_OFFSET); + *psb_status_value = psp_read32(base, PSB_STATUS_OFFSET); return CB_SUCCESS; } diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 369ef08..ff58dab 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -146,7 +146,11 @@ MBOX_PSP_SPI_BUSY = 0x0b, }; -uintptr_t get_psp_mmio_base(void); +/* TODO */ +uint64_t psp_get_base(void); +uint32_t psp_read32(uint64_t base, uint32_t offset); +void psp_write32(uint64_t base, uint32_t offset, uint32_t data); +void psp_write64(uint64_t base, uint32_t offset, uint64_t data); void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 026d32f..04e7ba1 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -1,86 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/psp.h> +#include <console/console.h> +#include <device/mmio.h> #include <timer.h> #include <types.h> -#include <amdblocks/psp.h> -#include <amdblocks/root_complex.h> -#include <amdblocks/smn.h> -#include <device/mmio.h> #include "psp_def.h" #define PSP_MAILBOX_COMMAND_OFFSET CONFIG_PSPV2_MBOX_CMD_OFFSET /* 4 bytes */ #define PSP_MAILBOX_BUFFER_OFFSET (CONFIG_PSPV2_MBOX_CMD_OFFSET + 4) /* 8 bytes */ -#define IOHC_MISC_PSP_MMIO_REG 0x2e0 - -static uint64_t get_psp_mmio_mask(void) -{ - const struct non_pci_mmio_reg *mmio_regs; - size_t reg_count; - mmio_regs = get_iohc_non_pci_mmio_regs(&reg_count); - - for (size_t i = 0; i < reg_count; i++) { - if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) - return mmio_regs[i].mask; - } - - printk(BIOS_ERR, "No PSP MMIO register description found.\n"); - return 0; -} - -#define PSP_MMIO_LOCK BIT(8) - -/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, - so we have to read this from the hardware registers */ -uintptr_t get_psp_mmio_base(void) -{ - static uintptr_t psp_mmio_base; - const struct domain_iohc_info *iohc; - size_t iohc_count; - - if (psp_mmio_base) - return psp_mmio_base; - - iohc = get_iohc_info(&iohc_count); - const uint64_t psp_mmio_mask = get_psp_mmio_mask(); - - if (!psp_mmio_mask) - return 0; - - for (size_t i = 0; i < iohc_count; i++) { - uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); - - if (!(reg64 & IOHC_MMIO_EN)) - continue; - - const uint64_t base = reg64 & psp_mmio_mask; - - if (ENV_X86_32 && base >= 4ull * GiB) { - printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); - continue; - } - - /* If the PSP MMIO base is enabled but the register isn't locked, set the lock - bit. This shouldn't happen, but better be a bit too careful here */ - if (!(reg64 & PSP_MMIO_LOCK)) { - printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " - "Locking it.\n", i); - reg64 |= PSP_MMIO_LOCK; - /* Since the lock bit lives in the lower one of the two 32 bit SMN - registers, we only need to write that one to lock it */ - smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, - reg64 & 0xffffffff); - } - - psp_mmio_base = base; - } - - if (!psp_mmio_base) - printk(BIOS_ERR, "No usable PSP MMIO found.\n"); - - return psp_mmio_base; -} - union pspv2_mbox_command { uint32_t val; struct pspv2_mbox_cmd_fields { @@ -92,37 +21,37 @@ } __packed fields; }; -static uint16_t rd_mbox_sts(uintptr_t psp_mmio) +static uint16_t rd_mbox_sts(uint64_t base) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, uint8_t cmd) +static void wr_mbox_cmd(uint64_t base, uint8_t cmd) { union pspv2_mbox_command tmp = { .val = 0 }; /* Write entire 32-bit area to begin command execution */ tmp.fields.mbox_command = cmd; - write32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET, tmp.val); + psp_write32(base, PSP_MAILBOX_COMMAND_OFFSET, tmp.val); } -static uint8_t rd_mbox_recovery(uintptr_t psp_mmio) +static uint8_t rd_mbox_recovery(uint64_t base) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); return !!tmp.fields.recovery; } -static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer) +static void wr_mbox_buffer_ptr(uint64_t base, void *buffer) { - write64p(psp_mmio | PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); + psp_write64(base, PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); } -static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) +static int wait_command(uint64_t base, bool wait_for_ready) { union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; @@ -140,7 +69,7 @@ stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); do { - tmp = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); tmp &= ~and_mask.val; if (tmp == expected.val) return 0; @@ -151,27 +80,27 @@ int send_psp_command(uint32_t command, void *buffer) { - const uintptr_t psp_mmio = get_psp_mmio_base(); - if (!psp_mmio) + const uint64_t base = psp_get_base(); + if (!base) return -PSPSTS_NOBASE; - if (rd_mbox_recovery(psp_mmio)) + if (rd_mbox_recovery(base)) return -PSPSTS_RECOVERY; - if (wait_command(psp_mmio, true)) + if (wait_command(base, true)) return -PSPSTS_CMD_TIMEOUT; /* set address of command-response buffer and write command register */ - wr_mbox_buffer_ptr(psp_mmio, buffer); - wr_mbox_cmd(psp_mmio, command); + wr_mbox_buffer_ptr(base, buffer); + wr_mbox_cmd(base, command); /* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ - if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) + if (wait_command(base, command != MBOX_BIOS_CMD_SX_INFO)) return -PSPSTS_CMD_TIMEOUT; /* check delivery status */ - if (rd_mbox_sts(psp_mmio)) + if (rd_mbox_sts(base)) return -PSPSTS_SEND_ERROR; return 0; @@ -202,12 +131,12 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = psp_get_base(); - if (!psp_mmio) { + if (!base) { printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); return CB_ERR; } - *msg_38_value = read32p(psp_mmio | CORE_2_PSP_MSG_38_OFFSET); + *msg_38_value = psp_read32(base, CORE_2_PSP_MSG_38_OFFSET); return CB_SUCCESS; } diff --git a/src/soc/amd/common/block/psp/psp_gen2_mmio.c b/src/soc/amd/common/block/psp/psp_gen2_mmio.c new file mode 100644 index 0000000..14f0327 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2_mmio.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/psp.h> +#include <amdblocks/root_complex.h> +#include <amdblocks/smn.h> +#include <console/console.h> +#include <device/mmio.h> +#include <types.h> +#include "psp_def.h" + +#define IOHC_MISC_PSP_MMIO_REG 0x2e0 + +static uint64_t get_psp_mmio_mask(void) +{ + const struct non_pci_mmio_reg *mmio_regs; + size_t reg_count; + mmio_regs = get_iohc_non_pci_mmio_regs(&reg_count); + + for (size_t i = 0; i < reg_count; i++) { + if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) + return mmio_regs[i].mask; + } + + printk(BIOS_ERR, "No PSP MMIO register description found.\n"); + return 0; +} + +#define PSP_MMIO_LOCK BIT(8) + +/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, + so we have to read this from the hardware registers */ +static uintptr_t get_psp_mmio_base(void) +{ + static uintptr_t psp_mmio_base; + const struct domain_iohc_info *iohc; + size_t iohc_count; + + if (psp_mmio_base) + return psp_mmio_base; + + iohc = get_iohc_info(&iohc_count); + const uint64_t psp_mmio_mask = get_psp_mmio_mask(); + + if (!psp_mmio_mask) + return 0; + + for (size_t i = 0; i < iohc_count; i++) { + uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); + + if (!(reg64 & IOHC_MMIO_EN)) + continue; + + const uint64_t base = reg64 & psp_mmio_mask; + + if (ENV_X86_32 && base >= 4ull * GiB) { + printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); + continue; + } + + /* If the PSP MMIO base is enabled but the register isn't locked, set the lock + bit. This shouldn't happen, but better be a bit too careful here */ + if (!(reg64 & PSP_MMIO_LOCK)) { + printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " + "Locking it.\n", i); + reg64 |= PSP_MMIO_LOCK; + /* Since the lock bit lives in the lower one of the two 32 bit SMN + registers, we only need to write that one to lock it */ + smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, + reg64 & 0xffffffff); + } + + psp_mmio_base = base; + } + + if (!psp_mmio_base) + printk(BIOS_ERR, "No usable PSP MMIO found.\n"); + + return psp_mmio_base; +} + +uint64_t psp_get_base(void) +{ + return get_psp_mmio_base(); +} + +uint32_t psp_read32(uint64_t base, uint32_t offset) +{ + return read32p((uintptr_t)(base | offset)); +} + +void psp_write32(uint64_t base, uint32_t offset, uint32_t data) +{ + write32p((uintptr_t)(base | offset), data); +} + +void psp_write64(uint64_t base, uint32_t offset, uint64_t data) +{ + write64p((uintptr_t)(base | offset), data); +} diff --git a/src/soc/amd/common/block/psp/psp_gen2_smn.c b/src/soc/amd/common/block/psp/psp_gen2_smn.c new file mode 100644 index 0000000..45b7487 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2_smn.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/psp.h> +#include <amdblocks/smn.h> +#include <types.h> +#include "psp_def.h" + +uint64_t psp_get_base(void) +{ + return SMN_PSP_PUBLIC_BASE; +} + +uint32_t psp_read32(uint64_t base, uint32_t offset) +{ + return smn_read32(base | offset); +} + +void psp_write32(uint64_t base, uint32_t offset, uint32_t data) +{ + smn_write32(base | offset, data); +} + +void psp_write64(uint64_t base, uint32_t offset, uint64_t data) +{ + smn_write32(base | (offset + sizeof(uint32_t)), data >> 32); + smn_write32(base | offset, data & 0xffffffff); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I863cc94e882b4558dcdbb18d8d7ad42e3580c878 Gerrit-Change-Number: 86106 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add platform debug option for FSP
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86104?usp=email to look at the new patch set (#2). Change subject: soc/intel/pantherlake: Add platform debug option for FSP ...................................................................... soc/intel/pantherlake: Add platform debug option for FSP Previously, DCI was enabled unconditionally, which could interfere with the USB data path when connected behind a powered hub and/or servo v4.1 debug connector. This patch sets DciEn parameter based on the selected platform debug option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is set to 0. BUG=b:384453901 TEST=Able to boot google/fatcat. Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86104/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Gerrit-Change-Number: 86104 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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