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Change subject: mb/asus/p8x7x-series: Streamline DT PCIe configs
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/asus/p8x7x-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85797/comment/cdf9f2ec_1cb6fcf2?us… :
PS1, Line 40: device ref pcie_rp1 on end # PCIe x4 slot, by various names
> If they are still present in the overridetrees so that the comment about the name is still present, […]
My original plan would be to rid those comments from all the
overridetrees, but I'm torn whether to go ahead with that, so I'm
dropping this line here for now.
https://review.coreboot.org/c/coreboot/+/85797/comment/d0e48e5b_3402bff6?us… :
PS1, Line 41: device ref pcie_rp2 off end
: device ref pcie_rp3 off end
: device ref pcie_rp4 off end
: device ref pcie_rp5 off end
: device ref pcie_rp6 off end
: device ref pcie_rp7 off end
: device ref pcie_rp8 off end
> All of these default to off in the chipset devicetree (`nb/intel/sandybridge/chipset. […]
Done
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Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85821?usp=email )
Change subject: mb/asus/p8x7x-series: Drop unused MRC devicetree setting
......................................................................
mb/asus/p8x7x-series: Drop unused MRC devicetree setting
Drop MRC setting usb3.hs_port_switch_mask that since commit ee126348726b
(nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree)
mirrors xhci_switchable_ports and is no longer used separately.
Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/devicetree.cb
1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/85821/1
diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb
index 979f124..e4e8d84 100644
--- a/src/mainboard/asus/p8x7x-series/devicetree.cb
+++ b/src/mainboard/asus/p8x7x-series/devicetree.cb
@@ -7,13 +7,6 @@
register "max_mem_clock_mhz" = "800"
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
- # 4 bit switch mask. 0=not switchable, 1=switchable
- # Means once it's loaded the OS, it can swap ports
- # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
- register "usb3.hs_port_switch_mask" = "0xf"
- # (The other 3 usb3.* settings can be set from nvram options, and so are set
- # from runtime code)
-
device domain 0 on
device ref peg10 on end # PCIEX16_1
device ref igd on end
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Attention is currently required from: Keith Hui, Nicholas Chin.
Hello Nicholas Chin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85797?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Nicholas Chin, Verified+1 by build bot (Jenkins)
Change subject: mb/asus/p8x7x-series: Streamline DT PCIe configs
......................................................................
mb/asus/p8x7x-series: Streamline DT PCIe configs
Drop PCI(e) devices from devicetree that remain off or unchanged from
chipset defaults.
TEST=Timeless binaries did not change across entire family.
Change-Id: I4feb88a78f72952bed049505073aed00d2120df3
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/devicetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
5 files changed, 0 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85797/2
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Elyes Haouas has uploaded a new patch set (#9) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85169?usp=email )
Change subject: util/crossgcc: Update LLVM from 18.1.8 to 19.1.6
......................................................................
util/crossgcc: Update LLVM from 18.1.8 to 19.1.6
Change-Id: I4a392b472b7450685343e1343c7b84c78b0cad3d
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/clang-19.1.6.src_x86_baremetal.patch
D util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/clang-19.1.6.src.tar.xz.cksum
D util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/clang-tools-extra-19.1.6.src.tar.xz.cksum
D util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/cmake-19.1.6.src.tar.xz.cksum
D util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/compiler-rt-19.1.6.src.tar.xz.cksum
D util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/libunwind-19.1.6.src.tar.xz.cksum
D util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/lld-19.1.6.src.tar.xz.cksum
D util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum
A util/crossgcc/sum/llvm-19.1.6.src.tar.xz.cksum
16 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/85169/9
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Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email )
Change subject: mb/asrock: Add Z77 Extreme4
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/asrock/z77_extreme4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/85772/comment/5abc94a9_d3c10930?us… :
PS10, Line 5: #include <southbridge/intel/bd82x6x/pch.h>
> Still seems to be there?
oops, forgot to git add that one
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/asrock: Add Z77 Extreme4
......................................................................
mb/asrock: Add Z77 Extreme4
New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".
Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.16.3 booting to Devuan and Void Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIe x16 slots, including automatic bifurcation (x8/x8)
- PCI slots
- Suspend and resume (S3)
- Serial port header COM1 (including coreboot output)
Untested:
- Intel VBIOS
- USB headers
- Other fans
- LED headers
- eSATA, SPDIF
- PCIe x1 slots
Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com>
---
A src/mainboard/asrock/z77_extreme4/Kconfig
A src/mainboard/asrock/z77_extreme4/Kconfig.name
A src/mainboard/asrock/z77_extreme4/Makefile.mk
A src/mainboard/asrock/z77_extreme4/acpi/ec.asl
A src/mainboard/asrock/z77_extreme4/acpi/platform.asl
A src/mainboard/asrock/z77_extreme4/acpi/superio.asl
A src/mainboard/asrock/z77_extreme4/board_info.txt
A src/mainboard/asrock/z77_extreme4/cmos.default
A src/mainboard/asrock/z77_extreme4/cmos.layout
A src/mainboard/asrock/z77_extreme4/data.vbt
A src/mainboard/asrock/z77_extreme4/devicetree.cb
A src/mainboard/asrock/z77_extreme4/dsdt.asl
A src/mainboard/asrock/z77_extreme4/early_init.c
A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads
A src/mainboard/asrock/z77_extreme4/gpio.c
A src/mainboard/asrock/z77_extreme4/hda_verb.c
A src/mainboard/asrock/z77_extreme4/mainboard.c
17 files changed, 621 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/12
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