coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: soc/intel/mtl: Enable all bits for IO decode register
by Sean Rhodes (Code Review) 01 Jan '25

01 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85707?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/mtl: Enable all bits for IO decode register ...................................................................... soc/intel/mtl: Enable all bits for IO decode register Based on discussions on various patches (CB:57140), the idea was to enable all bits to avoid incomplete ports. Therefore, enable all bits - the same as ADL. Change-Id: I5ace878faa09b959384338efcdbdfce390145002 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85707 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/bootblock/soc_die.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, but someone else must approve diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c index cfbc22c..71fc464 100644 --- a/src/soc/intel/meteorlake/bootblock/soc_die.c +++ b/src/soc/intel/meteorlake/bootblock/soc_die.c @@ -55,8 +55,10 @@ static void soc_die_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_LPT_EN | LPC_IOE_FDD_EN | + LPC_IOE_LGE_200 | LPC_IOE_HGE_208 | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | + LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ace878faa09b959384338efcdbdfce390145002 Gerrit-Change-Number: 85707 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/intel/usb4: Guard usage of RFMU with a null check
by Sean Rhodes (Code Review) 01 Jan '25

01 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84615?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/usb4: Guard usage of RFMU with a null check ...................................................................... drivers/intel/usb4: Guard usage of RFMU with a null check Add a null check around the usage of the RFWU (Retimer Firmware Update path) in the `usb4_retimer_execute_ec_cmd` function. This ensures that any interaction with RFWU is only performed when the path is valid, preventing potential null pointer dereferences. This fixes are large amount of errors when `ec_retimer_fw_update_path` isn't declared, such as comparisons like `If ((Local0 == Break))`. Change-Id: I5a219345440f91332f680885b51e2cc09f14f7a7 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84615 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: coreboot org <coreboot.org(a)gmail.com> --- M src/drivers/intel/usb4/retimer/retimer.c 1 file changed, 39 insertions(+), 34 deletions(-) Approvals: coreboot org: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 3769fc9..40dd4c1 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -36,10 +36,12 @@ /* Invoke EC Retimer firmware update command execution */ ec_retimer_fw_update(data); /* If RFWU has return value 0xfe, return error -1 */ - acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_ERROR); - acpigen_disable_tx_gpio(power_gpio); - acpigen_write_return_integer(-1); - acpigen_pop_len(); /* If */ + if (RFWU) { + acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_ERROR); + acpigen_disable_tx_gpio(power_gpio); + acpigen_write_return_integer(-1); + acpigen_pop_len(); /* If */ + } acpigen_write_store_int_to_op(USB4_RETIMER_ITERATION_NUM, LOCAL2_OP); acpigen_emit_byte(WHILE_OP); @@ -47,39 +49,42 @@ acpigen_emit_byte(LGREATER_OP); acpigen_emit_byte(LOCAL2_OP); acpigen_emit_byte(ZERO_OP); - acpigen_write_if_lequal_namestr_int(RFWU, expected_value); - acpigen_emit_byte(BREAK_OP); - acpigen_pop_len(); /* If */ - if (cmd == USB_RETIMER_FW_UPDATE_GET_MUX) { - acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_INVALID_MUX); - acpigen_write_sleep(USB4_RETIMER_POLL_CYCLE_MS); - acpigen_emit_byte(DECREMENT_OP); - acpigen_emit_byte(LOCAL2_OP); - acpigen_emit_byte(CONTINUE_OP); - acpigen_pop_len(); /* If */ - - acpigen_emit_byte(AND_OP); - acpigen_emit_namestring(RFWU); - acpigen_write_integer(USB_RETIMER_FW_UPDATE_MUX_MASK); - acpigen_emit_byte(LOCAL3_OP); - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(LOCAL3_OP); - acpigen_emit_byte(0); - acpigen_disable_tx_gpio(power_gpio); - acpigen_write_return_integer(-1); - acpigen_pop_len(); /* If */ - } else if (cmd == USB_RETIMER_FW_UPDATE_SET_TBT) { - /* - * EC return either USB_PD_MUX_USB4_ENABLED or USB_PD_MUX_TBT_COMPAT_ENABLED - * to RFWU after the USB_RETIMER_FW_UPDATE_SET_TBT command execution. It is - * needed to add additional check for USB_PD_MUX_TBT_COMPAT_ENABLED. - */ - acpigen_write_if_lequal_namestr_int(RFWU, USB_PD_MUX_TBT_COMPAT_ENABLED); + if (RFWU) { + acpigen_write_if_lequal_namestr_int(RFWU, expected_value); acpigen_emit_byte(BREAK_OP); acpigen_pop_len(); /* If */ + + if (cmd == USB_RETIMER_FW_UPDATE_GET_MUX) { + acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_INVALID_MUX); + acpigen_write_sleep(USB4_RETIMER_POLL_CYCLE_MS); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONTINUE_OP); + acpigen_pop_len(); /* If */ + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring(RFWU); + acpigen_write_integer(USB_RETIMER_FW_UPDATE_MUX_MASK); + acpigen_emit_byte(LOCAL3_OP); + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_byte(0); + acpigen_disable_tx_gpio(power_gpio); + acpigen_write_return_integer(-1); + acpigen_pop_len(); /* If */ + } else if (cmd == USB_RETIMER_FW_UPDATE_SET_TBT) { + /* + * EC return either USB_PD_MUX_USB4_ENABLED or USB_PD_MUX_TBT_COMPAT_ENABLED + * to RFWU after the USB_RETIMER_FW_UPDATE_SET_TBT command execution. It is + * needed to add additional check for USB_PD_MUX_TBT_COMPAT_ENABLED. + */ + acpigen_write_if_lequal_namestr_int(RFWU, USB_PD_MUX_TBT_COMPAT_ENABLED); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } } acpigen_write_sleep(USB4_RETIMER_POLL_CYCLE_MS); -- To view, visit https://review.coreboot.org/c/coreboot/+/84615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a219345440f91332f680885b51e2cc09f14f7a7 Gerrit-Change-Number: 84615 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[M] Change in coreboot[main]: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments
by Elyes Haouas (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Riku Viitanen. Elyes Haouas has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85822?usp=email ) Change subject: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Gerrit-Change-Number: 85822 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 17:29:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: qualcomm/common: Remove dead code
by Elyes Haouas (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85778?usp=email ) Change subject: qualcomm/common: Remove dead code ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40cffcf3714decfc54f2bbce9d4a867a9313d72e Gerrit-Change-Number: 85778 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 01 Jan 2025 17:28:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/findusb_debug: Check for lsusb and lspci
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Nicholas Chin. Riku Viitanen has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85796?usp=email ) Change subject: util/findusb_debug: Check for lsusb and lspci ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Gerrit-Change-Number: 85796 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 17:15:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/autoport/bd82x6x: Output the correct PCH version comment
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Riku Viitanen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85823?usp=email ) Change subject: util/autoport/bd82x6x: Output the correct PCH version comment ...................................................................... util/autoport/bd82x6x: Output the correct PCH version comment TEST=Tested with logs from 6-series and 7-series boards. Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85823/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Gerrit-Change-Number: 85823 Gerrit-PatchSet: 2 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[XS] Change in coreboot[main]: util/autoport/bd82x6x: Output the correct PCH version comment
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85823?usp=email ) Change subject: util/autoport/bd82x6x: Output the correct PCH version comment ...................................................................... util/autoport/bd82x6x: Output the correct PCH version comment Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85823/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index bd80901..fefddbc 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -104,9 +104,16 @@ pcieHotplugMap += "0 }" } + pchComment := "Intel Series " + if b.variant == "BD82X6X" { + pchComment += "6 Cougar Point PCH" + } else { + pchComment += "7 Panther Point PCH" + } + cur := DevTreeNode{ Chip: "southbridge/intel/bd82x6x", - Comment: "Intel Series 6 Cougar Point PCH", + Comment: pchComment, Registers: map[string]string{ "sata_interface_speed_support": "0x3", -- To view, visit https://review.coreboot.org/c/coreboot/+/85823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Gerrit-Change-Number: 85823 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[M] Change in coreboot[main]: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85822?usp=email ) Change subject: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments ...................................................................... util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments Since the aliases are used and already contain the device name, there's reason to generate these in the first place. TEST=Ran autoport with logs from ASRock Z77 Extreme4. Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M util/autoport/bd82x6x.go M util/autoport/sandybridge.go 2 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/85822/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 71b97d4..bd80901 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -124,29 +124,29 @@ "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), }, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal"}, }, } diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 29b57b4..552bd66 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -51,15 +51,15 @@ PCIController: true, ChildPCIBus: 0, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd"}, }, }, }, } - PutPCIDev(addr, "Host bridge") + PutPCIDev(addr, "") /* FIXME:XX some configs are unsupported. */ KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true -- To view, visit https://review.coreboot.org/c/coreboot/+/85822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Gerrit-Change-Number: 85822 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA pins to pull-down
by Yidi Lin (Code Review) 01 Jan '25

01 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85751?usp=email ) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA pins to pull-down ...................................................................... soc/mediatek/mt8196: Set SPMI-P SCL/SDA pins to pull-down The current Pull-Down capabilities of the SPMI are insufficient and require optimization. Configure the SCL and SDA of the SPMI-P to Pull-Down mode on MT8196 SoC side. It is done only once during the SPMI read check to fix SPMI clock calibration failure. TEST=Build pass BUG=b:361174333 Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85751 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index 91f9038..d00afe1 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -167,6 +167,9 @@ /* SPMI_P 14mA */ gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA); gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA); + /* SPMI-P set Pull-Down mode */ + gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); printk(BIOS_INFO, "%s done\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Angel Pons, Keith Hui. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: > Do you have to do anything special to make a PS/2 mouse work? Nope, it just works automatically in Devuan Daedalus (Linux 6.1 and Xfce 4.18). Kinda makes sense, since in vendor firmware there's also no setting to choose between a mouse and a keyboard. But on the other hand I recall seeing some other board in coreboot that had some issues with PS/2 mice connected like this. File src/mainboard/asrock/z77_extreme4/early_init.c: https://review.coreboot.org/c/coreboot/+/85772/comment/44bcd991_f8be791c?us… : PS12, Line 10: if (CONFIG(CONSOLE_SERIAL)) > The function will no-op itself if this config is not selected, so it's not necessary. Ack. Having the "if" here makes more sense imo. But yeah it's a bit redundant at the moment. Many other boards do this too, perhaps we should consistently have one style or the other. -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 12 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 12:38:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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