coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/system76/mtl: Enable NPU
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85721?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/system76/mtl: Enable NPU ...................................................................... mb/system76/mtl: Enable NPU Customers have asked that the NPU device be available. Test: Verified the device shows up in lspci. Change-Id: I2b5c3030c6378c0998a2ac792126c15d2e17bbf9 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85721 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/system76/mtl/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb index d409380..0e1eaac 100644 --- a/src/mainboard/system76/mtl/devicetree.cb +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -30,6 +30,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" end + device ref vpu on end device ref ioe_shared_sram on end device ref pmc_shared_sram on end device ref cnvi_wifi on -- To view, visit https://review.coreboot.org/c/coreboot/+/85721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5c3030c6378c0998a2ac792126c15d2e17bbf9 Gerrit-Change-Number: 85721 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: Documentation: Fix snb/ivb nri frequency table
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85757?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Documentation: Fix snb/ivb nri frequency table ...................................................................... Documentation: Fix snb/ivb nri frequency table 2*8*133 = 2133 Change-Id: Ic5e6120aaa9fe7db2a3c1651d2ea9443a24e7c4d Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85757 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/northbridge/intel/sandybridge/nri_freq.md 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 0732870..d641575 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -108,7 +108,7 @@ +------------+-----------+------------------+-------------------------+---------------+ | 933 | DDR3-1866 | 7 | 133 MHz | | +------------+-----------+------------------+-------------------------+---------------+ -| 1066 | DDR3-2166 | 8 | 133 MHz | | +| 1066 | DDR3-2133 | 8 | 133 MHz | | +------------+-----------+------------------+-------------------------+---------------+ ``` @@ -127,7 +127,7 @@ +------------+-----------+------------------+-------------------------+---------------+ | 933 | DDR3-1866 | 7 | 133 MHz | | +------------+-----------+------------------+-------------------------+---------------+ -| 1066 | DDR3-2166 | 8 | 133 MHz | | +| 1066 | DDR3-2133 | 8 | 133 MHz | | +------------+-----------+------------------+-------------------------+---------------+ | 700 | DDR3-1400 | 7 | 100 MHz | '1 | +------------+-----------+------------------+-------------------------+---------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/85757?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5e6120aaa9fe7db2a3c1651d2ea9443a24e7c4d Gerrit-Change-Number: 85757 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Enable CNVI WLAN based on fw_config
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85534?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/var/kanix: Enable CNVI WLAN based on fw_config ...................................................................... mb/google/rex/var/kanix: Enable CNVI WLAN based on fw_config BUG=b:377377766 TEST=emerge-rex coreboot pass Change-Id: Ibdf01e16267aa64bcf376001e108e2eaa677aaa6 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85534 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/kanix/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 4f912d8..83663e8 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -381,6 +381,16 @@ end end end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on + probe WIFI_TYPE WIFI_CNVI + end + end + end device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/85534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdf01e16267aa64bcf376001e108e2eaa677aaa6 Gerrit-Change-Number: 85534 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Adding device id for Crashlog and Telemetry
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85372?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Adding device id for Crashlog and Telemetry ...................................................................... soc/intel/pantherlake: Adding device id for Crashlog and Telemetry This patch adds device id for Crashlog and Telemetry. CPU crashlog record is stored in punit SRAM. Source: EDS 815002 BUG=None TEST=Build fatcat and boot with Panther Lake SoC with added device id. Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Change-Id: I2959623986108a2c5e3dce16e892913a42d71755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85372 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/sram/sram.c 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jamie Ryu: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 60a7d17..c882fdc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4934,6 +4934,7 @@ #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM 0x7a27 +#define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM 0xb07d /* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index e63f805..da7022d 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -35,6 +35,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_SRAM, PCI_DID_INTEL_PTL_U_H_SRAM, + PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM, PCI_DID_INTEL_LNL_SRAM, PCI_DID_INTEL_MTL_SOC_SRAM, PCI_DID_INTEL_MTL_IOE_M_SRAM, -- To view, visit https://review.coreboot.org/c/coreboot/+/85372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2959623986108a2c5e3dce16e892913a42d71755 Gerrit-Change-Number: 85372 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>

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[XS] Change in coreboot[main]: ec/acpi/ec.c: Promote timeout messages to errors
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85229?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/acpi/ec.c: Promote timeout messages to errors ...................................................................... ec/acpi/ec.c: Promote timeout messages to errors A timeout when attempting to read/write to an EC should be treated as an error, as it could potentially cause unwanted or unexpected behavior from the device. Change-Id: I60be6191dcd8ff576fa525f08720b6ea2d0a7454 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85229 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/ec/acpi/ec.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index dddfb6b..4378b02 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -45,7 +45,7 @@ int send_ec_command_timeout(u8 command, int timeout_us) { if (!ec_ready_send(timeout_us)) { - printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", + printk(BIOS_ERR, "Timeout while sending command 0x%02x to EC!\n", command); return -1; } @@ -63,7 +63,7 @@ int send_ec_data_timeout(u8 data, int timeout_us) { if (!ec_ready_send(timeout_us)) { - printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n", + printk(BIOS_ERR, "Timeout while sending data 0x%02x to EC!\n", data); return -1; } @@ -83,7 +83,7 @@ u8 data; if (!ec_ready_recv(timeout_us)) { - printk(BIOS_DEBUG, "Timeout while receiving data from EC!\n"); + printk(BIOS_ERR, "Timeout while receiving data from EC!\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85229?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60be6191dcd8ff576fa525f08720b6ea2d0a7454 Gerrit-Change-Number: 85229 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: elogtool: Correct invalid strings for wake source
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85155?usp=email ) Change subject: elogtool: Correct invalid strings for wake source ...................................................................... elogtool: Correct invalid strings for wake source elogtool output invalid strings for below two ids: ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f ELOG_WAKE_SOURCE_PME_TCSS_DMA 0x30 BUG=None TEST=None Change-Id: Ib68434fd675d3d32241b54161297dba66e5ea548 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85155 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/cbfstool/eventlog.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index b9a3706..4746670 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -318,8 +318,8 @@ {ELOG_WAKE_SOURCE_GPIO, " GPIO #"}, {ELOG_WAKE_SOURCE_PME_TBT, "PME - Thunderbolt"}, {ELOG_WAKE_SOURCE_PME_TCSS_XHCI, "PME - TCSS XHCI"}, - {ELOG_WAKE_SOURCE_PME_TCSS_XHCI, "PME - TCSS XDCI"}, - {ELOG_WAKE_SOURCE_PME_TCSS_XHCI, "PME - TCSS DMA"}, + {ELOG_WAKE_SOURCE_PME_TCSS_XDCI, "PME - TCSS XDCI"}, + {ELOG_WAKE_SOURCE_PME_TCSS_DMA, "PME - TCSS DMA"}, {0, NULL}, }; static const struct valstr ec_event_types[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib68434fd675d3d32241b54161297dba66e5ea548 Gerrit-Change-Number: 85155 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_mapping for the easy ones
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85923?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_mapping for the easy ones ...................................................................... mb/*: Drop xhci_overcurrent_mapping for the easy ones This is now copied from USBOCM1 built with main USB port config. Boards patched here have matching EHCI and xHCI overcurrent mappings. Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85923 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb 28 files changed, 0 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 8ecae25..0c12853 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -23,7 +23,6 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 161c613..ee5b06a 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -35,7 +35,6 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 05cb870..581b9a5 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -19,7 +19,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index e9b97bc..b1b3901 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -25,7 +25,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" device ref xhci on end diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 9e75c64..fe395d0 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -44,7 +44,6 @@ # enable ONLY ports present on stock MintBox/Intense PC #register "sata_port_map" = "0x1d" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb index 85c448d..0fd59a3 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end device ref gbe off end diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb index 3a0fa72..0f4f924 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end device ref sata1 on diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb index 4125159..5866828 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end end diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb index 631f404..3248dad 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb @@ -28,7 +28,6 @@ }" device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end end diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb index 8b9c82f..ef292bb 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb index 8c8820d..9f2c197 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -2,7 +2,6 @@ device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH device ref mei1 off end - register "xhci_overcurrent_mapping" = "0x00000c03" device ref pcie_rp2 on end device ref pcie_rp3 on device pci 00.0 on # PCI 1969:1091 diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb index 3511bbd..b4ab82f 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb @@ -14,7 +14,6 @@ # 0x1: 2.5", 0x2: DVD, 0x4: mSATA register "sata_port_map" = "0x7" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb index a8dcb17..1701159 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb @@ -8,7 +8,6 @@ register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb index 4684b0e..8340489 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb @@ -8,7 +8,6 @@ register "sata_port_map" = "0xf" register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb index dfd1cce..7955ff3 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb @@ -21,7 +21,6 @@ # HDD(0), ODD(1), mSATA(2), eSATA(4) register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, /* SSP1: dock */ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index ab6529e..735e4f3 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -20,7 +20,6 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x33" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index b3cc3a9..c6bc747 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -21,7 +21,6 @@ # HDD(0), ODD(1), mSATA(2), eSATA(4) register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 1, 0 }, diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 1ea6bb0..1d09f8b 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -22,7 +22,6 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x1f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, /* Dock USB3.0 */ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index c16634d..a91da32 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -20,7 +20,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x3" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, /* SSP1: dock */ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index 45a3c3e..772a6aa 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -20,7 +20,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x1" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 4e450ea..3944f4a 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -32,7 +32,6 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x5" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f86c31a..89dcf97 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -34,7 +34,6 @@ # Do not enable xHCI Port 4 since WWAN USB is EHCI-only register "superspeed_capable_ports" = "0x7" register "xhci_switchable_ports" = "0x7" - register "xhci_overcurrent_mapping" = "0x04000201" register "usb_port_config" = "{ { 1, 1, 0 }, { 1, 1, 1 }, diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index ba24ca9..12fed70 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -43,7 +43,6 @@ # Wire port 4 (wwan usb) to ehci for it lacks superspeed components register "xhci_switchable_ports" = "0x7" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 4abc9c0..84611d0 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -42,7 +42,6 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" register "usb_port_config" = "{ {0, 3, 0 }, /* P00 disconnected */ {1, 1, 1 }, /* P01 left or right */ diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index f47e3b7..3067096 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -44,7 +44,6 @@ # Do not enable xHCI Port 4 since WWAN USB is EHCI-only register "xhci_switchable_ports" = "0x7" register "superspeed_capable_ports" = "0x7" - register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 9f37526..2fa7137 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -53,7 +53,6 @@ register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" register "usb_port_config" = "{ diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 5c3c72b..dadde9f 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -58,7 +58,6 @@ register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" register "usb_port_config" = "{ diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index acaae83..0284c21 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -24,7 +24,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/85923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Gerrit-Change-Number: 85923 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Balaji Manigandan, Intel coreboot Reviewers, Jakub Czapiga, Jędrzej Ciupis, Pratikkumar V Prajapati, Sowmya Aralguppe, Subrata Banik. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84359?usp=email ) Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: would like to get some resolution here - either get this patch merged to fix dedede boards, or if crashlog hasn't been tested on JSL, removed entirely -- To view, visit https://review.coreboot.org/c/coreboot/+/84359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b Gerrit-Change-Number: 84359 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 20:14:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Disable UFS controller on every boot
by Dinesh Gehlot (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email ) Change subject: soc/intel/alderlake/romstage: Disable UFS controller on every boot ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 20:00:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: util/amdfwtool: Add binary parsing
by Maximilian Brune (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Ana Carolina Cabral, Anand Vaikar, Bao Zheng, Felix Held, Marshall Dawson, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84373?usp=email ) Change subject: util/amdfwtool: Add binary parsing ...................................................................... Patch Set 11: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84373/comment/514f161f_fe7062da?us… : PS8, Line 263: { .type = AMD_FW_MINIMSMU, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, : { .type = AMD_FW_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, > anything else to do here? ping -- To view, visit https://review.coreboot.org/c/coreboot/+/84373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78d7a9dba71de557e0a9a885d8561eea1f4191ef Gerrit-Change-Number: 84373 Gerrit-PatchSet: 11 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 Jan 2025 19:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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