coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/qemu-i440fx: refactor fw_cfg logic as separate driver
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85673?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/qemu-i440fx: refactor fw_cfg logic as separate driver ...................................................................... mb/qemu-i440fx: refactor fw_cfg logic as separate driver The fw_cfg device can be used by other qemu boards outside i440fx (and q35, which manually includes the code). Factor out the fw_cfg code as a separate driver that qemu mainboards can enable. Change-Id: I8c5c4cb5f5478abd21aab8e8d0b503db41d81d40 Signed-off-by: Carlos López <carlos.lopez(a)openchip.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85673 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/emulation/qemu/Kconfig M src/drivers/emulation/qemu/Makefile.mk R src/drivers/emulation/qemu/fw_cfg.c R src/include/device/fw_cfg.h R src/include/device/fw_cfg_if.h M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.mk M src/mainboard/emulation/qemu-i440fx/bootmode.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.mk M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/emulation/qemu-q35/cpu.c M src/mainboard/emulation/qemu-q35/memmap.c 15 files changed, 23 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 5b01ae7..cab0694 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -35,3 +35,9 @@ default 600 depends on LINEAR_FRAMEBUFFER depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS + +config DRIVERS_EMULATION_QEMU_FW_CFG + bool "qemu fw_cfg" + default n + help + qemu fw_cfg driver diff --git a/src/drivers/emulation/qemu/Makefile.mk b/src/drivers/emulation/qemu/Makefile.mk index 619782f..76bd864 100644 --- a/src/drivers/emulation/qemu/Makefile.mk +++ b/src/drivers/emulation/qemu/Makefile.mk @@ -7,3 +7,9 @@ ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += bochs.c ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_CIRRUS) += cirrus.c + +bootblock-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c +romstage-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c +verstage-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c +postcar-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c +ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/drivers/emulation/qemu/fw_cfg.c similarity index 99% rename from src/mainboard/emulation/qemu-i440fx/fw_cfg.c rename to src/drivers/emulation/qemu/fw_cfg.c index ad664a6..3725419 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/drivers/emulation/qemu/fw_cfg.c @@ -8,9 +8,8 @@ #include <arch/io.h> #include <acpi/acpi.h> #include <commonlib/endian.h> - -#include "fw_cfg.h" -#include "fw_cfg_if.h" +#include <device/fw_cfg.h> +#include <device/fw_cfg_if.h> #define FW_CFG_PORT_CTL 0x0510 #define FW_CFG_PORT_DATA 0x0511 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/include/device/fw_cfg.h similarity index 100% rename from src/mainboard/emulation/qemu-i440fx/fw_cfg.h rename to src/include/device/fw_cfg.h diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/include/device/fw_cfg_if.h similarity index 100% rename from src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h rename to src/include/device/fw_cfg_if.h diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 6d6181c..e17e25d 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -20,6 +20,7 @@ select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED select BOOT_DEVICE_SUPPORTS_WRITES + select DRIVERS_EMULATION_QEMU_FW_CFG config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.mk b/src/mainboard/emulation/qemu-i440fx/Makefile.mk index 6ff2f73..c20f427 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.mk +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.mk @@ -9,5 +9,4 @@ ramstage-y += northbridge.c ramstage-y += rom_media.c -all-y += fw_cfg.c all-y += bootmode.c diff --git a/src/mainboard/emulation/qemu-i440fx/bootmode.c b/src/mainboard/emulation/qemu-i440fx/bootmode.c index 12990b2..ce06478 100644 --- a/src/mainboard/emulation/qemu-i440fx/bootmode.c +++ b/src/mainboard/emulation/qemu-i440fx/bootmode.c @@ -2,7 +2,7 @@ #include <bootmode.h> #include <console/console.h> -#include "fw_cfg.h" +#include <device/fw_cfg.h> /* * Enable recovery mode with fw_cfg option to qemu: diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index be730b7..a8033f2 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -5,8 +5,8 @@ #include <arch/romstage.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <device/fw_cfg.h> #include "memory.h" -#include "fw_cfg.h" #define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71 diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 609e389..5c8636c 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -9,15 +9,14 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/device.h> +#include <device/fw_cfg.h> +#include <device/fw_cfg_if.h> #include <identity.h> #include <stdlib.h> #include <smbios.h> #include <types.h> #include "memory.h" -#include "fw_cfg.h" -#include "fw_cfg_if.h" - #include "acpi.h" static void qemu_reserve_ports(struct device *dev, unsigned int idx, diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 70a7437..854c053 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -18,6 +18,7 @@ select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED select BOOT_DEVICE_SUPPORTS_WRITES + select DRIVERS_EMULATION_QEMU_FW_CFG config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk index c1619f5..fc85e64 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.mk +++ b/src/mainboard/emulation/qemu-q35/Makefile.mk @@ -16,7 +16,6 @@ ramstage-y += memmap.c ramstage-y += cpu.c -all-y += ../qemu-i440fx/fw_cfg.c all-y += ../qemu-i440fx/bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index e85ce65..c1c483d 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <device/fw_cfg.h> -#include "../qemu-i440fx/fw_cfg.h" #include "../qemu-i440fx/acpi.h" void mainboard_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index c57ec50..c30c833 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -7,7 +7,7 @@ #include <cpu/x86/legacy_save_state.h> #include <cpu/x86/mp.h> #include <cpu/x86/smm.h> -#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> +#include <device/fw_cfg.h> #include <stddef.h> #include <stdint.h> diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index d57b25c..3e8da5c 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -5,9 +5,9 @@ #include <assert.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <device/fw_cfg.h> #include <device/pci_ops.h> #include <mainboard/emulation/qemu-i440fx/memory.h> -#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> #include <cpu/intel/smm_reloc.h> #include "q35.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/85673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c5c4cb5f5478abd21aab8e8d0b503db41d81d40 Gerrit-Change-Number: 85673 Gerrit-PatchSet: 3 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>

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[XS] Change in coreboot[main]: Documentation: Fix make rule for sphinx-autobuild
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85833?usp=email ) Change subject: Documentation: Fix make rule for sphinx-autobuild ...................................................................... Documentation: Fix make rule for sphinx-autobuild Add source directory to arguments of sphinx-autobuild Tested in docker and natively Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Signed-off-by: Vesek <venda.straka(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85833 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/Makefile.sphinx 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/Makefile.sphinx b/Documentation/Makefile.sphinx index c4984ec..93e5dfb 100644 --- a/Documentation/Makefile.sphinx +++ b/Documentation/Makefile.sphinx @@ -21,7 +21,7 @@ @echo "Starting sphinx-autobuild. The HTML pages are in $(BUILDDIR)." @echo "Press Ctrl-C to stop." @echo - $(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR) + $(SPHINXAUTOBUILD) "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) # Catch-all target: route all unknown targets to Sphinx using the new # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). -- To view, visit https://review.coreboot.org/c/coreboot/+/85833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Gerrit-Change-Number: 85833 Gerrit-PatchSet: 3 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/hp/pro_3500_series: Move usb configuration
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85831?usp=email ) Change subject: mb/hp/pro_3500_series: Move usb configuration ...................................................................... mb/hp/pro_3500_series: Move usb configuration Since commit 943b5409147 USB configurations are read from the southbridge devicetree This change only moves the USB configuration from early_init.c to the devicetree Change-Id: I69f1f800e4e2de5367795400d619bf9c000ff184 Signed-off-by: Vesek <venda.straka(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85831 Reviewed-by: Keith Hui <buurin(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/hp/pro_3500_series/devicetree.cb M src/mainboard/hp/pro_3500_series/early_init.c 2 files changed, 16 insertions(+), 17 deletions(-) Approvals: Keith Hui: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/hp/pro_3500_series/devicetree.cb b/src/mainboard/hp/pro_3500_series/devicetree.cb index cf75313..3d9cf61 100644 --- a/src/mainboard/hp/pro_3500_series/devicetree.cb +++ b/src/mainboard/hp/pro_3500_series/devicetree.cb @@ -22,6 +22,22 @@ register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 6, 0 }, + { 1, 6, 0 }, + { 1, 6, 1 }, + { 1, 9, 1 }, + { 1, 10, 2 }, + { 1, 11, 2 }, + { 1, 6, 3 }, + { 1, 6, 3 }, + { 1, 6, 4 }, + { 1, 12, 4 }, + { 1, 6, 6 }, + { 1, 11, 5 }, + { 1, 6, 5 }, + { 1, 6, 6 }, + }" device ref ehci2 on end device ref hda on end device ref pcie_rp2 on end # MINI_PCIE diff --git a/src/mainboard/hp/pro_3500_series/early_init.c b/src/mainboard/hp/pro_3500_series/early_init.c index fbf73cfb..1e149b5 100644 --- a/src/mainboard/hp/pro_3500_series/early_init.c +++ b/src/mainboard/hp/pro_3500_series/early_init.c @@ -8,23 +8,6 @@ #include "common_defines.h" #include "led.h" -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 6, 0 }, - { 1, 6, 0 }, - { 1, 6, 1 }, - { 1, 9, 1 }, - { 1, 10, 2 }, - { 1, 11, 2 }, - { 1, 6, 3 }, - { 1, 6, 3 }, - { 1, 6, 4 }, - { 1, 12, 4 }, - { 1, 6, 6 }, - { 1, 11, 5 }, - { 1, 6, 5 }, - { 1, 6, 6 }, -}; - void bootblock_mainboard_early_init(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/85831?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69f1f800e4e2de5367795400d619bf9c000ff184 Gerrit-Change-Number: 85831 Gerrit-PatchSet: 3 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Document latest test results
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78204?usp=email ) Change subject: Documentation/mb/asus/p8z77-m: Document latest test results ...................................................................... Documentation/mb/asus/p8z77-m: Document latest test results Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/mainboard/asus/p8z77-m.md 1 file changed, 63 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/Documentation/mainboard/asus/p8z77-m.md b/Documentation/mainboard/asus/p8z77-m.md index 23b28ee..0929cb0 100644 --- a/Documentation/mainboard/asus/p8z77-m.md +++ b/Documentation/mainboard/asus/p8z77-m.md @@ -35,80 +35,115 @@ ## Working - All USB2 ports (mouse, keyboard and thumb drive) -- USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB) +- USB3 ports on rear (Boots Arch-based SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB) - Gigabit Ethernet (RTL8111F) - SATA3, SATA2 (all ports, hot-swap not tested) - (Blue SATA2) (Blue SATA2) (White SATA3) - port 5 port 3 port 1 - port 6 port 4 port 2 - -- CPU Temp sensors and hardware monitor (some values don't make sense) +- CPU Temp sensors and hardware monitor (See [Known issues] below) - Native and MRC memory initialization - (please see [Native raminit compatibility] and [MRC memory compatibility]) + (please see [RAM compatibility] below) - Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM (VGA/DVI-D/HDMI tested and working) -- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3 - (Arch based)) +- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3) - Serial port - PCI slot - Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested) - Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from + - Rockwell HSF 56k PCI modem (detected, not function tested) + - Sound Blaster Live! CT4780 (detected, not function tested) + - Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from SeaBIOS) -- S3 suspend from Linux +- PCIe x1 slot + - MSI Herald-BE (Qualcomm NCM865 m.2 Wifi 7 module via PCIe-m.2 adaptor) +- LPC POST card manually wired to TPM header - 2-channel analog audio (WAV playback by mplayer via back panel line out port) +- HDMI digital audio - Windows 10 with libgfxinit high resolution framebuffer and VBT +- UEFI boot into Fedora 38 through 41 with edk2 payload (202306 mrchromebox fork) +- PS/2 keyboard (IBM Model M #1391401 & original Microsoft Natural) with edk2 payload ## Known issues - If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could be reconfigured by the blob. +- Sometimes only half the memory is initialized, and/or at reduced speed. This is being + investigated. + - If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config. Otherwise integrated graphics would fail with a black screen. - PCI POST card is not functional because the PCI bridge early init is not yet done. -- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for - an x8, and is electrically an x4 only. +- Although the black PCIEX16_2 slot can physically fit an x16 card, it only has physical + contacts for x8, and is electrically x4 only. + +- PS/2 keyboard may not work with SeaBIOS payload. + +- These lm_sensors configurations are needed for hardware monitor values to make sense: + +```bash +label in1 "+12V" +label in4 "+5V" +compute in1 @*12, @/12 +compute in4 @*5, @/5 +# ... +set temp1_type 4 +set temp2_type 4 + +``` ## Untested - Wake-on-LAN - USB3 on header -- TPM header +- TPM module - EHCI debugging (Debug port is on the 5-pin side of USB2_910 header) -- HDMI and S/PDIF audio out +- S/PDIF audio out ## Not working -- PS/2 keyboard or mouse +- PS/2 mouse (a patch has been submitted for review) - 4 and 6 channel analog audio out: Rear left and right audio is a muted copy of front left and right audio, and the other two channels are silent. -## Native (and MRC) raminit compatibility +## RAM compatibility + +### Native and MRC raminit: - OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600. - -- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable - with obvious pattern of bit errors during memtest86+ runs. - - Samsung PC3-10600U 2x2GB kit works at full rated speed. +- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on unbranded adapter works at full rated speed. + +### MRC raminit: + +- Corsair ValueSelect CMSO4GX3M1C1600C11 4GB SODIMM works at full rated speed + on an unbranded adapter. +- Samsung M471B5273DH0 4GB SODIMM on adapter works at full rated speed. + +### Native raminit: - Kingston KTH9600B-4G 2x4GB kit works at full rated speed. +- Samsung M471B5273DH0 4GB SODIMM on adapter works only at DDR3-1066 if max_mem_clock_mhz + is reduced to 666, and only one module would be detected. It will completely fail to + train if max_mem_clock_mhz is set to 800. +- Corsair modules on channel 1 fails training and is unusable. +- Two Patriot PV316G160C9K 2x8GB kits in all slots work at full rated speed. ## Extra onboard buttons -The board has two onboard buttons, and each has a related LED nearby. -What controls the LEDs and what the buttons control are unknown, -therefore they currently do nothing under coreboot. +The board has two onboard buttons, each with a related LED nearby. -- BIOS_FLBK +- `BIOS_FLBK` / `FLBK_LED`: OEM firmware uses this button to facilitate a simple update mechanism via a USB drive plugged into the bottom USB port of the USB/LAN stack. + They are connected to a proprietary AI1314 microcontroller. + They currently do nothing under coreboot. -- MemOK! +- `MemOK!` / `DRAM_LED`: OEM firmware uses this button for memory tuning related to overclocking. + They are connected to the NCT6779D super I/O chip. + Button is connected to pin 74, and currently do nothing under coreboot. + DRAM_LED is connected to GP07 pin. Active low. Since commit f7ed007298e0 + coreboot lights it up during early boot similar to vendor firmware. ## Technology @@ -132,6 +167,6 @@ - [Flash chip datasheet][W25Q64FVA1Q] -[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/ +[ASUS P8Z77-M]: https://www.asus.com/supportonly/p8z77-m/helpdesk_manual/ [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf [flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Keijzer <kevin(a)quietlife.nl>

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Drop unused MRC devicetree setting
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85821?usp=email ) Change subject: mb/asus/p8x7x-series: Drop unused MRC devicetree setting ...................................................................... mb/asus/p8x7x-series: Drop unused MRC devicetree setting Drop MRC setting usb3.hs_port_switch_mask that since commit ee126348726b ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree") mirrors xhci_switchable_ports and is no longer used separately. Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85821 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-) Approvals: Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index a54e6d8..fbff870 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,13 +7,6 @@ register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" - # 4 bit switch mask. 0=not switchable, 1=switchable - # Means once it's loaded the OS, it can swap ports - # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - register "usb3.hs_port_switch_mask" = "0xf" - # (The other 3 usb3.* settings can be set from nvram options, and so are set - # from runtime code) - device domain 0 on device ref peg10 on end # PCIEX16_1 device ref igd on end -- To view, visit https://review.coreboot.org/c/coreboot/+/85821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560 Gerrit-Change-Number: 85821 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/asus/p8x7x-series: Streamline devicetree configs
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85797?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/asus/p8x7x-series: Streamline devicetree configs ...................................................................... mb/asus/p8x7x-series: Streamline devicetree configs Drop PCI(e) devices from devicetree that remain off or unchanged from chipset defaults. TEST=Timeless binaries did not change across entire family. Change-Id: I4feb88a78f72952bed049505073aed00d2120df3 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85797 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 5 files changed, 0 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index b1b3901..a54e6d8 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -15,7 +15,6 @@ # from runtime code) device domain 0 on - device ref host_bridge on end device ref peg10 on end # PCIEX16_1 device ref igd on end @@ -28,30 +27,10 @@ register "xhci_switchable_ports" = "0x0000000f" device ref xhci on end - device ref mei1 on end - device ref mei2 off end - device ref me_ide_r off end - device ref me_kt off end - device ref gbe off end device ref ehci2 on end device ref hda on end - - device ref pcie_rp1 off end - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end - device ref pcie_rp5 off end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 off end - device ref ehci1 on end - device ref pci_bridge off end - device ref lpc on end device ref sata1 on end # SATA (AHCI) - device ref smbus on end - device ref sata2 off end # SATA (Legacy) - device ref thermal off end end end end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 1e8d807..c0d38b6 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -24,13 +24,9 @@ { 1, 0, 6 } }" device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # PCIEX1_1 device ref pcie_rp6 on end # 82574 GbE #1 device ref pcie_rp7 on end # 82574 GbE #2 - device ref pcie_rp8 off end device ref pci_bridge on end device ref lpc on chip superio/nuvoton/nct6776 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index 1389304..f1decba 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -22,9 +22,6 @@ }" register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # AR8161 GbE NIC device ref pcie_rp6 on end # ASM1083 PCI Bridge device ref pcie_rp7 on end # PCIEX1_1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index 50aed1b..c88b260 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -23,16 +23,12 @@ }" device ref pcie_rp1 on end # PCIe x4 slot - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # PCIe x1 slot device ref pcie_rp6 on # RTL8111F GbE NIC subsystemid 0x1849 0x1e1a device pci 00.0 on end # make onboard end device ref pcie_rp7 on end # PCI slot via ASM1083 - device ref pcie_rp8 off end device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 66bc5bb..4d8124a 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -24,9 +24,6 @@ register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # RTL8111 GbE NIC device ref pcie_rp6 on end # ASM1083 PCI Bridge device ref pcie_rp7 on end # PCIEX1_1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85797?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4feb88a78f72952bed049505073aed00d2120df3 Gerrit-Change-Number: 85797 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/autoport/bd82x6x: Output the correct PCH version comment
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85823?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/autoport/bd82x6x: Output the correct PCH version comment ...................................................................... util/autoport/bd82x6x: Output the correct PCH version comment TEST=Tested with logs from 6-series and 7-series boards. Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85823 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index bd80901..fefddbc 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -104,9 +104,16 @@ pcieHotplugMap += "0 }" } + pchComment := "Intel Series " + if b.variant == "BD82X6X" { + pchComment += "6 Cougar Point PCH" + } else { + pchComment += "7 Panther Point PCH" + } + cur := DevTreeNode{ Chip: "southbridge/intel/bd82x6x", - Comment: "Intel Series 6 Cougar Point PCH", + Comment: pchComment, Registers: map[string]string{ "sata_interface_speed_support": "0x3", -- To view, visit https://review.coreboot.org/c/coreboot/+/85823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Gerrit-Change-Number: 85823 Gerrit-PatchSet: 4 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85822?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments ...................................................................... util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments Since the aliases are used and already contain the device name, there's reason to generate these in the first place. TEST=Ran autoport with logs from ASRock Z77 Extreme4. Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85822 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/autoport/bd82x6x.go M util/autoport/sandybridge.go 2 files changed, 27 insertions(+), 27 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 71b97d4..bd80901 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -124,29 +124,29 @@ "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), }, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal"}, }, } diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 29b57b4..552bd66 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -51,15 +51,15 @@ PCIController: true, ChildPCIBus: 0, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd"}, }, }, }, } - PutPCIDev(addr, "Host bridge") + PutPCIDev(addr, "") /* FIXME:XX some configs are unsupported. */ KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true -- To view, visit https://review.coreboot.org/c/coreboot/+/85822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Gerrit-Change-Number: 85822 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/asrock/h77pro4-m/dt: Remove superfluous comments
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85761?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/asrock/h77pro4-m/dt: Remove superfluous comments ...................................................................... mb/asrock/h77pro4-m/dt: Remove superfluous comments Change-Id: Ie8d8d5287af8f3084f23c9d882202aa6ac8d4c5f Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85761 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/asrock/h77pro4-m/devicetree.cb 1 file changed, 26 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 469567e..93e4999 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -3,13 +3,13 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on - device ref host_bridge on # Host bridge + device ref host_bridge on subsystemid 0x1849 0x0100 end - device ref peg10 on # PEG - slot "PCIE1" + device ref peg10 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE1" "SlotDataBusWidth16X" end - device ref igd on # iGPU + device ref igd on subsystemid 0x1849 0x0102 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH @@ -38,49 +38,49 @@ { 1, 1, 5 }, { 1, 0, 6 } }" - device ref xhci on # USB 3.0 Controller + device ref xhci on subsystemid 0x1849 0x1e31 end - device ref mei1 on # Management Engine Interface 1 + device ref mei1 on subsystemid 0x1849 0x1e3a end - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT - device ref gbe off end # Intel Gigabit Ethernet - device ref ehci2 on # USB2 EHCI #2 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe off end + device ref ehci2 on subsystemid 0x1849 0x1e2d end - device ref hda on # High Definition Audio + device ref hda on subsystemid 0x1849 0x8892 end - device ref pcie_rp1 on # PCIe Port #1 - slot "PCIE4", 4 lanes + device ref pcie_rp1 on subsystemid 0x1849 0x1e10 smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIE4" "SlotDataBusWidth4X" end - device ref pcie_rp2 off end # PCIe Port #2 - device ref pcie_rp3 off end # PCIe Port #3 - device ref pcie_rp4 off end # PCIe Port #4 - device ref pcie_rp5 on # PCIe Port #5 - slot "PCIE2", 1 lane + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on subsystemid 0x1849 0x1e18 smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIE2" "SlotDataBusWidth1X" end - device ref pcie_rp6 on # PCIe Port #6 - RTL8111E GbE + device ref pcie_rp6 on # RTL8111E GbE subsystemid 0x1849 0x1e1a device pci 00.0 on end # PCI 10ec:8168 end - device ref pcie_rp7 on # PCIe Port #7 - slot "PCIE3", 1 lane + device ref pcie_rp7 on subsystemid 0x1849 0x1e16 smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthLong" "PCIE3" "SlotDataBusWidth1X" end - device ref pcie_rp8 on # PCIe Port #8 - ASM1061 SATA Controller + device ref pcie_rp8 on # ASM1061 SATA Controller subsystemid 0x1849 0x1e1e end - device ref ehci1 on # USB2 EHCI #1 + device ref ehci1 on subsystemid 0x1849 0x1e26 end - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge + device ref pci_bridge off end + device ref lpc on subsystemid 0x1849 0x1e4a chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -140,14 +140,14 @@ device pnp 2e.17 off end # GPIOA end end - device ref sata1 on # SATA (AHCI) + device ref sata1 on subsystemid 0x1849 0x1e02 end - device ref smbus on # SMBus + device ref smbus on subsystemid 0x1849 0x1e22 end - device ref sata2 off end # SATA (Legacy) - device ref thermal off end # Thermal + device ref sata2 off end + device ref thermal off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8d8d5287af8f3084f23c9d882202aa6ac8d4c5f Gerrit-Change-Number: 85761 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/asrock/h77pro4-m: Add SMBIOS slot descriptions
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85760?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/asrock/h77pro4-m: Add SMBIOS slot descriptions ...................................................................... mb/asrock/h77pro4-m: Add SMBIOS slot descriptions Based mostly on the comments in the file. Physical slot lengths checked from manufacturer's specs online. TEST: It still builds Change-Id: I706910dd192ca3415082955a7611d17702d3cfba Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85760 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/asrock/h77pro4-m/devicetree.cb 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 581b9a5..469567e 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -6,7 +6,9 @@ device ref host_bridge on # Host bridge subsystemid 0x1849 0x0100 end - device ref peg10 on end # PEG - slot "PCIE1" + device ref peg10 on # PEG - slot "PCIE1" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE1" "SlotDataBusWidth16X" + end device ref igd on # iGPU subsystemid 0x1849 0x0102 end @@ -54,12 +56,14 @@ end device ref pcie_rp1 on # PCIe Port #1 - slot "PCIE4", 4 lanes subsystemid 0x1849 0x1e10 + smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIE4" "SlotDataBusWidth4X" end device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp4 off end # PCIe Port #4 device ref pcie_rp5 on # PCIe Port #5 - slot "PCIE2", 1 lane subsystemid 0x1849 0x1e18 + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIE2" "SlotDataBusWidth1X" end device ref pcie_rp6 on # PCIe Port #6 - RTL8111E GbE subsystemid 0x1849 0x1e1a @@ -67,6 +71,7 @@ end device ref pcie_rp7 on # PCIe Port #7 - slot "PCIE3", 1 lane subsystemid 0x1849 0x1e16 + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthLong" "PCIE3" "SlotDataBusWidth1X" end device ref pcie_rp8 on # PCIe Port #8 - ASM1061 SATA Controller subsystemid 0x1849 0x1e1e -- To view, visit https://review.coreboot.org/c/coreboot/+/85760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I706910dd192ca3415082955a7611d17702d3cfba Gerrit-Change-Number: 85760 Gerrit-PatchSet: 4 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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