coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
by Paul Menzel (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85774?usp=email ) Change subject: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85774/comment/6c7e531d_91dd2054?us… : PS6, Line 13: mtk_cksys_init = 0x1 As this is log level info, could it be more informative for the user, like what 0x1 means? -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 23:53:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource
by Paul Menzel (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Benjamin Doron, Patrick Rudolph. Paul Menzel has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/79228?usp=email ) Change subject: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79228/comment/7a91ba55_0a308f1b?us… : PS1, Line 11: > Done Thank you for the explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/79228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I106c1730787a88c03719acfb8a80e7b840b29997 Gerrit-Change-Number: 79228 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 23:51:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Document latest test results
by Keith Hui (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Angel Pons, Kevin Keijzer, Nicholas Chin, Paul Menzel. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/78204?usp=email ) Change subject: Documentation/mb/asus/p8z77-m: Document latest test results ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > I should try again. I blame my SODIMM adapters. :P -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 23:41:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Keijzer <kevin(a)quietlife.nl> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Document latest test results
by Keith Hui (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Angel Pons, Kevin Keijzer, Nicholas Chin, Paul Menzel. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/78204?usp=email ) Change subject: Documentation/mb/asus/p8z77-m: Document latest test results ...................................................................... Patch Set 4: (1 comment) File Documentation/mainboard/asus/p8z77-m.md: https://review.coreboot.org/c/coreboot/+/78204/comment/228fe0e7_68da5649?us… : PS2, Line 106: It appears all memory modules rated for DDR3-1600 will fail to boot if : max_mem_clock_mhz is set to 800 in devicetree. > Rebase done, but I'm running into problems over there too. Take a look. Looks like the root cause of all my RAM problems is that my SODIMM adapters are failing. I bought four 8GB CL9 desktop DDR3 modules and they run perfect. -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 23:40:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Keijzer <kevin(a)quietlife.nl> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: util/autoport/bd82x6x: Output the correct PCH version comment
by Nicholas Chin (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Riku Viitanen. Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85823?usp=email ) Change subject: util/autoport/bd82x6x: Output the correct PCH version comment ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd99be965b41b49845a9a1072868ba43b445a79 Gerrit-Change-Number: 85823 Gerrit-PatchSet: 2 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 21:24:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/alderlake: Remove ADL-M Entries
by Sean Rhodes (Code Review) 01 Jan '25

01 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84651?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Remove ADL-M Entries ...................................................................... soc/intel/alderlake: Remove ADL-M Entries Support for `-M` was removed, so remove these. Change-Id: Ic2e58b951b5017e1642f6beecc8353ad9de7ce1e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84651 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/chipset.cb 1 file changed, 0 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 7ae1990..355ef2e 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -32,22 +32,6 @@ .tdp_pl4 = 215, }" - register "power_limits_config[ADL_M_282_12W_CORE]" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 35, - }" - - register "power_limits_config[ADL_M_282_15W_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 45, - }" - - register "power_limits_config[ADL_M_242_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 30, - .tdp_pl4 = 68, - }" - register "power_limits_config[ADL_N_081_7W_CORE]" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 25, -- To view, visit https://review.coreboot.org/c/coreboot/+/84651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2e58b951b5017e1642f6beecc8353ad9de7ce1e Gerrit-Change-Number: 84651 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/mtl: Enable all bits for IO decode register
by Sean Rhodes (Code Review) 01 Jan '25

01 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85707?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/mtl: Enable all bits for IO decode register ...................................................................... soc/intel/mtl: Enable all bits for IO decode register Based on discussions on various patches (CB:57140), the idea was to enable all bits to avoid incomplete ports. Therefore, enable all bits - the same as ADL. Change-Id: I5ace878faa09b959384338efcdbdfce390145002 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85707 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/bootblock/soc_die.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, but someone else must approve diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c index cfbc22c..71fc464 100644 --- a/src/soc/intel/meteorlake/bootblock/soc_die.c +++ b/src/soc/intel/meteorlake/bootblock/soc_die.c @@ -55,8 +55,10 @@ static void soc_die_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_LPT_EN | LPC_IOE_FDD_EN | + LPC_IOE_LGE_200 | LPC_IOE_HGE_208 | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | + LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ace878faa09b959384338efcdbdfce390145002 Gerrit-Change-Number: 85707 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/intel/usb4: Guard usage of RFMU with a null check
by Sean Rhodes (Code Review) 01 Jan '25

01 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84615?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/usb4: Guard usage of RFMU with a null check ...................................................................... drivers/intel/usb4: Guard usage of RFMU with a null check Add a null check around the usage of the RFWU (Retimer Firmware Update path) in the `usb4_retimer_execute_ec_cmd` function. This ensures that any interaction with RFWU is only performed when the path is valid, preventing potential null pointer dereferences. This fixes are large amount of errors when `ec_retimer_fw_update_path` isn't declared, such as comparisons like `If ((Local0 == Break))`. Change-Id: I5a219345440f91332f680885b51e2cc09f14f7a7 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84615 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: coreboot org <coreboot.org(a)gmail.com> --- M src/drivers/intel/usb4/retimer/retimer.c 1 file changed, 39 insertions(+), 34 deletions(-) Approvals: coreboot org: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 3769fc9..40dd4c1 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -36,10 +36,12 @@ /* Invoke EC Retimer firmware update command execution */ ec_retimer_fw_update(data); /* If RFWU has return value 0xfe, return error -1 */ - acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_ERROR); - acpigen_disable_tx_gpio(power_gpio); - acpigen_write_return_integer(-1); - acpigen_pop_len(); /* If */ + if (RFWU) { + acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_ERROR); + acpigen_disable_tx_gpio(power_gpio); + acpigen_write_return_integer(-1); + acpigen_pop_len(); /* If */ + } acpigen_write_store_int_to_op(USB4_RETIMER_ITERATION_NUM, LOCAL2_OP); acpigen_emit_byte(WHILE_OP); @@ -47,39 +49,42 @@ acpigen_emit_byte(LGREATER_OP); acpigen_emit_byte(LOCAL2_OP); acpigen_emit_byte(ZERO_OP); - acpigen_write_if_lequal_namestr_int(RFWU, expected_value); - acpigen_emit_byte(BREAK_OP); - acpigen_pop_len(); /* If */ - if (cmd == USB_RETIMER_FW_UPDATE_GET_MUX) { - acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_INVALID_MUX); - acpigen_write_sleep(USB4_RETIMER_POLL_CYCLE_MS); - acpigen_emit_byte(DECREMENT_OP); - acpigen_emit_byte(LOCAL2_OP); - acpigen_emit_byte(CONTINUE_OP); - acpigen_pop_len(); /* If */ - - acpigen_emit_byte(AND_OP); - acpigen_emit_namestring(RFWU); - acpigen_write_integer(USB_RETIMER_FW_UPDATE_MUX_MASK); - acpigen_emit_byte(LOCAL3_OP); - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(LOCAL3_OP); - acpigen_emit_byte(0); - acpigen_disable_tx_gpio(power_gpio); - acpigen_write_return_integer(-1); - acpigen_pop_len(); /* If */ - } else if (cmd == USB_RETIMER_FW_UPDATE_SET_TBT) { - /* - * EC return either USB_PD_MUX_USB4_ENABLED or USB_PD_MUX_TBT_COMPAT_ENABLED - * to RFWU after the USB_RETIMER_FW_UPDATE_SET_TBT command execution. It is - * needed to add additional check for USB_PD_MUX_TBT_COMPAT_ENABLED. - */ - acpigen_write_if_lequal_namestr_int(RFWU, USB_PD_MUX_TBT_COMPAT_ENABLED); + if (RFWU) { + acpigen_write_if_lequal_namestr_int(RFWU, expected_value); acpigen_emit_byte(BREAK_OP); acpigen_pop_len(); /* If */ + + if (cmd == USB_RETIMER_FW_UPDATE_GET_MUX) { + acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_INVALID_MUX); + acpigen_write_sleep(USB4_RETIMER_POLL_CYCLE_MS); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONTINUE_OP); + acpigen_pop_len(); /* If */ + + acpigen_emit_byte(AND_OP); + acpigen_emit_namestring(RFWU); + acpigen_write_integer(USB_RETIMER_FW_UPDATE_MUX_MASK); + acpigen_emit_byte(LOCAL3_OP); + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_byte(0); + acpigen_disable_tx_gpio(power_gpio); + acpigen_write_return_integer(-1); + acpigen_pop_len(); /* If */ + } else if (cmd == USB_RETIMER_FW_UPDATE_SET_TBT) { + /* + * EC return either USB_PD_MUX_USB4_ENABLED or USB_PD_MUX_TBT_COMPAT_ENABLED + * to RFWU after the USB_RETIMER_FW_UPDATE_SET_TBT command execution. It is + * needed to add additional check for USB_PD_MUX_TBT_COMPAT_ENABLED. + */ + acpigen_write_if_lequal_namestr_int(RFWU, USB_PD_MUX_TBT_COMPAT_ENABLED); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } } acpigen_write_sleep(USB4_RETIMER_POLL_CYCLE_MS); -- To view, visit https://review.coreboot.org/c/coreboot/+/84615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a219345440f91332f680885b51e2cc09f14f7a7 Gerrit-Change-Number: 84615 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[M] Change in coreboot[main]: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments
by Elyes Haouas (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Riku Viitanen. Elyes Haouas has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85822?usp=email ) Change subject: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Gerrit-Change-Number: 85822 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 17:29:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: qualcomm/common: Remove dead code
by Elyes Haouas (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85778?usp=email ) Change subject: qualcomm/common: Remove dead code ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40cffcf3714decfc54f2bbce9d4a867a9313d72e Gerrit-Change-Number: 85778 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 01 Jan 2025 17:28:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025