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[M] Change in coreboot[main]: util/intelp2m/fields: Add unit tests
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68673?usp=email ) Change subject: util/intelp2m/fields: Add unit tests ...................................................................... util/intelp2m/fields: Add unit tests Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68673 Reviewed-by: Daniel Maslowski <info(a)orangecms.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- A util/intelp2m/fields/cb/cb_test.go A util/intelp2m/fields/fsp/fsp_test.go A util/intelp2m/fields/raw/raw_test.go A util/intelp2m/fields/test/suite.go 4 files changed, 194 insertions(+), 0 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved Daniel Maslowski: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/util/intelp2m/fields/cb/cb_test.go b/util/intelp2m/fields/cb/cb_test.go new file mode 100644 index 0000000..64d735e --- /dev/null +++ b/util/intelp2m/fields/cb/cb_test.go @@ -0,0 +1,48 @@ +package cb_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/fields/cb" + "review.coreboot.org/coreboot.git/util/intelp2m/fields/test" +) + +// sliding-one + +func TestCbFields(t *testing.T) { + referenceSlice := []string{ + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RESET(PLTRST), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 29), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 28), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_TRIG(OFF), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE), PAD_CFG1_TOL_1V8),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RX_POL(INVERT), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(IOAPIC), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(SCI), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(SMI), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(NMI), PAD_IOSSTATE(HIZCRx1)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_IOSSTATE(Tx1RxDCRx1)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_IOSSTATE(Tx0RxDCRx1)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_IOSSTATE(Tx0RxDCRx0)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_PULL(INVALID)),", // Error invalid TERM value = 8 + "_PAD_CFG_STRUCT(, PAD_FUNC(NF4), PAD_PULL(DN_20K)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(NF2), PAD_PULL(DN_5K)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(NF1), PAD_PULL(INVALID)),", // Error invalid TERM value = 1 + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE), PAD_IOSTERM(ENPD)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), PAD_IOSTERM(DISPUPD)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 1), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | 1, 0),", + } + test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", cb.FieldMacros{}) +} diff --git a/util/intelp2m/fields/fsp/fsp_test.go b/util/intelp2m/fields/fsp/fsp_test.go new file mode 100644 index 0000000..90bbc0e --- /dev/null +++ b/util/intelp2m/fields/fsp/fsp_test.go @@ -0,0 +1,46 @@ +package fsp_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/fields/fsp" + "review.coreboot.org/coreboot.git/util/intelp2m/fields/test" +) + +func TestFSPFields(t *testing.T) { + referenceSlice := []string{ + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioPlatformReset, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLvlEdgDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntEdge, GpioResetPwrGood, GpioTolerance1v8 | GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntApic | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntSci | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntSmi | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntNmi | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, INVALID, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeNative4, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermWpd20K, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeNative2, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermWpd5K, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, INVALID, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutHigh, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + } + test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", fsp.FieldMacros{}) +} diff --git a/util/intelp2m/fields/raw/raw_test.go b/util/intelp2m/fields/raw/raw_test.go new file mode 100644 index 0000000..8cab698 --- /dev/null +++ b/util/intelp2m/fields/raw/raw_test.go @@ -0,0 +1,46 @@ +package raw_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/fields/raw" + "review.coreboot.org/coreboot.git/util/intelp2m/fields/test" +) + +func TestRAWFields(t *testing.T) { + referenceSlice := []string{ + "_PAD_CFG_STRUCT(, 0x80000000, 0x80000000),", + "_PAD_CFG_STRUCT(, 0x40000000, 0x40000000),", + "_PAD_CFG_STRUCT(, 0x20000000, 0x20000000),", + "_PAD_CFG_STRUCT(, 0x10000000, 0x10000000),", + "_PAD_CFG_STRUCT(, 0x08000000, 0x08000000),", + "_PAD_CFG_STRUCT(, 0x04000000, 0x04000000),", + "_PAD_CFG_STRUCT(, 0x02000000, 0x02000000),", + "_PAD_CFG_STRUCT(, 0x01000000, 0x01000000),", + "_PAD_CFG_STRUCT(, 0x00800000, 0x00800000),", + "_PAD_CFG_STRUCT(, 0x00400000, 0x00400000),", + "_PAD_CFG_STRUCT(, 0x00200000, 0x00200000),", + "_PAD_CFG_STRUCT(, 0x00100000, 0x00100000),", + "_PAD_CFG_STRUCT(, 0x00080000, 0x00080000),", + "_PAD_CFG_STRUCT(, 0x00040000, 0x00040000),", + "_PAD_CFG_STRUCT(, 0x00020000, 0x00020000),", + "_PAD_CFG_STRUCT(, 0x00010000, 0x00010000),", + "_PAD_CFG_STRUCT(, 0x00008000, 0x00008000),", + "_PAD_CFG_STRUCT(, 0x00004000, 0x00004000),", + "_PAD_CFG_STRUCT(, 0x00002000, 0x00002000),", + "_PAD_CFG_STRUCT(, 0x00001000, 0x00001000),", + "_PAD_CFG_STRUCT(, 0x00000800, 0x00000800),", + "_PAD_CFG_STRUCT(, 0x00000400, 0x00000400),", + "_PAD_CFG_STRUCT(, 0x00000200, 0x00000200),", + "_PAD_CFG_STRUCT(, 0x00000100, 0x00000100),", + "_PAD_CFG_STRUCT(, 0x00000080, 0x00000080),", + "_PAD_CFG_STRUCT(, 0x00000040, 0x00000040),", + "_PAD_CFG_STRUCT(, 0x00000020, 0x00000020),", + "_PAD_CFG_STRUCT(, 0x00000010, 0x00000010),", + "_PAD_CFG_STRUCT(, 0x00000008, 0x00000008),", + "_PAD_CFG_STRUCT(, 0x00000004, 0x00000004),", + "_PAD_CFG_STRUCT(, 0x00000002, 0x00000002),", + "_PAD_CFG_STRUCT(, 0x00000001, 0x00000001),", + } + test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", raw.FieldMacros{}) +} diff --git a/util/intelp2m/fields/test/suite.go b/util/intelp2m/fields/test/suite.go new file mode 100644 index 0000000..a61062e --- /dev/null +++ b/util/intelp2m/fields/test/suite.go @@ -0,0 +1,54 @@ +package test + +import ( + "fmt" + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" +) + +type TestCase struct { + DW0, DW1 uint32 + Ownership uint8 + Reference string +} + +func (tc TestCase) Check(actuallyMacro string) error { + if actuallyMacro != tc.Reference { + return fmt.Errorf(`TestCase: DW0 = %d, DW1 = %d, Ownership = %d: +Expects: '%s' +Actually: '%s'`, tc.DW0, tc.DW1, tc.Ownership, tc.Reference, actuallyMacro) + } + return nil +} + +type Suite []TestCase + +func (suite Suite) Run(t *testing.T, label string, decoderIf common.Fields) { + t.Run(label, func(t *testing.T) { + platform := snr.PlatformSpecific{} + macro := common.GetInstanceMacro(platform, decoderIf) + dw0 := macro.Register(common.PAD_CFG_DW0) + dw1 := macro.Register(common.PAD_CFG_DW1) + for _, tc := range suite { + macro.Clear() + macro.PadIdSet("").SetPadOwnership(tc.Ownership) + dw0.ValueSet(tc.DW0) + dw1.ValueSet(tc.DW1) + macro.Fields.GenerateString() + if err := tc.Check(macro.Get()); err != nil { + t.Errorf("Test failed: %v", err) + } + } + }) +} + +func SlidingOneTestSuiteCreate(referenceSlice []string) Suite { + suite := make([]TestCase, len(referenceSlice)) + dw := uint32(0x80000000) + for i, reference := range referenceSlice { + suite[i] = TestCase{DW0: dw >> i, DW1: dw >> i, Reference: reference} + } + return suite +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Gerrit-Change-Number: 68673 Gerrit-PatchSet: 20 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: util/intelp2m/parser: Add unit test
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67701?usp=email ) Change subject: util/intelp2m/parser: Add unit test ...................................................................... util/intelp2m/parser: Add unit test Also add an interface for printing macros to override this in the test and not create a new gpio file for comparison. Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67701 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/parser/parser_test.go A util/intelp2m/parser/test/inteltool_test.log 4 files changed, 292 insertions(+), 126 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index 1f3333b..5e17721 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -9,6 +9,20 @@ "review.coreboot.org/coreboot.git/util/intelp2m/parser" ) +type Printer struct{} + +func (Printer) Linef(lvl int, format string, args ...interface{}) { + if config.InfoLevelGet() >= lvl { + fmt.Fprintf(config.OutputGenFile, format, args...) + } +} + +func (Printer) Line(lvl int, str string) { + if config.InfoLevelGet() >= lvl { + fmt.Fprint(config.OutputGenFile, str) + } +} + var ( // Version is injected into main during project build Version string = "Unknown" @@ -19,28 +33,6 @@ fmt.Printf("[ intelp2m ] Version: %s\n", Version) } -// generateOutputFile - generates include file -// parser : parser data structure -func generateOutputFile(parser *parser.ParserData) (err error) { - header := fmt.Sprintf(`/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CFG_GPIO_H -#define CFG_GPIO_H - -#include <gpio.h> - -/* Pad configuration was generated automatically using intelp2m %s */ -static const struct pad_config gpio_table[] = {`, Version) - config.OutputGenFile.WriteString(header + "\n") - // Add the pads map - parser.PadMapFprint() - config.OutputGenFile.WriteString(`}; - -#endif /* CFG_GPIO_H */ -`) - return nil -} - // main func main() { // Command line arguments @@ -148,13 +140,31 @@ config.OutputGenFile = outputGenFile config.InputRegDumpFile = inputRegDumpFile - parser := parser.ParserData{} - parser.Parse() + prs := parser.ParserData{} + prs.Parse() - // gpio.h - err = generateOutputFile(&parser) - if err != nil { - fmt.Printf("Error! Can not create the file with GPIO configuration!\n") + generator := parser.Generator{ + PrinterIf: Printer{}, + Data: &prs, + } + header := fmt.Sprintf(`/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m %s */ +static const struct pad_config gpio_table[] = {`, Version) + config.OutputGenFile.WriteString(header + "\n") + // Add the pads map + + if err := generator.Run(); err != nil { + fmt.Printf("Error: %v", err) os.Exit(1) } + config.OutputGenFile.WriteString(`}; + +#endif /* CFG_GPIO_H */ +`) } diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index f6ed047..c30c695 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -2,21 +2,22 @@ import ( "bufio" + "errors" "fmt" - "strings" "strconv" + "strings" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg" + "review.coreboot.org/coreboot.git/util/intelp2m/config" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl" - "review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg" - "review.coreboot.org/coreboot.git/util/intelp2m/config" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl" ) // PlatformSpecific - platform-specific interface @@ -42,57 +43,16 @@ ownership uint8 } -// generate - wrapper for Fprintf(). Writes text to the file specified -// in config.OutputGenFile -func (info *padInfo) generate(lvl int, line string, a ...interface{}) { - if config.InfoLevelGet() >= lvl { - fmt.Fprintf(config.OutputGenFile, line, a...) - } -} - -// titleFprint - print GPIO group title to file -// /* ------- GPIO Group GPP_L ------- */ -func (info *padInfo) titleFprint() { - info.generate(0, "\n\t/* %s */\n", info.function) -} - -// reservedFprint - print reserved GPIO to file as comment -// /* GPP_H17 - RESERVED */ -func (info *padInfo) reservedFprint() { - info.generate(2, "\n") - // small comment about reserved port - info.generate(0, "\t/* %s - %s */\n", info.id, info.function) -} - -// padInfoMacroFprint - print information about current pad to file using -// special macros: -// PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */ -// gpio : gpio.c file descriptor -// macro : string of the generated macro -func (info *padInfo) padInfoMacroFprint(macro string) { - info.generate(2, - "\n\t/* %s - %s */\n\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */\n", - info.id, - info.function, - info.dw0, - info.dw1) - info.generate(0, "\t%s", macro) - if config.InfoLevelGet() == 1 { - info.generate(1, "\t/* %s */", info.function) - } - info.generate(0, "\n") -} - // ParserData - global data // line : string from the configuration file // padmap : pad info map // RawFmt : flag for generating pads config file with DW0/1 reg raw values // Template : structure template type of ConfigFile type ParserData struct { - platform PlatformSpecific - line string - padmap []padInfo - ownership map[string]uint32 + platform PlatformSpecific + line string + padmap []padInfo + ownership map[string]uint32 } // hostOwnershipGet - get the host software ownership value for the corresponding @@ -118,14 +78,14 @@ var dw0, dw1 uint32 var template = map[int]template{ config.TempInteltool: UseInteltoolLogTemplate, - config.TempGpioh : useGpioHTemplate, - config.TempSpec : useYourTemplate, + config.TempGpioh: useGpioHTemplate, + config.TempSpec: useYourTemplate, } if template[config.TemplateGet()](parser.line, &function, &id, &dw0, &dw1) == 0 { pad := padInfo{id: id, - function: function, - dw0: dw0, - dw1: dw1, + function: function, + dw0: dw0, + dw1: dw1, ownership: parser.hostOwnershipGet(id)} parser.padmap = append(parser.padmap, pad) return 0 @@ -143,56 +103,46 @@ // PlatformSpecificInterfaceSet - specific interface for the platform selected // in the configuration func (parser *ParserData) PlatformSpecificInterfaceSet() { - var platform = map[uint8]PlatformSpecific { - config.SunriseType : snr.PlatformSpecific{}, + var platform = map[uint8]PlatformSpecific{ + config.SunriseType: snr.PlatformSpecific{}, // See platforms/lbg/macro.go - config.LewisburgType : lbg.PlatformSpecific{ - InheritanceTemplate : snr.PlatformSpecific{}, + config.LewisburgType: lbg.PlatformSpecific{ + InheritanceTemplate: snr.PlatformSpecific{}, }, - config.ApolloType : apl.PlatformSpecific{}, - config.CannonType : cnl.PlatformSpecific{ - InheritanceTemplate : snr.PlatformSpecific{}, + config.ApolloType: apl.PlatformSpecific{}, + config.CannonType: cnl.PlatformSpecific{ + InheritanceTemplate: snr.PlatformSpecific{}, }, - config.TigerType : tgl.PlatformSpecific{}, - config.AlderType : adl.PlatformSpecific{}, - config.JasperType : jsl.PlatformSpecific{}, - config.MeteorType : mtl.PlatformSpecific{}, + config.TigerType: tgl.PlatformSpecific{}, + config.AlderType: adl.PlatformSpecific{}, + config.JasperType: jsl.PlatformSpecific{}, + config.MeteorType: mtl.PlatformSpecific{}, // See platforms/ebg/macro.go - config.EmmitsburgType : ebg.PlatformSpecific{ - InheritanceTemplate : cnl.PlatformSpecific{ - InheritanceTemplate : snr.PlatformSpecific{}, + config.EmmitsburgType: ebg.PlatformSpecific{ + InheritanceTemplate: cnl.PlatformSpecific{ + InheritanceTemplate: snr.PlatformSpecific{}, }, }, } parser.platform = platform[config.PlatformGet()] } -// PadMapFprint - print pad info map to file -func (parser *ParserData) PadMapFprint() { - for _, pad := range parser.padmap { - switch pad.dw0 { - case 0: - pad.titleFprint() - case 0xffffffff: - pad.reservedFprint() - default: - str := parser.platform.GenMacro(pad.id, pad.dw0, pad.dw1, pad.ownership) - pad.padInfoMacroFprint(str) - } - } -} - // Register - read specific platform registers (32 bits) // line : string from file with pad config map // nameTemplate : register name femplate to filter parsed lines // return -// valid : true if the dump of the register in intertool.log is set in accordance -// with the template -// name : full register name -// offset : register offset relative to the base address -// value : register value +// +// valid : true if the dump of the register in intertool.log is set in accordance +// with the template +// name : full register name +// offset : register offset relative to the base address +// value : register value func (parser *ParserData) Register(nameTemplate string) ( - valid bool, name string, offset uint32, value uint32) { + valid bool, + name string, + offset uint32, + value uint32, +) { if strings.Contains(parser.line, nameTemplate) && config.TemplateGet() == config.TempInteltool { if registerInfoTemplate(parser.line, &name, &offset, &value) == 0 { @@ -204,7 +154,8 @@ } // padOwnershipExtract - extract Host Software Pad Ownership from inteltool dump -// return true if success +// +// return true if success func (parser *ParserData) padOwnershipExtract() bool { var group string status, name, offset, value := parser.Register("HOSTSW_OWN_GPP_") @@ -212,13 +163,14 @@ _, group = parser.platform.GroupNameExtract(parser.line) parser.ownership[group] = value fmt.Printf("\n\t/* padOwnershipExtract: [offset 0x%x] %s = 0x%x */\n", - offset, name, parser.ownership[group]) + offset, name, parser.ownership[group]) } return status } // padConfigurationExtract - reads GPIO configuration registers and returns true if the -// information from the inteltool log was successfully parsed. +// +// information from the inteltool log was successfully parsed. func (parser *ParserData) padConfigurationExtract() bool { // Only for Sunrise or CannonLake, and only for inteltool.log file template if config.TemplateGet() != config.TempInteltool || config.IsPlatformApollo() { @@ -242,7 +194,7 @@ scanner := bufio.NewScanner(config.InputRegDumpFile) for scanner.Scan() { parser.line = scanner.Text() - isIncluded, _ := common.KeywordsCheck(parser.line, "GPIO Community", "GPIO Group"); + isIncluded, _ := common.KeywordsCheck(parser.line, "GPIO Community", "GPIO Group") if isIncluded { parser.communityGroupExtract() } else if !parser.padConfigurationExtract() && parser.platform.KeywordCheck(parser.line) { @@ -253,3 +205,48 @@ } fmt.Println("...done!") } + +type PrinterIf interface { + Linef(lvl int, format string, args ...interface{}) + Line(lvl int, str string) +} + +type Generator struct { + Data *ParserData // information from the parser + PrinterIf // interface for printing +} + +// Run - generate a new gpio file based on the information from the parser +func (g Generator) Run() error { + if g.PrinterIf == nil && g.Data == nil { + return errors.New("Generator: Incorrect initialization") + } + for _, pad := range g.Data.padmap { + switch pad.dw0 { + case 0x00000000: + // titleFprint - print GPIO group title to file + // /* ------- GPIO Group GPP_L ------- */ + g.Linef(0, "\n\t/* %s */\n", pad.function) + case 0xffffffff: + // reservedFprint - print reserved GPIO to file as comment + // /* GPP_H17 - RESERVED */ + g.Line(2, "\n") + // small comment about reserved port + g.Linef(0, "\t/* %s - %s */\n", pad.id, pad.function) + default: + // padInfoMacroFprint - print information about current pad to file using + // special macros: + // PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */ + platform := g.Data.platform + macro := platform.GenMacro(pad.id, pad.dw0, pad.dw1, pad.ownership) + g.Linef(2, "\n\t/* %s - %s */\n\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */\n", + pad.id, pad.function, pad.dw0, pad.dw1) + g.Linef(0, "\t%s", macro) + if config.InfoLevelGet() == 1 { + g.Linef(1, "\t/* %s */", pad.function) + } + g.Line(0, "\n") + } + } + return nil +} diff --git a/util/intelp2m/parser/parser_test.go b/util/intelp2m/parser/parser_test.go new file mode 100644 index 0000000..4f0e452 --- /dev/null +++ b/util/intelp2m/parser/parser_test.go @@ -0,0 +1,104 @@ +package parser_test + +import ( + "fmt" + "os" + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/config" + "review.coreboot.org/coreboot.git/util/intelp2m/parser" +) + +const testLogFilePath = "test/inteltool_test.log" + +type Printer struct { + lines []string +} + +func (p *Printer) Linef(lvl int, format string, args ...interface{}) { + if config.InfoLevelGet() >= lvl { + p.lines = append(p.lines, fmt.Sprintf(format, args...)) + } +} + +func (p *Printer) Line(lvl int, str string) { + if config.InfoLevelGet() >= lvl { + p.lines = append(p.lines, str) + } +} + +func TestParser(t *testing.T) { + t.Run("PARSER/PARSE-INTELTOOL-FILE", func(t *testing.T) { + reference := []string{ + "\n\t/* ------- GPIO Community 0 ------- */\n", + "\n\t/* ------- GPIO Group GPP_A ------- */\n", + "\tPAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),", "\t/* RCIN# */", "\n", + "\tPAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),", "\t/* LAD0 */", "\n", + "\tPAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),", "\t/* LFRAME# */", "\n", + "\tPAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),", "\t/* SUSWARN#/SUSPWRDNACK */", "\n", + "\tPAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI),", "\t/* GPIO */", "\n", + "\n\t/* ------- GPIO Group GPP_B ------- */\n", + "\t/* GPP_C1 - RESERVED */\n", + "\tPAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),", "\t/* GPIO */", "\n", + "\tPAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2),", "\t/* PCHHOT# */", "\n", + "\n\t/* ------- GPIO Community 1 ------- */\n", + "\n\t/* ------- GPIO Group GPP_C ------- */\n", + "\tPAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),", "\t/* SMBCLK */", "\n", + "\tPAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),", "\t/* GPIO */", "\n", + "\t/* GPP_C6 - RESERVED */\n", + "\t/* GPP_C7 - RESERVED */\n", + "\tPAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),", "\t/* UART2_RTS# */", "\n", + "\n\t/* ------- GPIO Group GPP_D ------- */\n", + "\n\t/* ------- GPIO Group GPP_E ------- */\n", + "\tPAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),", "\t/* SATAXPCIE0 */", "\n", + "\n\t/* ------- GPIO Group GPP_G ------- */\n", + "\tPAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1),", "\t/* SMI# */", "\n", + "\n\t/* ------- GPIO Community 2 ------- */\n", + "\n\t/* -------- GPIO Group GPD -------- */\n", + "\tPAD_CFG_NF(GPD9, NONE, PWROK, NF1),", "\t/* SLP_WLAN# */", "\n", + "\n\t/* ------- GPIO Community 3 ------- */\n", + "\n\t/* ------- GPIO Group GPP_I ------- */\n", + "\tPAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),", "\t/* DDPB_HPD0 */", "\n", + "\tPAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),", "\t/* DDPC_HPD1 */", "\n", + "\tPAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),", "\t/* DDPD_HPD2 */", "\n", + } + + input, err := os.Open(testLogFilePath) + if err != nil { + t.Errorf("Something is wrong with the test file - %s!\n", testLogFilePath) + os.Exit(1) + } + defer input.Close() + + config.InputRegDumpFile = input + config.FldStyleSet("none") + config.NonCheckingFlagSet(true) + config.InfoLevelSet(1) + + prs := parser.ParserData{} + prs.Parse() + + printer := Printer{lines: make([]string, 0)} + generator := parser.Generator{ + PrinterIf: &printer, + Data: &prs, + } + + if err := generator.Run(); err != nil { + t.Errorf("Generator: %v", err) + os.Exit(1) + } + + if len(printer.lines) == len(reference) { + for i := range printer.lines { + if printer.lines[i] != reference[i] { + t.Errorf("\nExpects: '%s'\nActually: '%s'\n\n", reference[i], printer.lines[i]) + return + } + } + } else { + t.Errorf("%d does not match the reference slice len - %d!", + len(reference), len(printer.lines)) + } + }) +} diff --git a/util/intelp2m/parser/test/inteltool_test.log b/util/intelp2m/parser/test/inteltool_test.log new file mode 100644 index 0000000..4c01d63 --- /dev/null +++ b/util/intelp2m/parser/test/inteltool_test.log @@ -0,0 +1,55 @@ +CPU: ID 0x906e9, Processor Type 0x0, Family 0x6, Model 0x9e, Stepping 0x9 +Northbridge: 8086:591f (unknown) +Southbridge: 8086:a143 (H110) +IGD: 8086:5912 (Intel(R) UHD Graphics 630) +Trying to reveal Primary to Sideband Bridge (P2SB), +let's hope the OS doesn't mind... done. +SBREG_BAR = 0xfd000000 (MEM) + +Hiding Primary to Sideband Bridge (P2SB). + +============= GPIOS ============= + +------- GPIO Community 0 ------- + +PCR Port ID: 0xaf0000 + +------- GPIO Group GPP_A ------- +0x0400: 0x0000001884000502 GPP_A0 RCIN# +0x0408: 0x0000301984000402 GPP_A1 LAD0 +0x0428: 0x0000001d84000600 GPP_A5 LFRAME# +0x0468: 0x0000002544000600 GPP_A13 SUSWARN#/SUSPWRDNACK +0x04b8: 0x0000002f84000102 GPP_A23 GPIO +------- GPIO Group GPP_B ------- +0x0438: 0xffffffffffffffff GPP_C1 RESERVED +0x04c0: 0x0000003084000100 GPP_B0 GPIO +0x0578: 0x0000104784000a01 GPP_B23 PCHHOT# +------- GPIO Community 1 ------- + +PCR Port ID: 0xae0000 + +------- GPIO Group GPP_C ------- +0x0400: 0x0000004844000502 GPP_C0 SMBCLK +0x0428: 0x0000004d84000100 GPP_C5 GPIO +0x0430: 0xffffffffffffffff GPP_C6 RESERVED +0x0438: 0xffffffffffffffff GPP_C7 RESERVED +0x04b0: 0x0000005e84000600 GPP_C22 UART2_RTS# +------- GPIO Group GPP_D ------- +------- GPIO Group GPP_E ------- +0x0580: 0x0000301884000502 GPP_E0 SATAXPCIE0 +------- GPIO Group GPP_G ------- +0x0740: 0x0000005084000500 GPP_G19 SMI# +------- GPIO Community 2 ------- + +PCR Port ID: 0xad0000 + +-------- GPIO Group GPD -------- +0x0448: 0x0000002104000600 GPD9 SLP_WLAN# +------- GPIO Community 3 ------- + +PCR Port ID: 0xac0000 + +------- GPIO Group GPP_I ------- +0x0400: 0x0000006d84000500 GPP_I0 DDPB_HPD0 +0x0408: 0x0000006e84000502 GPP_I1 DDPC_HPD1 +0x0410: 0x0000006f84000502 GPP_I2 DDPD_HPD2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67701?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Gerrit-Change-Number: 67701 Gerrit-PatchSet: 20 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/volteer/variants/drobit: fix power_limits_config
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86026?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/volteer/variants/drobit: fix power_limits_config ...................................................................... mb/google/volteer/variants/drobit: fix power_limits_config Drobit shows little power usage (around 9W) and very low clock speeds (1.1GHz - 1.4GHz) under load (`stress -c $(nproc)`), despite being at temperature too low for thermal throttling (40-50C). It turns out that power_limits_config is set to the lower end of the dptf power limit ranges as opposed to baseboard and other variants. This seems to prevent the device from using the intended power limits. Tested: Boot and confirm more reasoable power usage (17W) and clock speeds (around 2.5GHz) as well as good temperatures (topped 85C) and stability under 100% load (`stress -c $(nproc)` for 30min). Device for tests is i5-1135G7 and 16GG RAM. Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Signed-off-by: Ingo Reitz <9l(a)9lo.re> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86026 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index c791079..148af6e 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -12,8 +12,8 @@ register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 28, + .tdp_pl1_override = 17, + .tdp_pl2_override = 64, .tdp_pl4 = 105, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/86026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Gerrit-Change-Number: 86026 Gerrit-PatchSet: 7 Gerrit-Owner: Ingo Reitz <9l(a)9lo.re> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[M] Change in coreboot[main]: drivers/pc80/pc/keyboard.c: Add function to change a command byte bit
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85330?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/pc80/pc/keyboard.c: Add function to change a command byte bit ...................................................................... drivers/pc80/pc/keyboard.c: Add function to change a command byte bit Some keyboard controllers need to have a specific bit in the command byte set (e.g. PC_KBC_TRANSLATE) in order for the keyboard to function properly. Change-Id: I8745d1848f223634043eecc4659021a76a2b239b Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85330 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/pc80/pc/keyboard.c M src/include/pc80/keyboard.h 2 files changed, 57 insertions(+), 14 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index a96dba7..f086391 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -22,19 +22,6 @@ #define KBC_CMD_SELF_TEST 0xAA // Controller self-test #define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test -/* The Keyboard controller command byte - * BIT | Description - * ----+------------------------------------------------------- - * 7 | reserved, must be zero - * 6 | XT Translation, (1 = on, 0 = off) - * 5 | Disable Mouse Port (1 = disable, 0 = enable) - * 4 | Disable Keyboard Port (1 = disable, 0 = enable) - * 3 | reserved, must be zero - * 2 | System Flag (1 = self-test passed. DO NOT SET TO ZERO) - * 1 | Mouse Port Interrupts (1 = enable, 0 = disable) - * 0 | Keyboard Port Interrupts (1 = enable, 0 = disable) - */ - // Keyboard Controller Replies #define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded @@ -369,3 +356,34 @@ kbc_cleanup_buffers(); } + +enum cb_err pc_keyboard_set_command_byte_bit(u8 bit, u8 value) +{ + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting to read command byte\n"); + return CB_KBD_INTERFACE_FAILURE; + } + outb(KBC_CMD_READ_COMMAND, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Timeout waiting to read command byte\n"); + return CB_KBD_INTERFACE_FAILURE; + } + u8 byte = inb(KBD_DATA); + + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting to write command byte\n"); + return CB_KBD_INTERFACE_FAILURE; + } + outb(KBC_CMD_WRITE_COMMAND, KBD_COMMAND); + + byte = value ? (byte | BIT(bit)) : (byte & ~BIT(bit)); + + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting to write command byte\n"); + return CB_KBD_INTERFACE_FAILURE; + } + outb(byte, KBD_DATA); + + return CB_SUCCESS; +} diff --git a/src/include/pc80/keyboard.h b/src/include/pc80/keyboard.h index 6664980..a799e33d 100644 --- a/src/include/pc80/keyboard.h +++ b/src/include/pc80/keyboard.h @@ -3,12 +3,37 @@ #ifndef PC80_KEYBOARD_H #define PC80_KEYBOARD_H -#include <stdint.h> +#include <types.h> #define NO_AUX_DEVICE 0 #define PROBE_AUX_DEVICE 1 +/* + * The Keyboard controller command byte + * + * BIT | Description + * ----+------------------------------------------------------- + * 7 | reserved, must be zero : + * 6 | XT Translation : 1 = on, 0 = off + * 5 | Disable Mouse Port : 1 = disable, 0 = enable + * 4 | Disable Keyboard Port : 1 = disable, 0 = enable + * 3 | reserved, must be zero : + * 2 | System Flag : 1 = self-test passed (DO NOT SET TO ZERO) + * 1 | Mouse Port Interrupts : 1 = enable, 0 = disable + * 0 | Keyboard Port Interrupts : 1 = enable, 0 = disable + * ----+------------------------------------------------------- + */ +enum { + PC_KBC_KBD_INT = 0, + PC_KBC_AUX_INT = 1, + PC_KBC_SYS = 2, + PC_KBC_KBD_DISABLE = 4, + PC_KBC_AUX_DISABLE = 5, + PC_KBC_TRANSLATE = 6, +}; + uint8_t pc_keyboard_init(uint8_t probe_aux); void set_kbc_ps2_mode(void); +enum cb_err pc_keyboard_set_command_byte_bit(u8 bit, u8 value); #endif /* PC80_KEYBOARD_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8745d1848f223634043eecc4659021a76a2b239b Gerrit-Change-Number: 85330 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85809?usp=email ) Change subject: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable ...................................................................... soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable On x86_32 the xHCI BAR isn't reachable as it's mapped in high MMIO. Currently this is not a problem since the code is unused. Add a check and return NULL instead of cutting of the higher bits and thus do not return an invalid pointer. On x86_64 it's working when the extended page-tables are installed. Change-Id: I00496ad476c33e0984d7cb0019f27154302edda5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85809 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/ebg/soc_xhci.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/ebg/soc_xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c index f8aa37b..f7b1320 100644 --- a/src/soc/intel/xeon_sp/ebg/soc_xhci.c +++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c @@ -17,6 +17,13 @@ printk(BIOS_ERR, "XHCI BAR is not found\n"); return NULL; } + +#if ENV_X86_32 + assert(res->base < 0x100000000ULL); + if (res->base >= 0x100000000ULL) + return NULL; +#endif + return (void *)(uintptr_t)res->base; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85809?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00496ad476c33e0984d7cb0019f27154302edda5 Gerrit-Change-Number: 85809 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Enable x86_64
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85805?usp=email ) Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ...................................................................... soc/intel/xeon_sp/skx: Enable x86_64 On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of the address space. Most of the PCI BARs reside in high MMIO, not reachable by x86_32 coreboot. Add support for x86_64 coreboot and confirm that all supported boards are booting without errors. This is done by: - converting all occurrences of VOID * to UINT32 to make sure that FSP UPDs do not change when pointers are 8byte wide. - Drop SetupStructPtr as it's unused within FSP and coreboot TEST: Booted on ocp/tiogapass to Linux. No errors were observed. Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/mainboard/ocp/tiogapass/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 3 files changed, 36 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Shuo Liu: Looks good to me, but someone else must approve diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 276285a..ca54aba 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -20,6 +20,9 @@ static void oem_update_iio(FSPM_UPD *mupd) { + UPD_IIO_BIFURCATION_DATA_ENTRY *entry = + (void *)(uintptr_t)mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr; + /* Read GPIO to decide IIO bifurcation at run-time. */ int slot_config0 = gpio_get(GPP_C15); int slot_config1 = gpio_get(GPP_C16); @@ -28,25 +31,24 @@ reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation accordingly is left for future work. */ if (!slot_config0 && slot_config1) - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation - = IIO_BIFURCATE_xxx8xxx8; + entry[Skt0_Iou0].Bifurcation = IIO_BIFURCATE_xxx8xxx8; } static void mainboard_config_iio(FSPM_UPD *mupd) { memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr = + (uintptr_t)(UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table); - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; + mupd->FspmConfig.IioPciConfig.ConfigurationTablePtr = + (uintptr_t)(UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; mupd->FspmConfig.IioPciConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_pci_port_skt0); - mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; + mupd->FspmConfig.PchPciConfig.PciPortConfigPtr = + (uintptr_t)(UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; mupd->FspmConfig.PchPciConfig.NumberOfEntries = ARRAY_SIZE(tp_pch_pci_port_skt0); @@ -88,7 +90,7 @@ mainboard_config_iio(mupd); /* do not configure GPIO controller inside FSP-M */ - mupd->FspmConfig.GpioConfig.GpioTable = NULL; + mupd->FspmConfig.GpioConfig.GpioTablePtr = 0; mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; } diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 970dba3..acbc31f 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,8 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select UDK_202005_BINDING + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT help Intel Skylake-SP support diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index f81e218..2049716 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -37,6 +37,9 @@ #pragma pack(1) +/* Must not use VOID * since that would break x86_64 coreboot support! */ +#define PTR_32B(type) UINT32 + /** FSP Header Version Number **/ @@ -261,7 +264,7 @@ /** GPIOTABLE_CONFIG: GpioTable - Base Address of the Gpio Table declared by the - bootloader. + bootloader. Pointer to UPD_GPIO_INIT_CONFIG. Default: NULL NumberofEntries - Number of Entries in the GPIO Table provided Default: 0 @@ -269,8 +272,8 @@ configuration using default GPIO_INIT_CONFIG tables **/ typedef struct { - UPD_GPIO_INIT_CONFIG *GpioTable; - UINT32 NumberOfEntries; + PTR_32B(UPD_GPIO_INIT_CONFIG) GpioTablePtr; + UINT32 NumberOfEntries; } GPIOTABLE_CONFIG; /** @@ -293,7 +296,7 @@ /** IIOBIFURCATION_CONFIG: IIoBifurcationTable - Base Address of the IIO Bifurcation table - declared by the bootloader + declared by the bootloader. Pointer to UPD_IIO_BIFURCATION_DATA_ENTRY. Default: NULL NumberofEntries - Number of Entries in the IIO Bifurcation Table Default: 0 @@ -301,8 +304,8 @@ bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables **/ typedef struct { - UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable; - UINT32 NumberOfEntries; + PTR_32B(UPD_IIO_BIFURCATION_DATA_ENTRY) IIoBifurcationTablePtr; + UINT32 NumberOfEntries; } IIOBIFURCATION_CONFIG; /** @@ -381,13 +384,12 @@ /** PCIEPORT_CONFIG: PciePortConfiguration - Pointer to an array of PCIe port configuration structures - as declared above + as declared above. Pointer to UPD_PCI_PORT_CONFIG. NumberOfEntries - Number of elements in the PciePortConfiguration Array **/ typedef struct { - UPD_PCI_PORT_CONFIG *ConfigurationTable; - - UINT16 NumberOfEntries; + PTR_32B(UPD_PCI_PORT_CONFIG) ConfigurationTablePtr; + UINT16 NumberOfEntries; } IIOPCIPORT_CONFIG; /** @@ -412,12 +414,13 @@ /** IIORESOURCE_CONFIG: - ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array + ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array. + Pointer to UPD_IIO_STACK_RESOURCE_CONFIG. NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array **/ typedef struct { - UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable; - UINT16 NumberOfEntries; + PTR_32B(UPD_IIO_STACK_RESOURCE_CONFIG) ResourceTablePtr; + UINT16 NumberOfEntries; } IIORESOURCE_CONFIG; /** @@ -436,6 +439,7 @@ /** PCHPCIPORT_CONFIG: PciPortConfig - Pointer to an array of PCH PCI Ports to be configured + Pointer to UPD_PCH_PCIE_PORT. RootPortFunctionSwapping - Disable root port swapping based on device connection status PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage @@ -446,10 +450,10 @@ NumberOfEntries - Number of entries in the PCH PCI Port configuration **/ typedef struct { - UPD_PCH_PCIE_PORT *PciPortConfig; - UINT8 RootPortFunctionSwapping; - UINT8 PciePllSsc; - UINT16 NumberOfEntries; + PTR_32B(UPD_PCH_PCIE_PORT) PciPortConfigPtr; + UINT8 RootPortFunctionSwapping; + UINT8 PciePllSsc; + UINT16 NumberOfEntries; } PCHPCIPORT_CONFIG; /** FSP-M Configuration @@ -507,12 +511,7 @@ **/ UINT8 BoardId; - UINT8 reserved2[24]; - -/** Offset 0x00C2 **/ - VOID *SetupStructPtr; - - UINT8 reserved3[20]; + UINT8 reserved2[48]; /** Offset 0x00DA - IioPciConfig IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. @@ -529,7 +528,7 @@ **/ IIORESOURCE_CONFIG IioResourceConfig; - UINT8 reserved4[3]; + UINT8 reserved3[3]; /** Offset 0x00F1 - DCI Enable Enable / Disable DCI -- To view, visit https://review.coreboot.org/c/coreboot/+/85805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Gerrit-Change-Number: 85805 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation: Add Topton N100 (X2F)
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85680?usp=email ) Change subject: Documentation: Add Topton N100 (X2F) ...................................................................... Documentation: Add Topton N100 (X2F) Document the board and how to flash coreboot. Change-Id: Id585b064054b338ea8cead6edb6c5153030b9cde Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85680 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/topton/adl/x2f-n100.md 2 files changed, 108 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4cbcaf6..f9f9048 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -408,6 +408,13 @@ Beaglebone Black <ti/beaglebone-black.md> ``` +## Topton +```{toctree} +:maxdepth: 1 + +X2F-N100 <topton/adl/x2f-n100.md> +``` + ## UP ```{toctree} diff --git a/Documentation/mainboard/topton/adl/x2f-n100.md b/Documentation/mainboard/topton/adl/x2f-n100.md new file mode 100644 index 0000000..c386ad3 --- /dev/null +++ b/Documentation/mainboard/topton/adl/x2f-n100.md @@ -0,0 +1,101 @@ +# Topton N100 (X2F)2 Firewall Appliance + +This page describes how to run coreboot on the Topton N100. + +```{eval-rst} ++---------------+---------------------------------+----------------------+ +| Binary file | Apply | Required / Optional | ++===============+=================================+======================+ +| IFD | Intel Flash Descriptor | Required (see below) | ++---------------+---------------------------------+----------------------+ +| ME | Intel Management Engine | Required (see below) | ++---------------+---------------------------------+----------------------+ +| FSP-M & FSP-S | Intel Firmware Support Package | Required | ++---------------+---------------------------------+----------------------+ +``` + +## Flashing coreboot + +**WARNING:** There are multiple devices from the same vendor with +similar name, using different board layout, capabilities and EC/SuperIO. + +Likewise, there are other vendors selling their devices with +the same mainboard. According to the sticker on the box: `H30W-N100-226`. + +Please **DO NOT cross-flash firmware on "similar-looking" device**. +Doing so **may kill your device**. You have been warned :) + +### Internally + +Vendor of this motherboard hasn't locked any flash regions, resulting +in [flashprog] having full access to the SPI chip. +Assuming that user had booted Linux with `iomem=relaxed`, they can: +- Flash coreboot from stock firmware +- Flash stock firmware from coreboot +- Update coreboot build to a newer version + + Without opening the case and connecting the SPI flasher. + +Please note that for AlderLake-N platform you will need to use +[flashprog] v1.3.0 or newer. + +[flashrom] is broken due to regressions, which results in +failed flashes, bricking the device. + +[flashprog] is a better maintained fork of [flashrom], which +works flawlessly. + +You can skip extracting `SI_BIOS` and `SI_ME` regions from your ROM +and flash coreboot to `SI_BIOS` region by issuing the following command: +`flashprog -p internal --ifd -i SI_BIOS -w ./build/coreboot.rom` + +### Externally + +SPI chip on this mainboard is located near the SoC, on the other side +of the board (upper-right corner). +Please note that SPI voltage on this board is standard 3.3V, despite +using mobile SoC. +Vendor populated this board with Winbond W25Q128JV chip in SOIC-8 package. + +## Functionality + +### Tested and working + +- All USB ports (including mPCIe) +- All NICs (4x Intel I226-V 2.5GbE) +- All display outputs (HDMI, DisplayPort) +- M.2 NVME (PCIe x2 electrically) +- mPCIe WiFi +- SATA port +- Intel PTT (fTPM 2.0) +- PC Speaker (goes beep-boop) +- Serial console on the front of the device (RS232 in RJ45 form-factor), +"Cisco-style" +- PCIe passtrough (NICs to VMs, such as OpenWrt using libvirt) + +- Payload: EDK2, LinuxBoot +- OS: Alpine Linux, Windows 11 + +### Untested, broken + +- 5G modem on special M.2-like connector (lack hardware for it). +- Suspend in Windows 11 +(might work, but Windows has been tested from USB drive). + +## Specification +```{eval-rst} ++--------+-------------------------------+ +| SoC | Intel AlderLake N100 (IoT) | ++--------+-------------------------------+ +| Memory | DDR5 SO-DIMM (single-channel) | ++--------+-------------------------------+ +| EC | ITE IT8625E | ++--------+-------------------------------+ +| SPI | Winbond W25Q128 (16MiB 3.3V) | ++--------+-------------------------------+ +| NIC | 4x Intel I226-V (2.5GbE) | ++--------+-------------------------------+ +``` + +[flashprog]: https://flashprog.org/wiki/Flashprog +[flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/85680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id585b064054b338ea8cead6edb6c5153030b9cde Gerrit-Change-Number: 85680 Gerrit-PatchSet: 4 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation: Add Erying Polestar G613 Pro
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81611?usp=email ) Change subject: Documentation: Add Erying Polestar G613 Pro ...................................................................... Documentation: Add Erying Polestar G613 Pro Document the board and process of building/flashing coreboot on it. Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81611 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A Documentation/mainboard/erying/tgl/tgl_matx.md M Documentation/mainboard/index.md 2 files changed, 211 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/Documentation/mainboard/erying/tgl/tgl_matx.md b/Documentation/mainboard/erying/tgl/tgl_matx.md new file mode 100644 index 0000000..1234a1c --- /dev/null +++ b/Documentation/mainboard/erying/tgl/tgl_matx.md @@ -0,0 +1,203 @@ +# Erying Polestar G613 Pro + +This page describes how to run coreboot on the [Erying Polestar G613 Pro]. + +## Required proprietary blobs + +To build full working image of coreboot, the following blobs are required: + +```{eval-rst} ++-----------------+---------------------------------+----------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+======================+ +| Microcode | CPU Microcode | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +| FSP-M & FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+----------------------+ +| ME | Intel Management Engine | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +| FD | Intel Flash Descriptor | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +``` + +Microcode for those SoCs cannot be generated from the tree. +While boards with D1 (production) stepping may work, microcode Intel had +included in their tree is too old, which causes issues with APIC +(Advanced Programmable Interrupt Controller), resulting in overall instability. + +This is **required** for boards sold with D0 SoC revision (Engineering Sample). +Maintainer of this port had included publicly-available [microcodes] in +`3rdparty/blobs` coreboot repository, which are being pulled as submodule. + +To choose appropriate microcode for your system, you should choose: +1. If your motherboard uses Engineering Sample (D0) stepping: + - `cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin` +2. If your motherboard uses retail (D1) stepping: + - `cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin` + +By going to `Chipset -> Include CPU microcode in CBFS +(Include external microcode binary)` + +Failure to choose an appropriate microcode may result in: +- Bricked (unbootable) board +- Issues with APIC, resulting in random freezes +- MCE (Machine Check Exception) errors +- Unstable system RAM, leading to bit flips and data corruption + +There are no extra steps required for FSP. +Both SKUs work perfectly with FSP Intel publishes in their public repository. +coreboot automatically pulls FSP binary from `3rdparty/fsp` submodule +at build time, which points to TigerLakeFspBinPkg/Client package in +official Intel FSP repository. + +## Flashing coreboot + +### Internally + +Vendor of this motherboard hasn't locked any flash regions, resulting in +[flashrom] having full access to the SPI chip. +Assuming that user had booted Linux with `iomem=relaxed`, they can: +- Flash coreboot from stock firmware +- Flash stock firmware from coreboot +- Update coreboot build to a newer version + +Without opening the case and connecting the SPI flasher. +Please note that you will need to use [flashrom] v1.3.0 or newer, +as older versions won't detect the chipset. + +If you're using [flashrom] or [flashprog] (fork of flashrom), you can +skip extracting `SI_BIOS` and `SI_ME` regions from your ROM, and flash +coreboot to `SI_BIOS` region by issuing the following command: +`flashrom -p internal --ifd -i SI_BIOS -w ./build/coreboot.rom` + +### Externally + +SPI chip on this mainboard is located right underneath the PCH heatsink. +Due to it's location, it's likely that you will need to move (or remove) +the PCH (Platform Controller Hub) heatsink in order to clip it properly. + +Vendor populated this board with Winbond W25Q128FV chip in SOIC-8 package. +Although the stock chip is 16MiB, it is possible to replace it with 32MiB +equivalent if user desires to use LinuxBoot payload instead of EDK2. + +Please note that SPI voltage on this board is standard 3.3V, +despite using mobile SoC and PCH. + +## Tested and working + +- RS232 serial output from IT8613E for debugging (cbmem, Linux) +- Fan control from userspace (IT8613E Environment Controller) +- USB2.0 and 3.0 +- HDMI (iGPU, including audio) +- Realtek RTL8111 (GbE NIC) +- Realtek ALC897 (integrated audio) +- PCIe x16 4.0 (SoC) +- PCIe x1 3.0 (PCH) +- M.2 x4 4.0 (SoC) +- M.2 x4 3.0 (PCH) +- M.2 NGFF (WiFi) +- 4x SATA3 ports +- IOMMU/VT-x (PCIe passthrough) +- PCIe ReBAR (Resizable BAR) +- Intel PTT (fTPM 2.0) + +## Work in progress, broken, issues + +- XMP Profiles (some people reported issues, despite successful tests). +You can enable it by setting `SpdProfileSelected` in `romstage_fsp_params.c`. +See [FSP XMP flags] for configuration options, proceed with caution. +- GOP init on external GPUs (most EDK2 branches do not include module +necessary to load external Option ROMs) +- Sleep states (which were broken on stock as well) +- USB3.2 might take few tries to get detected at full speed +- iGPU DisplayPort (very simple fix, did not have time to fix GPIO) +- Automatic fan control (fans will always spin at 50% - see below) +- 2x USB2.0 FP and M.2 NGFF USB2.0 not mapped (yet) +- PCIe ASPM (results in AER spam in dmesg) + +Please ensure to: +- Disable sleep state in your OS to prevent data loss +- Configure automatic fan control using pwmconfig +(`modprobe it87 force_id=0x8603`) +- Append `pcie_aspm=off` to your kernel commandline to avoid dmesg spam. + +## Notes + +1. Required blobs, if flashing the entire flash chip. + They can be skipped safely if you are planning on flashing + only the `SI_BIOS` region. + - Intel Flash Descriptor (IFD): `descriptor.bin` + - Intel Management Engine (ME): `me.bin` + + Both blobs included in `3rdparty/blobs` repository were extracted + from vendor's firmware (available to download on their website). + IFD region has been modified using `ifdtool` to set + `MeAltDisable` flag. + +2. Modifications + + It is possible to replace Winbond 16MB chip with 32MB equivalent, + which would allow you to use LinuxBoot or implement + RO + A/B VBOOT update scheme. + +3. Payload and pre-OS display output + + If you are using an external graphics card (AMD, Nvidia, Intel Arc), + you will see output in your OS as soon as kernel initializes the + card (called "modprobing" in Linux) regardless of payload you chose. + + This board was tested with following payloads: + - EDK2 + - U-Boot + - LinuxBoot (U-Root + Linux kernel) + +If you would like to see output on your iGPU before that stage +(for picking a different boot medium or toggling Secure Boot setting), +you need to use [MrChromebox's EDK2] fork and include [GOP driver] for +TigerLake iGPU in your build. + +This will allow you to see output of EDK2 (payload, boot picker) +on your monitor connected to iGPU. + +If you're planning to primarly use an external card, disable iGPU by +enabling `Chipset -> Disable Integrated GFX Controller (0:2:0)` +and use [elly's EDK2] tree. + +In order to enable loading Option ROMs from PCIe devices, go to: +`Payload -> edk2 additional custom build parameters` +and add the string: `-D LOAD_OPTION_ROMS=TRUE` + +This functionality has been tested with following graphics cards, +with following results: +- Nvidia GeForce RTX3080, RTX3090: Works perfectly +- AMD Radeon RX6600XT, RX7800XT: Works with ReBAR disabled, +no output in EDK2 with ReBAR enabled +- Intel Arc A580: Works with ReBAR disabled, +corrupted framebuffer before modprobing with ReBAR enabled + +## Specification + +```{eval-rst} ++------------------+------------------------------+ +| SoC | Intel TigerLake Halo | ++------------------+------------------------------+ +| PCH | Intel HM570 | ++------------------+------------------------------+ +| Super I/O | ITE IT8613E | ++------------------+------------------------------+ +| SPI | Winbond W25Q128FV 16MiB 3.3V | ++------------------+------------------------------+ +| NIC | Realtek RTL8111 | ++------------------+------------------------------+ +| Audio | Realtek ALC897 | ++------------------+------------------------------+ +``` + +[Erying Polestar G613 Pro]: https://www.erying.cc/products-detail/id-97.html +[microcodes]: https://github.com/platomav/CPUMicrocodes/tree/master/Intel +[FSP XMP Flags]: https://github.com/intel/FSP/blob/master/TigerLakeFspBinPkg/Client/Include/… +[MrChromebox's EDK2]: https://github.com/MrChromebox/edk2 +[elly's EDK2]: https://github.com/ellyq/edk2 +[GOP driver]: https://github.com/MrChromebox/blobs/blob/master/soc/intel/tgl/IntelGopDriv… +[flashrom]: https://flashrom.org/Flashrom +[flashprog]: https://flashprog.org/wiki/Flashprog diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0009ef4..4cbcaf6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -97,6 +97,14 @@ QEMU POWER9 <emulation/qemu-power9.md> ``` +## Erying + +```{toctree} +:maxdepth: 1 + +Polestar G613 Pro <erying/tgl/tgl_matx.md> +``` + ## Facebook ```{toctree} -- To view, visit https://review.coreboot.org/c/coreboot/+/81611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Gerrit-Change-Number: 81611 Gerrit-PatchSet: 9 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com>

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[XS] Change in coreboot[main]: mb/erying/tgl: Remove unnecessary include in bootblock
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85856?usp=email ) Change subject: mb/erying/tgl: Remove unnecessary include in bootblock ...................................................................... mb/erying/tgl: Remove unnecessary include in bootblock Change-Id: I52de6b6ea6eb88ddb96e353161f365cc0fda807c Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85856 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/erying/tgl/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/mainboard/erying/tgl/bootblock.c b/src/mainboard/erying/tgl/bootblock.c index 15be8ce..3f51096 100644 --- a/src/mainboard/erying/tgl/bootblock.c +++ b/src/mainboard/erying/tgl/bootblock.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8613e/it8613e.h> -#include <gpio.h> #define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) #define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) -- To view, visit https://review.coreboot.org/c/coreboot/+/85856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52de6b6ea6eb88ddb96e353161f365cc0fda807c Gerrit-Change-Number: 85856 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Matt DeVillier (Code Review) 22 Jan '25

22 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85832?usp=email ) Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... mb/asus/h61-series: Add P8H67-I DELUXE variant On vendor firmware, the IFD is read-only and ME completely locked. But the BIOS region can be internally flashed with coreboot. Super I/O GP15 is connected to HDA_SDO, potentially enabling write access to entire flash. Simply setting this GPIO, and restarting the board wasn't enough. Tested: - i5-2500K - 8GB or 2x8GB Hynix HMT41GS6BFR8A-RD (@1333MHz) - 8+4GB Hynix HMT351S6EFR8A-PB (@1333MHz) - Internal SATA ports - Realtek Ethernet - libgfxinit, onboard DVI - All rear USB and USB3 ports, internal Bluetooth dongle is detected - SeaBIOS boots to Void Linux and Devuan - PS/2 keyboard and mouse (only combo port, one at a time) - PEG slot - Mini-PCIe WLAN slot Not tested: - eSATA - SPDIF - LEDs: front panel Not working: - Super I/O shows weird temperatures in lm_sensors: CPU -51°C AUX +84°C - Resuming from S3 when root partition is on an USB 3.0 stick (works when it's attached to USB 2.0 or SATA). - DRAM_LED (on vendor firmware, it stays lit if there are DRAM problems) Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85832 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/asus/h61-series/Kconfig M src/mainboard/asus/h61-series/Kconfig.name A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb 11 files changed, 443 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 08e7a22..4c4fd7e 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -60,6 +60,15 @@ select RT8168_SET_LED_MODE select SUPERIO_NUVOTON_NCT6776 +config BOARD_ASUS_P8H67_I_DELUXE + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_4096 + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select NO_UART_ON_SUPERIO + select REALTEK_8168_RESET + select SUPERIO_NUVOTON_NCT6776 + if BOARD_ASUS_H61_SERIES config MAINBOARD_DIR @@ -71,6 +80,7 @@ default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO default "p8h61-m_pro_cm6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 + default "p8h67-i_deluxe" if BOARD_ASUS_P8H67_I_DELUXE config MAINBOARD_PART_NUMBER default "H61M-CS" if BOARD_ASUS_H61M_CS @@ -78,6 +88,7 @@ default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO default "P8H61-M PRO CM6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 + default "P8H67-I DELUXE" if BOARD_ASUS_P8H67_I_DELUXE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -88,6 +99,9 @@ config CMOS_LAYOUT_FILE default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout" +config CBFS_SIZE + default 0x280000 if BOARD_ASUS_P8H67_I_DELUXE + # # These ME partitions need to be whitelisted for correct system # operation. Example issues from removing them include: no serial output diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name index 6db12b4..eee48c0 100644 --- a/src/mainboard/asus/h61-series/Kconfig.name +++ b/src/mainboard/asus/h61-series/Kconfig.name @@ -14,3 +14,6 @@ config BOARD_ASUS_P8H61_M_PRO_CM6630 bool "P8H61-M PRO CM6630" + +config BOARD_ASUS_P8H67_I_DELUXE + bool "P8H67-I DELUXE" diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt new file mode 100644 index 0000000..2bfc9b5 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt @@ -0,0 +1,9 @@ +Category: desktop +Board URL: https://www.asus.com/us/supportonly/p8h67-i%20deluxe/helpdesk_knowledge/ +Release year: 2011 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +ROM IC: W25Q32BV +Flashrom support: y +Internal flashing: y diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default new file mode 100644 index 0000000..e74cec9 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout new file mode 100644 index 0000000..8c6a055 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt new file mode 100644 index 0000000..2e26785 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt Binary files differ diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c new file mode 100644 index 0000000..8510b7f --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN); +} diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads new file mode 100644 index 0000000..d281ae5 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI + HDMI3, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c new file mode 100644 index 0000000..9103226 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, /* DRAM_LED */ + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, /* DRAM_LED */ + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, /* DRAM_LED */ + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, /* GPU_BOOST slider switch */ + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, /* GPU_BOOST slider switch */ + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c new file mode 100644 index 0000000..993767b --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1043848d, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1043848d), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80862805, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80862805), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb new file mode 100644 index 0000000..ef24784 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb @@ -0,0 +1,97 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0 on + subsystemid 0x1043 0x844d inherit + + device ref peg10 on + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "PCIEX16" "SlotDataBusWidth16X" + end + device ref igd on + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pcie_port_coalesce" = "1" + register "usb_port_config" = "{ + {1, 0xb57, 0}, /* USB3_12 (rear USB 3.0 ports) */ + {1, 0xb57, 0}, /* USB3_12 (rear USB 3.0 ports) */ + {1, 0xb57, 1}, /* USB12 (rear USB2 above eSATA, red) */ + {1, 0xb57, 1}, /* USB12 (rear USB2 above eSATA, red) */ + {1, 0x57, 2}, /* USB34 (rear USB2 under PS/2, black) */ + {1, 0x57, 2}, /* USB34 (rear USB2 under PS/2, black) */ + {1, 0xb57, 3}, /* USB3_34 header (front panel USB 3.0) */ + {1, 0xb57, 3}, /* USB3_34 header (front panel USB 3.0) */ + {1, 0x357, 4}, /* USB56 header (front panel USB 2.0) */ + {1, 0x357, 4}, /* USB56 header (front panel USB 2.0) */ + {0, 0xb57, 5}, /* unconnected */ + {0, 0x343, 5}, /* unconnected */ + {1, 0xb57, 6}, /* integrated Bluetooth */ + {0, 0xb57, 6}, /* unconnected */ + }" + device ref hda on # Realtek ALC892 + subsystemid 0x1043 0x848d + end + device ref pcie_rp5 on + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthShort" "WLAN" + end + device ref pcie_rp6 on end # uPD720200 for front panel USB3 + device ref pcie_rp7 on # RTL8111E GbE NIC + chip drivers/net + register "customized_leds" = "0x0c40" + device pci 00.0 on end + end + end + device ref pcie_rp8 on end # uPD720200 for rear USB3 ports + device ref lpc on + register "gen1_dec" = "0x00fc0295" + register "gen2_dec" = "0x00fc0a01" + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end + device pnp 2e.1 off end + device pnp 2e.2 off end # COM1 + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 + irq 0x72 = 0x0c + irq 0xf0 = 0x83 + end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.8 off end + device pnp 2e.9 on # GPIO2-5 + irq 0x30 = 0x0e + irq 0xe0 = 0xef + irq 0xe1 = 0x10 + irq 0xe4 = 0xf7 + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 + irq 0xe7 = 0x01 + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0x01 + io 0x60 = 0x290 + end + device pnp 2e.d off end + device pnp 2e.e off end + device pnp 2e.f on # GPIO push-pull/open drain + irq 0xf0 = 0x9d + end + device pnp 2e.14 off end + device pnp 2e.16 on end # Deep sleep + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0xff + end + end + end + device ref sata1 on + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1f" # 0-3: internal SATA, 4: eSATA + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 12 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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