coreboot-gerrit January 2025

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[M] Change in coreboot[main]: soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup
by Matt DeVillier (Code Review) 23 Jan '25

23 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84343?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup ...................................................................... soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup The Zynq 7000 family of SoCs integrates up to two Cortex-A9 processor cores with FPGA fabric using Xilinx's 7-series architecture. This commit adds the bare minimum support code to compile a rom successfully when the SoC is selected by a board. This code was loosely based on the TI AM335x code, especially the memlayout.ld file. In its current state valid Zynq boot images cannot be produced. CBFS media is not yet supported so only the bootblock is able to run. The easiest way to run this code is to manually load the bootblock ELF into memory over JTAG using OpenOCD. Change-Id: I45aa4e3a11074fa447d4008ac3c96d44f891831c Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84343 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: coreboot org <coreboot.org(a)gmail.com> --- A src/soc/xilinx/Kconfig A src/soc/xilinx/zynq7000/Kconfig A src/soc/xilinx/zynq7000/Makefile.mk A src/soc/xilinx/zynq7000/cbmem.c A src/soc/xilinx/zynq7000/memlayout.ld A src/soc/xilinx/zynq7000/reset.c A src/soc/xilinx/zynq7000/soc.c A src/soc/xilinx/zynq7000/timer.c 8 files changed, 135 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified coreboot org: Looks good to me, approved diff --git a/src/soc/xilinx/Kconfig b/src/soc/xilinx/Kconfig new file mode 100644 index 0000000..95100a0 --- /dev/null +++ b/src/soc/xilinx/Kconfig @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Load all chipsets +source "src/soc/xilinx/*/Kconfig" diff --git a/src/soc/xilinx/zynq7000/Kconfig b/src/soc/xilinx/zynq7000/Kconfig new file mode 100644 index 0000000..3254435 --- /dev/null +++ b/src/soc/xilinx/zynq7000/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only +# +config SOC_XILINX_ZYNQ7000 + bool + default n + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + +if SOC_XILINX_ZYNQ7000 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/xilinx/zynq7000/memlayout.ld" + +endif diff --git a/src/soc/xilinx/zynq7000/Makefile.mk b/src/soc/xilinx/zynq7000/Makefile.mk new file mode 100644 index 0000000..b6b4e1c --- /dev/null +++ b/src/soc/xilinx/zynq7000/Makefile.mk @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_XILINX_ZYNQ7000),y) + +bootblock-y += timer.c +romstage-y += timer.c +ramstage-y += timer.c + +romstage-y += cbmem.c +ramstage-y += soc.c + +bootblock-y += reset.c +romstage-y += reset.c +ramstage-y += reset.c + +endif diff --git a/src/soc/xilinx/zynq7000/cbmem.c b/src/soc/xilinx/zynq7000/cbmem.c new file mode 100644 index 0000000..eb0f0f4 --- /dev/null +++ b/src/soc/xilinx/zynq7000/cbmem.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <commonlib/bsd/helpers.h> + +uintptr_t cbmem_top_chipset(void) +{ + return CONFIG_DRAM_SIZE_MB * MiB; +} diff --git a/src/soc/xilinx/zynq7000/memlayout.ld b/src/soc/xilinx/zynq7000/memlayout.ld new file mode 100644 index 0000000..1ebd0d8 --- /dev/null +++ b/src/soc/xilinx/zynq7000/memlayout.ld @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +SECTIONS +{ + SRAM_START(0x00000000) + BOOTBLOCK(0x00000000, 20K) + FMAP_CACHE(0x00000000+20K, 2K) + CBFS_MCACHE(0x00000000+20K+2K, 8K) + TTB(0x00008000, 16K) + ROMSTAGE(0x00008000+16K, 40K) + + PRERAM_CBFS_CACHE(0x00008000+16K+40K, 20K) + + STACK(0x0001b000, 4K) + SRAM_END(0x30000) + + DRAM_START(0x100000) + RAMSTAGE(0x100000, 2M) + POSTRAM_CBFS_CACHE(0x300000, 32M) +} diff --git a/src/soc/xilinx/zynq7000/reset.c b/src/soc/xilinx/zynq7000/reset.c new file mode 100644 index 0000000..339acb6 --- /dev/null +++ b/src/soc/xilinx/zynq7000/reset.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <reset.h> + +#define SLCR_UNLOCK ((void *)0xF8000008u) +#define SLCR_UNLOCK_KEY 0xDF0D +#define PSS_RST_CTRL ((void *)0xF8000200u) +void do_board_reset(void) +{ + write16(SLCR_UNLOCK, SLCR_UNLOCK_KEY); + write32(PSS_RST_CTRL, 1); +} diff --git a/src/soc/xilinx/zynq7000/soc.c b/src/soc/xilinx/zynq7000/soc.c new file mode 100644 index 0000000..987e437 --- /dev/null +++ b/src/soc/xilinx/zynq7000/soc.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmem.h> +#include <device/device.h> +#include <symbols.h> + +static void soc_enable(struct device *dev) +{ + ram_range(dev, 0, 0, CONFIG_DRAM_SIZE_MB * (uint64_t)MiB); +} + +struct chip_operations soc_xilinx_zynq7000_ops = { + .name = "Xilinx Zynq 7000", + .enable_dev = soc_enable, +}; diff --git a/src/soc/xilinx/zynq7000/timer.c b/src/soc/xilinx/zynq7000/timer.c new file mode 100644 index 0000000..0448aa6 --- /dev/null +++ b/src/soc/xilinx/zynq7000/timer.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <delay.h> +#include <device/mmio.h> +#include <stdint.h> + +#define G_TIMER_COUNTER_0 ((void *)0xF8F00200u) +#define G_TIMER_COUNTER_1 ((void *)0xF8F00204u) +#define G_TIMER_CTRL ((void *)0xF8F00208u) + +#define CLK_PER_USEC 108 + +static inline uint64_t timer_raw_value(void) +{ + uint32_t upper, lower; + do { + upper = read32(G_TIMER_COUNTER_1); + lower = read32(G_TIMER_COUNTER_0); + } while (upper != read32(G_TIMER_COUNTER_1)); + + return (((uint64_t)upper) << 32) | lower; +} + +void init_timer(void) +{ + /* Disable timer */ + write32(G_TIMER_CTRL, read32(G_TIMER_CTRL) & ~0x1); + write32(G_TIMER_COUNTER_0, 0); + write32(G_TIMER_COUNTER_1, 0); + /* Enable timer */ + write32(G_TIMER_CTRL, read32(G_TIMER_CTRL) | 0x1); +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value() / CLK_PER_USEC); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45aa4e3a11074fa447d4008ac3c96d44f891831c Gerrit-Change-Number: 84343 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86110?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0 ...................................................................... Patch Set 2: (5 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/86110/comment/e5d2f019_d6da94f5?usp=e… : PS2, Line 240: `mtk_fsp_romstage.elf` is an ELF format file Remove this sentence, as it's trivial from the file name. https://review.coreboot.org/c/blobs/+/86110/comment/d8ae653e_d9d7af76?usp=e… : PS2, Line 241: include includes https://review.coreboot.org/c/blobs/+/86110/comment/4eb47dbb_02adc169?usp=e… : PS2, Line 244: This is a markdown file, so we don't need to align the text like this. Just 2 spaces (to align with "power switch"). https://review.coreboot.org/c/blobs/+/86110/comment/35bd1cc1_b1abf04f?usp=e… : PS2, Line 245: such as the CVCC (Constant Voltage, Constant Current) : voltage of SRAM. > such as Constant Voltage, Constant Current of SRAM. Note the line length. https://review.coreboot.org/c/blobs/+/86110/comment/03281afa_af622bc5?usp=e… : PS2, Line 256: -1 non-zero -- To view, visit https://review.coreboot.org/c/blobs/+/86110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ice4a51f375a86693674545a7730b16e656c57ac4 Gerrit-Change-Number: 86110 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add PI_IMG firmware v1.0
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86095?usp=email ) Change subject: soc/mediatek/mt8196: Add PI_IMG firmware v1.0 ...................................................................... Patch Set 1: (4 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/86095/comment/18ae52c9_8cfb80a1?usp=e… : PS1, Line 222: mcupm MCUPM https://review.coreboot.org/c/blobs/+/86095/comment/89410b0f_2561511d?usp=e… : PS1, Line 228: Use CBFS to load `pi_img.img`. ``` Load `pi_img.img` from CBFS. ``` https://review.coreboot.org/c/blobs/+/86095/comment/6681ed46_d30071fd?usp=e… : PS1, Line 229: No need to pass other parameters to pi_img Missing `.` File soc/mediatek/mt8196/pi_img.img.md5: https://review.coreboot.org/c/blobs/+/86095/comment/93a8f3dc_c7c31be4?usp=e… : PS1, Line 1: 357c892eea80a341201b9493de177362 Seems incorrect. My result starts with `d0f3`. -- To view, visit https://review.coreboot.org/c/blobs/+/86095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I4b36c928ad194f155442cf0e4314a826cfd3ef68 Gerrit-Change-Number: 86095 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:30:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: symbols: Add REGION() and REGION_END() macros
by Julius Werner (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Yu-Ping Wu. Julius Werner has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86115?usp=email ) Change subject: symbols: Add REGION() and REGION_END() macros ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I'm not really sure what this improves? What's wrong with the existing notation? -- To view, visit https://review.coreboot.org/c/coreboot/+/86115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80275a74a4015e72eaab204982b915e4435a339 Gerrit-Change-Number: 86115 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:26:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Enable RTC
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85979?usp=email ) Change subject: mb/google/rauru: Enable RTC ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7 Gerrit-Change-Number: 85979 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:25:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Shunxi Zhang. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 12: Code-Review+2 (1 comment) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/e9487da0_21d71aeb?us… : PS10, Line 90: config_interface(RG_FQMTR_TCKSEL, FQMTR_DCXO26M_EN | measure_src, : RG_FQMTR_TCKSEL_MASK, RG_FQMTR_TCKSEL_SHIFT); > will update Are you sure we don't need to enable `FQMTR_DCXO26M_EN`? -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:24:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek: Utilize REGION() and REGION_END() macros
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86116?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek: Utilize REGION() and REGION_END() macros ...................................................................... soc/mediatek: Utilize REGION() and REGION_END() macros Change-Id: Iad5a129a558e8902fbfd4adb9c34d9d5e5cba25f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8173/soc.c 2 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86116/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad5a129a558e8902fbfd4adb9c34d9d5e5cba25f Gerrit-Change-Number: 86116 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: symbols: Add REGION() and REGION_END() macros
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86115?usp=email to look at the new patch set (#2). Change subject: symbols: Add REGION() and REGION_END() macros ...................................................................... symbols: Add REGION() and REGION_END() macros Define the REGION() and REGION_END() macros for platform code to reference to the region start and end addresses more easily. Note that memlayout.h also defines macros of the same name, but that's fine, as that header is supposed to be included from memlayout.ld only. Change-Id: Ie80275a74a4015e72eaab204982b915e4435a339 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/include/symbols.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/86115/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80275a74a4015e72eaab204982b915e4435a339 Gerrit-Change-Number: 86115 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the region size for mcufw_reserved
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86108?usp=email ) Change subject: soc/mediatek/mt8196: Correct the region size for mcufw_reserved ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Just a note that this is an RO/RW incompatible change. -- To view, visit https://review.coreboot.org/c/coreboot/+/86108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 Gerrit-Change-Number: 86108 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:11:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: symbols: Add REGION() and REGION_END() macros
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86115?usp=email ) Change subject: symbols: Add REGION() and REGION_END() macros ...................................................................... Patch Set 1: (1 comment) File src/include/symbols.h: https://review.coreboot.org/c/coreboot/+/86115/comment/158beddd_c55610d3?us… : PS1, Line 10: uintptr_t Do you prefer this or `void *`? I believe the most common usage would be `mmu_config_range`, which takes an address of type `void *`. -- To view, visit https://review.coreboot.org/c/coreboot/+/86115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80275a74a4015e72eaab204982b915e4435a339 Gerrit-Change-Number: 86115 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:09:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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