coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Update Touch screen configuration
by Ian Feng (Code Review) 23 Jan '25

23 Jan '25

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86117?usp=email ) Change subject: mb/google/fatcat/var/francka: Update Touch screen configuration ...................................................................... mb/google/fatcat/var/francka: Update Touch screen configuration Correct the GPIO pin(GPP_B18) configuration issue base on schematic. TCHSCR_REPORT_DISABLE(GPP_B18): Low : Enable High : Disable BUG=b:391720235 TEST=Build and boot to OS in francka. Touch screen is workable. Change-Id: Iba26f496176c2e406285df323e3da3e861fa2ffc Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86117/1 diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c index a5d5ad9..8819122 100644 --- a/src/mainboard/google/fatcat/variants/francka/gpio.c +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -86,7 +86,7 @@ /* GPP_B17: SOC_ENVDD2 */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), /* GPP_B18: TCHSCR_REPORT_DISABLE */ - PAD_CFG_GPO(GPP_B18, 0, PLTRST), + PAD_CFG_GPO(GPP_B18, 1, PLTRST), /* GPP_B19: SOC_CNVI_EN# */ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPP_B20: SOC_WWAN_RST# */ diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index fed7294..9d2dd2f 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -200,7 +200,7 @@ register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B08)" register "generic.reset_delay_ms" = "200" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)" register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/86117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba26f496176c2e406285df323e3da3e861fa2ffc Gerrit-Change-Number: 86117 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Disable UFS controller on every boot
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email ) Change subject: soc/intel/alderlake/romstage: Disable UFS controller on every boot ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: may be you can consider reverting https://review.coreboot.org/c/coreboot/+/84974 where I have reactor the UFS disabling to save some Boot time. Should be not much problem of sending UFS disablement across all Boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 02:40:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/corsola: Increase ANX7625 data trail time
by Xin Ji (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Xin Ji has posted comments on this change by Xin Ji. ( https://review.coreboot.org/c/coreboot/+/86101?usp=email ) Change subject: mb/google/corsola: Increase ANX7625 data trail time ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86101/comment/777939d4_02a42792?us… : PS3, Line 10: shorter > too short Acknowledged https://review.coreboot.org/c/coreboot/+/86101/comment/131121c0_70575684?us… : PS3, Line 10: caused > is caused Acknowledged https://review.coreboot.org/c/coreboot/+/86101/comment/d0ef2f08_32afbb6c?us… : PS3, Line 13: enter > entering Acknowledged https://review.coreboot.org/c/coreboot/+/86101/comment/f582290e_74876c24?us… : PS3, Line 15: > So why is +9 correct, and not +11 or +8? This value is migrated from "kukui/panel_anx7625.c". And verified on corsola. -- To view, visit https://review.coreboot.org/c/coreboot/+/86101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Gerrit-Change-Number: 86101 Gerrit-PatchSet: 3 Gerrit-Owner: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 01:56:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/corsola: Increase ANX7625 data trail time
by Xin Ji (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Xin Ji, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86101?usp=email to look at the new patch set (#4). Change subject: mb/google/corsola: Increase ANX7625 data trail time ...................................................................... mb/google/corsola: Increase ANX7625 data trail time Currently, the eDP panel has display shift issue. This issue is caused by too short HS-trail time. Based on hardware design ANX7625 requires more HS-trail time to finish mipi data packet decoding before entering LP mode. So increase HS-trail time to avoid effect of entering LP mode. BUG=id:391304679 BRANCH=corsola TEST=Display is normal on corsola Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Signed-off-by: Xin Ji <xji(a)analogix.corp-partner.google.com> --- M src/mainboard/google/corsola/panel_anx7625.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86101/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Gerrit-Change-Number: 86101 Gerrit-PatchSet: 4 Gerrit-Owner: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Shunxi Zhang (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Shunxi Zhang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 12: Code-Review+1 (1 comment) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/0d963292_875ab196?us… : PS10, Line 90: config_interface(RG_FQMTR_TCKSEL, FQMTR_DCXO26M_EN | measure_src, : RG_FQMTR_TCKSEL_MASK, RG_FQMTR_TCKSEL_SHIFT); > Are you sure we don't need to enable `FQMTR_DCXO26M_EN`? this code : config_interface(RG_FQMTR_DCXO26M_EN, 1, RG_FQMTR_DCXO26M_MASK, RG_FQMTR_DCXO26M_SHIFT); has been enabled FQMTR_DCXO26M_EN already. -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 01:24:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: symbols: Add REGION() and REGION_END() macros
by Julius Werner (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Yu-Ping Wu. Julius Werner has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86115?usp=email ) Change subject: symbols: Add REGION() and REGION_END() macros ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Using REGION(name) makes it easier for (new) developers to find the actual region definition. Hmm... does it? I think it would just make them follow the macro definition to the source but that doesn't really help either. For symbols prefixed with underscores I think there at least exists a lot of precedent among various C code bases to represent linker script symbols that way. I feel like this adds just another macro that confuses things more without really helping tbh. The duplication of having two different macros with the same name in different headers also adds confusion (especially for people using things like cscope which can find definitions of identifiers but don't take the specific header include chains of the file into account). If we think these symbols are too confusing I think it would be better to write some more explicit documentation for memlayout stuff and refer to it from prominent places (e.g. a comment in `<symbols.h>`). -- To view, visit https://review.coreboot.org/c/coreboot/+/86115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80275a74a4015e72eaab204982b915e4435a339 Gerrit-Change-Number: 86115 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: docs/getting-started: Update guide for writing docs
by Alicja Michalska (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Nicholas Chin. Alicja Michalska has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85857?usp=email ) Change subject: docs/getting-started: Update guide for writing docs ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I569862e30fb88a421ad2338aafabeaf3ea76836a Gerrit-Change-Number: 85857 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:55:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/meteorlake: Move CNVi control out of chipset.cb
by Matt DeVillier (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jeremy Soller, Jérémy Compostella, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun, Tim Crawford. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86088?usp=email ) Change subject: soc/intel/meteorlake: Move CNVi control out of chipset.cb ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1 Gerrit-Change-Number: 86088 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:46:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: symbols: Add REGION() and REGION_END() macros
by Yu-Ping Wu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86115?usp=email ) Change subject: symbols: Add REGION() and REGION_END() macros ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I'm not really sure what this improves? What's wrong with the existing notation? 1. Writing `mmu_config_range(REGION(sram), REGION_SIZE(sram))` improves the readability (than `mmu_config_range(_sram, REGION_SIZE(sram))`), as the relationship between `_sram` and `sram` is unclear from the call. 2. Using `REGION(name)` makes it easier for (new) developers to find the actual region definition. 3. Variables starting with `_` look like private ones that shouldn't be exposed. -- To view, visit https://review.coreboot.org/c/coreboot/+/86115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80275a74a4015e72eaab204982b915e4435a339 Gerrit-Change-Number: 86115 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: soc/xilinx/zynq7000: Add UART driver
by Matt DeVillier (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Nicholas Chin. Matt DeVillier has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84344?usp=email ) Change subject: soc/xilinx/zynq7000: Add UART driver ...................................................................... Patch Set 1: (1 comment) File src/soc/xilinx/zynq7000/uart.c: https://review.coreboot.org/c/coreboot/+/84344/comment/db765e72_dcfa9cae?us… : PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > Would it make sense to put this under src/drivers/uart as a common xilinx driver? […] thoughts @nic.c3.14@gmail.com? If you want to do in a follow-up that's fine, just ack and we can merge as-is -- To view, visit https://review.coreboot.org/c/coreboot/+/84344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b845af3f057847d7c5c56615396f946df39b921 Gerrit-Change-Number: 84344 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 00:42:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: coreboot org <coreboot.org(a)gmail.com>

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