coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/birman: Add A/B flashmap for birman
by Patrick Rudolph (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao. Patrick Rudolph has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/85766?usp=email ) Change subject: mb/birman: Add A/B flashmap for birman ...................................................................... Patch Set 5: (1 comment) File src/mainboard/amd/birman_plus/board_glinda_ab.fmd: https://review.coreboot.org/c/coreboot/+/85766/comment/46c4e73f_e208ff92?us… : PS5, Line 5: COREBOOT why is it commented out? -- To view, visit https://review.coreboot.org/c/coreboot/+/85766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I743a3862791c3a36c1e4fca2334cc7dc2703dfb6 Gerrit-Change-Number: 85766 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 Jan 2025 07:43:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: commonlib/dt: Fix incorrect cell properties
by Kapil Porwal (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Julius Werner. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86030?usp=email ) Change subject: commonlib/dt: Fix incorrect cell properties ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Sorry, can you please explain why you want to do this? This reverts exactly the part that CB:85964 w […] The previous patch failed the CQ while building DC. Refer https://crrev/c/6178415 After some debugging, I figured that the old implementation was correct. It was just confusing because of its recursive nature. -- To view, visit https://review.coreboot.org/c/coreboot/+/86030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d360a4cc0a02462a53866bf375e5d4c85177a05 Gerrit-Change-Number: 86030 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 23 Jan 2025 07:40:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Kconfig
by Patrick Rudolph (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Ana Carolina Cabral, Martin Roth, Paul Menzel. Patrick Rudolph has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85493?usp=email ) Change subject: mb/amd/birman_plus: Kconfig ...................................................................... Patch Set 17: (1 comment) File src/mainboard/amd/birman_plus/port_descriptors_glinda.c: https://review.coreboot.org/c/coreboot/+/85493/comment/f433e424_5b944eb0?us… : PS17, Line 176: ENABLE_GBE_BIRMANPLUS why do you need to drop those descriptors when not enabled? Shouldn't the `port_present=0` be sufficient? -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 17 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Thu, 23 Jan 2025 07:31:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Kapil Porwal (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 07:21:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Kapil Porwal (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 07:20:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar. Hello Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86001?usp=email to look at the new patch set (#11). Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... drivers/intel/fsp2_0: Add option to control debug log level using CBFS This commit relies on newly added Kconfig option, USE_CBFS_FILE_OPTION_BACKEND, which allows controlling the FSP debug log level using CBFS options (RAW binary files). The default log-level is setup in coreboot while stitching the CBFS option binaries depending upon the coreboot log-level. Following files will be used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. In absense of these files, the FSP console log-level is determine by calling into fsp_map_console_log_level API. The values in these files should correspond to the FSP_LOG_LEVEL_* enum values. This change allows for more flexibility in controlling the FSP debug log level, especially in cases of debugging silicon firmware issues with a debug AP FW binary. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO CBFS, both the silicon firmware and MRC behave as debug binaries. To verify the presence of both log-level RAW CBFS binaries in the CBFS RO slot, run: ``` sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_ ``` This should output: ``` option/fsp_mrc_debug_level 0x88e40 raw 8 none option/fsp_pcd_debug_level 0x2a7400 raw 8 none ``` Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86001/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86002/comment/b603c012_9bf40556?us… : PS9, Line 9: This commit enables the FSP_DEBUG_LOG_LEVEL_USING_CBFS Kconfig option > Not anymore. Acknowledged https://review.coreboot.org/c/coreboot/+/86002/comment/a37a07a9_8c49e0bf?us… : PS9, Line 22: This capability is particularly useful when debugging issues that require > > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 06:53:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 10: (3 comments) File src/drivers/intel/fsp2_0/include/fsp/debug.h: https://review.coreboot.org/c/coreboot/+/86001/comment/212e0e56_ea9a7968?us… : PS9, Line 71: * no serial log. Otherwise, use below log levels > This text needs to be adjusted to reflect new code. […] Acknowledged https://review.coreboot.org/c/coreboot/+/86001/comment/31d698f8_0afeba33?us… : PS9, Line 81: * If disabled (!HAVE_CBFS_FILE_OPTION_BACKEND), the log levels will be determined by > This should say `If OPTION_BACKEND_NONE` (and should maybe be combined with the text above saying wh […] Acknowledged https://review.coreboot.org/c/coreboot/+/86001/comment/c0c3b98f_30498512?us… : PS9, Line 87: * used for outputting MRC debug messages. > Same stuff for this function. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 06:53:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Paul Menzel, Ronak Kanabar, Subrata Banik. Hello Andrey Petrov, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86001?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+2 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... drivers/intel/fsp2_0: Add option to control debug log level using CBFS This commit relies on newly added Kconfig option, USE_CBFS_FILE_OPTION_BACKEND, which allows controlling the FSP debug log level using CBFS options (RAW binary files). The default log-level is setup in coreboot while stitching the CBFS option binaries depending upon the coreboot log-level. Following files will be used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. In absense of these files, the FSP console log-level is determine by calling into fsp_map_console_log_level API. The values in these files should correspond to the FSP_LOG_LEVEL_* enum values. This change allows for more flexibility in controlling the FSP debug log level, especially in cases of debugging silicon firmware issues with a debug AP FW binary. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO CBFS, both the silicon firmware and MRC behave as debug binaries. To verify the presence of both log-level RAW CBFS binaries in the CBFS RO slot, run: ``` sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_ ``` This should output: ``` option/fsp_mrc_debug_level 0x88e40 raw 8 none option/fsp_pcd_debug_level 0x2a7400 raw 8 none ``` Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86001/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86002?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... soc/intel/pantherlake: Enable FSP debug log level control using CBFS This allows controlling the FSP debug log level using CBFS RAW binary files, providing more flexibility in debugging silicon firmware issues with a debug AP FW binary. The following CBFS files are used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86002/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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coreboot-gerrit January 2025