coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Arthur Heymans (Code Review) 02 Jan '25

02 Jan '25

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... Abandoned not working on this anylonger -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
by Angel Pons (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Alexander Couzens, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Evgeny Zinoviev, Frans Hendriks, Jakub Czapiga, Jeremy Soller, Johnny Lin, Jonathon Hall, Kevin Keijzer, Lean Sheng Tan, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Morgan Jang, Nicholas Chin, Nick Vaccaro, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Werner Zeh. Angel Pons has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/79742?usp=email ) Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/common/lpc.h: https://review.coreboot.org/c/coreboot/+/79742/comment/8d0d8103_44e42b44?us… : PS3, Line 7: LPC_IO_DEC > Much of the needed definitions can actually be found in src/soc/intel/common/block/lpc/lpc_def.h. […] This macro could be renamed, e.g. `LPC_IO_WINDOW` -- To view, visit https://review.coreboot.org/c/coreboot/+/79742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05a7b1e6d0bafcd3c376b8f8dc4acce0f2629a7 Gerrit-Change-Number: 79742 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:37:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Angel Pons (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Keith Hui, Riku Viitanen. Angel Pons has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 12 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:35:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Jayvik Desai (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Paul Menzel, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Kapil Porwal, Paul Menzel, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85326?usp=email to look at the new patch set (#18). Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... ec/google/chromeec: Add debug timestamp for host EC commands Improve host EC command debugging with timestamps and duration for better analysis, this feature can be enabled by selecting the config EC_GOOGLE_CHROMEEC_HOST_CMD_DEBUG. BUG=b:382551616 TEST=Brox/lotso device successfully built and booted. Debug messages confirmed in device logs only when the specific configuration is selected. Sample print: "EC HOST CMD Duration: 661 us, Command: 0x4b, version: 0x2" Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/ec_lpc.c 2 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85326/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 18 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Patrick Rudolph (Code Review) 02 Jan '25

02 Jan '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... soc/intel/xeon_sp: Add fix for DPR silicon bug On first batch of Intel Xeon-SP 10nm CPU the DPR register is affected by a silicon bug, where the TOP bits read as 0, which isn't possible according to the EDS. Currently the code also assumes that it's never zero and calculates the DPR size using the assigned address. By using 0 as TOP address it overflows and breaks boot due to an overly large MMIO window. On previous CPUs and newer CPUs the assumption is still correct and the DPR TOP bits never read as 0. Add a check for the silicon bug and use TSEG base like it's already done on snowridge, which is also a 10nm Xeon CPU affected by the same bug. Fixes negative size being calculated for DPR. Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/snowridge/systemagent.c M src/soc/intel/xeon_sp/uncore.c 2 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85829/1 diff --git a/src/soc/intel/snowridge/systemagent.c b/src/soc/intel/snowridge/systemagent.c index 2663dc0..f35ba9e 100644 --- a/src/soc/intel/snowridge/systemagent.c +++ b/src/soc/intel/snowridge/systemagent.c @@ -38,7 +38,11 @@ { union dpr_register dpr = { .raw = pci_read_config32(dev, DPR) }; *size = dpr.size * MiB; - /* DPR base is read as 0s so it is calculated based on the assumption that DPR is below TSEG. */ + /* + * Silicon bug: + * DPR top is read as 0s so it is calculated based on the assumption + * that DPR is below TSEG. + */ *base = sa_server_get_tseg_base() - *size; return true; } diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 85e45db..d4e4b08 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/msr.h> @@ -144,13 +145,27 @@ { const uintptr_t cbmem_top_mb = ALIGN_UP(cbmem_top(), MiB) / MiB; union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + uintptr_t base; + size_t size; /* The DPR lock bit has to be set sufficiently early. It looks like * it cannot be set anymore after FSP-S. */ dpr.lock = 1; dpr.epm = 1; - dpr.size = dpr.top - cbmem_top_mb; + + /* + * Silicon bug on 1st gen 10nm Xeon-SP: + * DPR top is read as 0s so it is calculated based on the assumption + * that DPR is below TSEG. + */ + if (!dpr.top) { + smm_region(&base, &size); + + dpr.size = base - cbmem_top_mb; + } else { + dpr.size = dpr.top - cbmem_top_mb; + } pci_write_config32(dev, VTD_LTDPR, dpr.raw); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/power_limit/power_limit.c: https://review.coreboot.org/c/coreboot/+/85606/comment/d5d0aae3_de83519f?us… : PS5, Line 97: msr = rdmsr(MSR_PKG_POWER_LIMIT); > Maybe one more thing... […] ACK.Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 6 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:27:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Angel Pons (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin, Riku Viitanen. Angel Pons has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 5: (1 comment) Patchset: PS2: > Yes, I am referring to PCIe add-in cards with this chip, those may possibly need to be put in AHCI m […] Also, the Z97 Extreme6 doesn't select this Kconfig, but has two ASMedia SATA controllers of this kind. They're behind a PCIe switch, though, so selecting the Kconfig wasn't necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:14:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Philipp Groß <jeangrande(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Angel Pons (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin, Riku Viitanen. Angel Pons has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 5: (1 comment) File src/drivers/asmedia/asm1061.c: https://review.coreboot.org/c/coreboot/+/85816/comment/91adccc6_f0d96a58?us… : PS5, Line 40: 0x0611, /* ASM1061 SATA IDE Controller */ Does the device ID change when switching to SATA mode? -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Angel Pons (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin, Riku Viitanen. Angel Pons has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS2: > I assume Angel is talking about those: https://www.ebay. […] Yes, I am referring to PCIe add-in cards with this chip, those may possibly need to be put in AHCI mode as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:12:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jan Philipp Groß <jeangrande(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP-M params for debug message control
by Kapil Porwal (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85827?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP-M params for debug message control ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2916ce82133058464d20eed327de7c7288e78a4 Gerrit-Change-Number: 85827 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 10:03:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025