coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Update Touch screen configuration
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86117?usp=email ) Change subject: mb/google/fatcat/var/francka: Update Touch screen configuration ...................................................................... mb/google/fatcat/var/francka: Update Touch screen configuration Correct the GPIO pin(GPP_B18) configuration issue base on schematic. TCHSCR_REPORT_DISABLE(GPP_B18): Low : Enable High : Disable BUG=b:391720235 TEST=Build and boot to OS in francka. Touch screen is workable. Change-Id: Iba26f496176c2e406285df323e3da3e861fa2ffc Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86117 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Jayvik Desai: Looks good to me, approved Pranava Y N: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c index a5d5ad9..8819122 100644 --- a/src/mainboard/google/fatcat/variants/francka/gpio.c +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -86,7 +86,7 @@ /* GPP_B17: SOC_ENVDD2 */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), /* GPP_B18: TCHSCR_REPORT_DISABLE */ - PAD_CFG_GPO(GPP_B18, 0, PLTRST), + PAD_CFG_GPO(GPP_B18, 1, PLTRST), /* GPP_B19: SOC_CNVI_EN# */ PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPP_B20: SOC_WWAN_RST# */ diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index fed7294..9d2dd2f 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -200,7 +200,7 @@ register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B08)" register "generic.reset_delay_ms" = "200" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)" register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/86117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba26f496176c2e406285df323e3da3e861fa2ffc Gerrit-Change-Number: 86117 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86098?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd ...................................................................... mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd Modify the overridetree.cb configuration to make the SSD effective. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I5d9219e0964ce1f2c8be6a37f93ead04943421d9 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/felino/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 28072d5..d401ed2 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -184,13 +184,13 @@ device ref pcie_rp9 on register "pcie_rp[PCIE_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, + .clk_src = 0, + .clk_req = 0, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "is_storage" = "true" - register "srcclk_pin" = "1" + register "srcclk_pin" = "0" device generic 0 on end end end # Gen5 SSD -- To view, visit https://review.coreboot.org/c/coreboot/+/86098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d9219e0964ce1f2c8be6a37f93ead04943421d9 Gerrit-Change-Number: 86098 Gerrit-PatchSet: 2 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption t...
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86105?usp=email ) Change subject: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready" ...................................................................... Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready" This default configuration caused a problem where USB devices connected behind a powered hub and/or Servo v4.1 were not detected. Reverting this change restores the previous behavior where Trace Hub and DCI are disabled by default, resolving the USB detection issue. BUG=b:384453901 TEST=Able to boot google/fatcat using USB storage behind servo v4.1 This reverts commit 1ed186fbff84386e0196dd30dd7bc89b8fec2cec. Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86105 Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Bora Guvendik: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Pranava Y N: Looks good to me, approved Jamie Ryu: Looks good to me, approved Gaggery Tsai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 4f6f658..dde401b 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -95,7 +95,6 @@ select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP - select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION -- To view, visit https://review.coreboot.org/c/coreboot/+/86105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d Gerrit-Change-Number: 86105 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add platform debug option for FSP
by Subrata Banik (Code Review) 23 Jan '25

23 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86104?usp=email ) Change subject: soc/intel/pantherlake: Add platform debug option for FSP ...................................................................... soc/intel/pantherlake: Add platform debug option for FSP Previously, DCI was enabled unconditionally, which could interfere with the USB data path when connected behind a powered hub and/or servo v4.1 debug connector. This patch sets DciEn parameter based on the selected platform debug option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is set to 0. BUG=b:384453901 TEST=Able to boot google/fatcat. Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86104 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: Jamie Ryu: Looks good to me, approved build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved Bora Guvendik: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 5846037..e879fad 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -121,6 +121,23 @@ | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, }; +/* Platform Debug Option using HW interface + * + * 0: Disabled, + * 2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix, + * 4: Enabled Trace ready: TraceHub is enabled and allowed S0ix, + * 6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional + * low power state, + * 7: User needs to configure Advanced Debug Settings manually. (only applicable for devices + * with BIOS Setup Menu option present. + */ +enum platform_hw_debug_option { + HW_DEBUG_DISABLE = 0, + HW_DEBUG_TRACEHUB_ACTIVE = BIT(1), + HW_DEBUG_TRACEHUB_READY = BIT(2), + HW_DEBUG_TRACEHUB_POWEROFF = BIT(2) | BIT(1), +}; + /* * As per definition from FSP header: * - [0] for IA diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 033c4ea..2bb4d21 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -253,7 +253,17 @@ m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT; m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); - m_cfg->DciEn = 1; + + switch (CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT) { + case HW_DEBUG_TRACEHUB_ACTIVE: + case HW_DEBUG_TRACEHUB_READY: + case HW_DEBUG_TRACEHUB_POWEROFF: + m_cfg->DciEn = 1; + break; + case HW_DEBUG_DISABLE: + m_cfg->DciEn = 0; + break; + } } static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/86104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Gerrit-Change-Number: 86104 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption t...
by Pranava Y N (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Subrata Banik. Pranava Y N has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86105?usp=email ) Change subject: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d Gerrit-Change-Number: 86105 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 10:14:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add platform debug option for FSP
by Pranava Y N (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Subrata Banik. Pranava Y N has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86104?usp=email ) Change subject: soc/intel/pantherlake: Add platform debug option for FSP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Gerrit-Change-Number: 86104 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 10:13:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat/variants/fatcat: Enable BT audio offload
by Naveen M (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Uday Bhat. Naveen M has posted comments on this change by Uday Bhat. ( https://review.coreboot.org/c/coreboot/+/86121?usp=email ) Change subject: mb/google/fatcat/variants/fatcat: Enable BT audio offload ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id68667d674386cf9e6abc066a4637ee055a967f3 Gerrit-Change-Number: 86121 Gerrit-PatchSet: 1 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 10:12:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Update Touch screen configuration
by Pranava Y N (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Ian Feng, Kapil Porwal. Pranava Y N has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86117?usp=email ) Change subject: mb/google/fatcat/var/francka: Update Touch screen configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba26f496176c2e406285df323e3da3e861fa2ffc Gerrit-Change-Number: 86117 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 10:12:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cmn/cnvi: Fix scope of CFLR ACPI method
by Sean Rhodes (Code Review) 23 Jan '25

23 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86092?usp=email ) Change subject: soc/intel/cmn/cnvi: Fix scope of CFLR ACPI method ...................................................................... soc/intel/cmn/cnvi: Fix scope of CFLR ACPI method When the CFLR method was added, it was inadvertently put outside of the scope of the CNVW device. Move CFLR under CNVW, and adjust the method/ variable references as needed. TEST=boot linux, dump ACPI, verify no unknown methods or objects related to the CNVW device. Change-Id: I7065e24626b2f763868909b8f85a8f18b4cc229b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86092 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: Cliff Huang: Looks good to me, approved build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 301fb3a..964aa17 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -189,7 +189,7 @@ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); { - acpigen_emit_namestring("^CFLR"); + acpigen_emit_namestring("CFLR"); acpigen_write_store_int_to_namestr(1, "PRRS"); @@ -338,26 +338,26 @@ acpigen_write_method("_DSW", 3); acpigen_pop_len(); - acpigen_write_scope_end(); - /* * Method (CFLR, 0, NotSerialized) * { - * If (^CNVW.WFLR == One) + * If (WFLR == One) * { - * ^CNVW.WIFR = One + * WIFR = One * } * } */ acpigen_write_method("CFLR", 0); { - acpigen_write_if_lequal_namestr_int("^CNVW.WFLR", 1); + acpigen_write_if_lequal_namestr_int("WFLR", 1); { - acpigen_write_store_int_to_namestr(1, "^CNVW.WIFR"); + acpigen_write_store_int_to_namestr(1, "WIFR"); } acpigen_pop_len(); } acpigen_pop_len(); + + acpigen_write_scope_end(); } static struct device_operations cnvi_wifi_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/86092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7065e24626b2f763868909b8f85a8f18b4cc229b Gerrit-Change-Number: 86092 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/cmn/cnvi: Drop CNIP ACPI method
by Sean Rhodes (Code Review) 23 Jan '25

23 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86091?usp=email ) Change subject: soc/intel/cmn/cnvi: Drop CNIP ACPI method ...................................................................... soc/intel/cmn/cnvi: Drop CNIP ACPI method This method is used in the Intel/AMI reference code to verify that the device is present (vendor ID != 0xFFFFFFFF), but that's neither used nor needed here, as coreboot only generates SSDT code for devices which are actually present. TEST=build/boot Linux, verify no ACPI issues after dropping Change-Id: Ib60c48852923e965620f4eee6a886c8c0f5c1783 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86091 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 0 insertions(+), 25 deletions(-) Approvals: Sean Rhodes: Looks good to me, approved build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 5e75f6d..301fb3a 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -358,31 +358,6 @@ acpigen_pop_len(); } acpigen_pop_len(); - -/* - * Method (CNIP, 0, NotSerialized) - * { - * If (^CNVW.VDID == 0xFFFFFFFF) - * { - * Return (Zero) - * } Else { - * Return (One) - * } - * } - */ - acpigen_write_method("CNIP", 0); - { - acpigen_write_if_lequal_namestr_int("^CNVW.VDID", 0xffffffff); - { - acpigen_write_return_integer(0); - } - acpigen_write_else(); - { - acpigen_write_return_integer(1); - } - acpigen_pop_len(); - } - acpigen_pop_len(); } static struct device_operations cnvi_wifi_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/86091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib60c48852923e965620f4eee6a886c8c0f5c1783 Gerrit-Change-Number: 86091 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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