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Change subject: mb/google/brya/baseboard/trulo: Disable GPIO dynamic clock gating
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Use ACPI to store and restore it?
this is more over for ISH communication at runtime after booted to OS, therefore, we might need to keep the advanced GPIO PM feature disabled for later use case as well.
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Change subject: devicetree.cb: Use a macro to make IO genx_dec more comprehensible
......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/common/lpc.h:
https://review.coreboot.org/c/coreboot/+/79742/comment/fa2c8900_939a9559?us… :
PS3, Line 7: LPC_IO_DEC
> This conflicts with the some of the `soc/intel/*/include/soc/lpc.h` and `sb/intel/*/i82801*x. […]
Much of the needed definitions can actually be found in src/soc/intel/common/block/lpc/lpc_def.h. However it lacks a macro to build the value to finally go into the register, which I suppose this patch is meant to provide.
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Change subject: mb/asus/p8x7x-series: Streamline devicetree configs
......................................................................
Patch Set 3: Code-Review+2
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Hello Angel Pons, Jan Philipp Groß, Riku Viitanen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Riku Viitanen, Verified+1 by build bot (Jenkins)
Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061
......................................................................
drivers/asmedia: Add code to enable AHCI for ASM1061
The ASMedia ASM1061 seems to default to IDE mode, which seems to be the
source of payloads and Linux not recognizing/booting from drives
connected to it. From the behaviour of vendor firmware on the ASRock Z87
Extreme 4, the mode can be changed by setting the PCI Subclass register
to either 0x06 (SATA controller) or 0x01 (IDE controller). This register
seems to be read only, but can be unlocked for writing by setting bit 2
at offset 0xEC in the PCI config space.
Since the ASMEDIA_ASPM_BLACKLIST driver already existed and only matched
the ASM1061, rename it to ASMEDIA_ASM1061 and add the AHCI mode setting
code to it. To maintain consistency with chipset SATA ports, this is
also configurable through the existing sata_mode CMOS option with the
default set to AHCI.
Tested on the ASUS Maximus VI Gene.
Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M src/drivers/asmedia/Kconfig
M src/drivers/asmedia/Makefile.mk
A src/drivers/asmedia/asm1061.c
D src/drivers/asmedia/aspm_blacklist.c
M src/mainboard/asrock/b75pro3-m/Kconfig
M src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
M src/mainboard/asrock/h77pro4-m/Kconfig
M src/mainboard/asus/h61-series/Kconfig
M src/mainboard/asus/p8x7x-series/Kconfig
9 files changed, 57 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85816/5
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Change subject: mb/asus/p8x7x-series: Streamline devicetree configs
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85797/comment/b57d3b07_f14d213b?us… :
PS2, Line 7: Streamline DT PCIe configs
> Maybe something like "Streamline devicetree configs" or "Clean up devicetree devices"? Yes, all the […]
Done
File src/mainboard/asus/p8x7x-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85797/comment/a2ef927d_82a32a71?us… :
PS2, Line 35: device ref pci_bridge off end
> Can also be removed, defaults to off in chipset. […]
Done
https://review.coreboot.org/c/coreboot/+/85797/comment/60bd04e5_5a3500df?us… :
PS2, Line 37: device ref sata2 off end # SATA (Legacy)
> Can also be removed, defaults to off in chipset. […]
Done
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Hello Nicholas Chin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: mb/asus/p8x7x-series: Streamline devicetree configs
......................................................................
mb/asus/p8x7x-series: Streamline devicetree configs
Drop PCI(e) devices from devicetree that remain off or unchanged from
chipset defaults.
TEST=Timeless binaries did not change across entire family.
Change-Id: I4feb88a78f72952bed049505073aed00d2120df3
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/devicetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
5 files changed, 0 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85797/3
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Change subject: mb/asus/p8x7x-series: Streamline DT PCIe configs
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85797/comment/64b1b4ee_cc3f845f?us… :
PS2, Line 7: Streamline DT PCIe configs
Maybe something like "Streamline devicetree configs" or "Clean up devicetree devices"? Yes, all the devices are logical PCI devices, but at least to me "PCIe configs" sounds more like something specific to the pcie_rp* devices.
File src/mainboard/asus/p8x7x-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85797/comment/44c88b7f_cb6cd62b?us… :
PS2, Line 35: device ref pci_bridge off end
Can also be removed, defaults to off in chipset.cb
https://review.coreboot.org/c/coreboot/+/85797/comment/5ff7dae0_8d099685?us… :
PS2, Line 37: device ref sata2 off end # SATA (Legacy)
Can also be removed, defaults to off in chipset.cb
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Change subject: mb/asus/p8x7x-series: Drop unused MRC devicetree setting
......................................................................
Patch Set 2: Code-Review+2
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Change subject: cpu/x86/64bit: Install extended page tables in BSS
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85806/comment/cf69b14a_0d55b95b?us… :
PS3, Line 9: support
support*s*
https://review.coreboot.org/c/coreboot/+/85806/comment/82026cdd_e80b3650?us… :
PS3, Line 21:
Maybe add the new log messages?
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